SU1251079A1 - Device for servicing interrogations - Google Patents

Abstract

The invention, designed to pass the request signals to the device outputs in the order of their arrival, to the inputs relates to the field of computer technology. The aim of the invention is to reduce the amount of equipment. The device contains N-1 group of priority blocks, the first group of AND elements, containing N elements AND, two OR elements, (N + 1) - bit ring shift register, pulse generator, delay element, AND element, second group of elements I. 1 silt (L g l (0

Description

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The invention relates to an acquiring technique — and is used to control the access of several active devices to one common resource in the order of time the questions arrived. The device can be used by JB automated control systems for complex power plants, for example, MHD generators.

The purpose of the invention is to reduce the amount of equipment.

The drawing shows the functional diagram of the device.

The device contains a circular shift register 1, a group of elements AND 2, (N-1) group of priority blocks 3, where N is the number of sources of requests, a group of elements AND 4, elements OR 5 and 6, a delay element 7, element AND 8, a generator 9 impulses, request 10. and installation 11 inputs, outputs 12.

Each i is a group of blocks 3, where, (N-I), contains i two-input priority blocks 3.

The device works as follows.

In the absence of signals to query inputs 10 signals at the outputs of the device 12 are also absent. The W-pulse of the initial setup, which arrives at output 12, sets the N first bits of the ring register 1 to one state, and the (N + I) -th bit to zero. Since the outputs of the first N bits of the ring register 1 are connected to the inputs of the And 2 elements, when the inquiry signals arrive at the inputs 10, they will pass to the outputs of the corresponding And 2 elements.

The request signal, received at the J-M input 10 of the device (), from the output of the corresponding element And 2 goes to the first inputs of the j-x priority block 3 in groups starting at the j-th and the second inputs of all blocks of the 3 (-1) -th group.

If the arising request signal is the first one in time, then it Passes to the corresponding outputs of all two-input priority blocks 3 associated with it and triggers the corresponding AND 4, which passes the request signal to the output device. The second request signal passes to the outputs (N-l) -ro of block 3

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the third is at the outputs (N-2) -x of blocks 3, etc. As a result, the second and subsequent request signals do not trigger the corresponding

The 5 elements AND 4 and at the outputs 5 of the device do not appear.

After removing the first request signal from the request input 10, blocking the passage of the request signals from the (N-l) -x priority blocks 3 is removed and the second request signal passing to the device output through the corresponding two-input priority blocks 3 is allowed.

5 The second signal passes through (N-1) blocks 3 and triggers the corresponding element AND 4.

Thus, if the arrival of signals at the request inputs is 10 times 20 in time, the order of their arrival is recorded by means of priority blocks 3 and saved when sending requests to the outputs 12.

With the simultaneous occurrence of three

25 or more signals from the request can arise a situation where the signals at the outputs of two-input priority schemes do not cause a single AND 4 element of the first group to be activated. AT

30 in this case, the signal at the output of the element OR 6 is absent, which leads to the opening of the element, AND 8, and the shift input of the cyclic register I receives pulses from the generator 9.

J5 As a result, the zero value is sequentially shifted by register 1 bits and, therefore, the And 2 elements are closed. This process. is equivalent to the separation of requests in time and will lead to the passage of one of the request signals to the output 12 of the device. At the output of OR 6, a high level signal is generated, which f ry closes the element AND 8 and sets the ring register 1 to its original state.

Element AND 8 transmits the shift pulses to the input of the ring register 1 when there are requests for inputs (the OR element 3 has no signals at the device outputs (the OR element 6 is closed). Element 7 ensures the delay of the register shift signals during the passage of the next request signal from the inputs of the priority block 3 to the output of the element OR 6.

As element 7, digital delay elements can be used with synchronization from oscillator 9. As blocks 3, any known two-input priority schemes can be used.

Claims (1)

Invention Formula The pSTs service unit contains a group of N elements AND, where N is the number of sources of requests and N-1 is a group of priority blocks, the number of priority blocks in the group is the group number and the inputs j-ro (, N) of the AND element are connected respectively with the first inputs of j-priority blocks of Kx groups, where K j (N-1), and with the second inputs of priority blocks (d-1) -th group, and the outputs of the And elements of the first group are the outputs of the device, characterized by that, in order to reduce the amount of equipment, the device contains two elements OR, W, IS: five  ABOUT t5 20 five (N + 1) -shift shift register, pulse generator, delay element, AND element and second AND group, the first inputs of which are the device's request inputs, and the output of the second group's j-rp element AND to the first inputs of the priority priority blocks jx Of the second group, with the second inputs of the (jl) group and with the corresponding input of the first element OR whose code is connected to the first direct input of the AND element, and the second direct input is connected to the output of the pulse generator, the output of the AND element delay connected to the shear input m shift register vghody first N bits of the ring shift register connected to the second inputs of the corresponding AND gates of the second group, and adjusting the input connected to the inverse input element Nick output of the second OR gate, whose inputs-are connected to respective outputs of AND gates of the second group. ov ; Editor T. Mitejko Compiled by Mikutsky .Techred I.Gaidos Proofreader I.Musk Order 4412/46 Circulation 671 Subscription VNIKLI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Rauyska nab. 4/5 “Production and printing company, Uzhgorod, Projecto st., 4