SU1128243A2 - Device for exchanging data between control computer and controlled processes - Google Patents

Abstract

DEVICE FOR EXCHANGE OF CONTROL COMPUTERS OF COMPUTERS WITH OBJECTS OF CONTROL on auth.St. No. 783780, differing in that, in order to expand the class of monitored objects, a control loop control unit and a response decryption unit are inserted into the device, with the first and second inputs of the control loop and response decryption block of the control unit information and the control input of the device, and the third inputs, respectively, to the second output of the control information receiving block and the output of the time interval of the control signals, the output of the decryption unit response connected to the fourth input of the control signal control unit and the control cycle control unit, the first output of the control output unit connected to the fifth input, and the second and third outputs, respectively, to the enable input of the information collection unit and the output signal of the device cycle end, the cycle control unit control contains four elements And, a group of amplifiers, transmitters, a counter, a register, a trigger, a comparison circuit and a group of elements I-ШШ, with the first and second inputs of the first element And and information the ion input of the register is the third, fourth, and second inputs of the control loop control unit respectively, the register output group is connected to the first group of inputs of the comparison circuit, the output of which is connected to the trigger reset input, and the second group of inputs to the counter output group and the first inputs the corresponding AND-OR groups, the second inputs of which are connected to the i direct output of the trigger and the first inputs of the second and third elements 1B AND, and the third inputs to the inverse output of the trigger and the first input of the fourth elements Ta And, the outputs of the third and fourth elements And are respectively the first and third outputs of the cycle control unit, the second input of the second element And is connected to the output of the first element And the clock input 0 X of the counter, the reset input of which is connected to the output of the third element And, d fourth the inputs of the AND-OR. group, the synchronization input of the controller,: the setup input of the trigger, and the second inputs of the third and fourth elements, AND form the first input of the cycle control unit, the output of the second element, AND, the right of the trigger and output rows of the AND-OR group are connected to the inputs of respective amplifiers, transmitters, the outputs of which form the second output of the control unit cycle.

Description

The invention relates to computer technology and can be used in automated systems for controlling digital and analog devices, as well as in automated process control systems, at which the instant of the arrival of response reactions occurs at some point in time when a target state appears at the output. .

According to the main auth. No. 783780, a device for exchanging a control computer with control objects is known, comprising a control information receiving unit, the input of which is the control input of the device, and the input and output are respectively connected to information and address inputs of the information collection unit, and the intermediate code memories the time of issuing and receiving, the exchange type control node and the reference frequency generator, the output of which is connected to the input of the counter, the output of which is connected to the FIRMWith the inputs of the comparison circuit, the second inputs of which are connected to the outputs of interim memory of the issuance and reception time codes, and the outputs, respectively, to the inputs of the drivers, the time of the control and strutting signal intervals, the outputs of which are respectively connected to the first inputs of the control signals and the control information receiving unit, the second input of which is control inputs of the device, and the third input is connected to the first output of the control unit of the exchange mode, the second output of which is connected to the second input of the control signal block, the first output of which is control The second output is connected to the fourth input of the control information receiving unit, the output of which is connected to the control input of the information collection unit, the first output of which is the information output of the device, and the second output connected to the third input of the local area: the main control signals Cl} A disadvantage of the known device is a limited class of control objects (OK) and a larger volume.

buffer memory. In particular, this device eliminates the possibility of conjugation with the OC, which functions autonomously in real time and requires

when exchanging information, waiting for OK to issue answers due to the fact that autonomously functioning OK, for example, controlled generators, during the E verification process, the control information from a certain point in time determined by the processes proceeding in the OK (setting the digital node to its initial state , setting the desired temperature, pressure, etc. in the process).

Data entering the information collection unit from the OQ prior to the establishment of the required state is, as a rule, uninformative, which leads to increased demands on the volume of the buffer memory.

The purpose of the invention is to expand the class of controlled objects and reduce the amount of buffer memory of the information collection unit.

 The goal is achieved by the fact that the control cycle control unit and the response decryption unit are entered into the device, with the first and second inputs of the control cycle control unit and the response decryption unit respectively connected to the output of the control information receiving unit and the control input of the device, and the third inputs corresponding to the second output of the control information receiving unit and the output of the driver of the time intervals of the control signals, the output of the response decryption unit is connected to the fourth inputs of the signal unit the control unit and the control cycle control unit, first by the output of the control signal unit connected to the PYATS4A input, and the second and third outputs, respectively, to the enable input of the information collection unit and the output of the device loop termination signal, the control cycle control unit contains four elements and a group amplifiers, transmitters, a counter, a register, a trigger, a comparison circuit, and a group of AND-OR elements, with the first and second inputs of the first AND element and the information input of the register being tert The third, fourth, and second inputs of the control cycle control unit, the register output group is connected to the first group of inputs of the comparison circuit, the output of which is connected to the trigger reset input, and the second group of inputs to the group, the counter outputs and the first inputs of the corresponding elements AND-OR the groups whose second inputs are connected to the forward trigger output and the first inputs of the second and third And elements, and the third inputs to the inverse output of the trigger and the first input of the fourth And element, the outputs of the third and fourth elements of And are Respectively, the first and third outputs of the cycle control unit, the second input of the second element AND is connected to the output of the first element AND and the clock input of the counter, the reset input of which is connected to the output of the third element AND, the fourth inputs of the AND-OR group, the synchronizing input of the register the trigger input and the second inputs of the third and fourth elements And form the first input of the cycle control unit, the output of the second element AND, the direct output of the trigger and the outputs of the AND-OR group elements are connected to the inputs of the corresponding amplifiers The switches are group switches whose outputs form the second output of the cycle control block. . FIG. 1 shows a block diagram of the proposed device j in FIG. 2-7, functional diagrams of a control signal output unit, a control information receiving unit, an information collection unit, an exchange type control unit, a response decryption unit, and a cycle control control unit. The device contains a block 1 of control signals, a block of receiving control information 2, a block of collecting information 3, a block of receiving control information 4, a comparison circuit 5 and 6, a counter 7, an intermediate memory 8 of issue time codes, an intermediate memory 9 of reception time codes , shaper 10 time slots of control signals, shunting 1; spruce 11 time intervals of strobe signals, shaper 12 of the reference frequency, node 13 control of exchange type, response decryption block 14, OK 15, control computer 16, cycle control block 17 of control. Block 4. receiving control information is designed to receive and transmit control information from computer 16, and block 1 is for receiving control information on the OK 15. The functional diagram of block 1 depends on the class OK. For example, to monitor digital type OK 15, block 1 contains a key 18, a comparison node 19 and a trigger 20 in each channel (Fig. 2). Block 2 is designed to receive monitoring information from the OK 15 or information from block 1 to conduct self-control of the device . Unit 2 performs reception of information in accordance with the exchange diagram, performs sign and time gating, and contains in each channel (Fig. 3) a register 21 and an I or OR element. 22.. Block 3 of information collection consists of two nodes of RAM 23 and 24 (Fig. 4), the first of which stores arrays of test information transmitted through block 1 to OK 15, and the second to the answers (reactions) OK 15 that enter the device through block 2. The exchange type control node 13 contains (Fig. 5) registers 25 and 26, a decoder 27 and a trigger 28. The response decryption unit 14 is designed to decrypt the OK 15 state by comparing the actual object reduction with the reference one and contains (Fig. 6 ) Comparison node 29, switch 30, registers 31 and 32. Comparison node 29 consists of elements 33-37, triggers 38-41 and the element NO 42. The control loop control block 17 contains (FIG. 7) elements AND 43-46, register 47, counter 48, comparison circuit 49, trigger 50, group OR1 51 elements, amplifiers, transmitters 52, 53 and 54 groups. The drawings also show busbars 55-70 connections between the units of the device. The device works as follows. Previously, prior to monitoring, the verification program is entered into the memory of the computer 16. When it is executed in memory of block 3, intermediate memories 8 and 9, into registers of driver 12, node 13 and block 14, the record gets information with which the device is configured to control or monitor a particular object connected to the device. The formers 10 and 11 generate pulses with predetermined time intervals, the discreteness of which changes depend on 5. qacTOTjii oscillations of the reference generator of the former 12, which starts the counter 7. At the moments of comparison, the counter codes 7 and the time codes received the intermediate memories 8 and 9, the circuits 5 and 6 of the comparison produce control pulses that trigger the formers 10 and 11, and depending on the type of OK 15, pulses are generated with the required timing diagram for the output groups of block 1 and for the groups m input unit 2. Node 13 provides vschachu OK 15 or receiving it from the information provided in a parallel or series code (in the form of pulses or potentials). Block 14 is designed to compare information obtained from the output of block 2 with the information expected at the output of block 2 when a certain state occurs in OK 15. This state may be, for example, a certain temperature in the process. In digital devices, such a state can be the initial position of the memory elements (e.g., a counter without setting inputs). The operation of the device during monitoring OK 15, in which the time of receipt of responses is not predetermined in advance, occurs as follows. Unit 1, in accordance with the tuning information, provides the control actions of the OK 15 with the required timing diagram for the input groups. Key 18 provides OK 15 and a block of control signals with levels of logic 1 or logic O. The signal amplitude of logic 1 is determined by the voltage of the source (Fig. 2). The control of unit 1 is implemented by registers 25 (impulse inputs) and 26 (input / output switching) of node 13 (FIG. 5). If a register 26 is present in this bit, the logical O key 18 of the corresponding block 1 is in the state state. In this case, the OK 15 view connected to the block channel is an output, and the information from the OK 15 goes to block 2. When monitoring digital devices requiring initial installation, the block can input to the groups of inputs a rotating control signal sequence. At the same time, before the appearance of the required combination of responses at the outputs of the OK 15, they are not recorded in the memory of block 3. Recording in block 3 is prohibited by the output signal of block 14. The signal at the output of block 14 appears only in the case that OK 15 is set to the required state. The implementation of block 14. (Fig. 6) allows monitoring of autonomously functioning objects in real. nominal time scale at frequencies determined by the control algorithm, and not at frequencies determined by the speed of the exchange of the control computer with the units of the device. The signal at the output of block 14 is used / -. .. is used to control unit 1 to terminate the repeating sequence of control signals and to continue monitoring under the control of the signals received. from block 3. For this purpose, each channel of block 1 receives clock pulses from block 10, a signal of operation -c of block 17 and a signal of prohibition from block 14. Presetting the OK 15. in a certain state is performed by applying a series of clock pulses from block 10. Pulses are fed through node 19 and key 18 to the selected input OK 15. In this case, the trigger 20 is signaled by the Work issued signal; block 17 must be set to one state. When a signal is received The prohibition from the output of block 14 (Fig. 6), the trigger 20 (Fig. 2) is reset to the zero state, thereby terminating the series of pulses to the OK input 15. The OK 15 is then monitored by a sequence of test kits supplied from the node 23 of block 3 (FIG. 4) to the input of the node 19 (FIG. 2). Prohibiting the recording of non-informative information in node 24 (Fig. 4) by inserting blocks 14 and 17 significantly reduces the amount of RAM in block 3. The type of repeating sequence of control signals assigned by block 1 to the control object 15 depends on the specific implementation Blocks 1, 14 and 17. This implementation provides transmission of the pulse packet to the OK inputs. The node 29 generates at the output of block 14 a signal of logical 1, if at a given output is OK 15, determined by the channel number recorded in register 31, the occurrence of a signal is recorded, the type of which coincides with the type recorded in register 32 of the type of expected response. Block 14, depending on the type of expected response recorded in register 32, registers the following signals: Register code Signal type 0001 Positive difference. 0010 Negative Differential 0100 Positive 1000 Negative Impulse The code of the type of expected response is recorded previously. COMP. 16. Node 13 contains- (Fig. 5) a register 25 for storing the type of input effects and a register 26 for controlling the input / output switch, whose output signals directly controlled by block 1. The trigger 28 is intended to control the type of exchange. The trigger 28 is controlled from block 4 via a decoder 27 in accordance with the computer program 16. When the trigger is installed 28 into 1 block 2 (FIG. 3), it transmits pulse information to write to block 3 registered in register 21 of the read answer. When the trigger 28 is installed in O, block 2 performs the reception of potential information from the OK 15. The information switch, implemented on the AND-OR 22 element (Fig. 3), switches information either directly from the OK 15 or from the outputs register 21. The operation of block 17 (Fig. 7) is as follows. Before the program, prior to the start of monitoring, the computer 16 and block 4 write into the register 47 the code of the final address of the nodes 23 and 24 and set the trigger 50 to 1 (Operation mode). At the same time, at the output of the form element 45, a Work signal is reset, which resets the counter 48, which stores the addresses, to the initial state. The counter 48 1 3 is blocked by the Inhibit signal sent from block 14 to the input of element AND 43. Thus, at the beginning of the monitoring cycle, counter 48, trigger 50 and amplifier transmitter 54 control the reading from node 23 of the first test set, which is passed through block 1 to inputs OK 15. The type of information (pulses or potentials) at the inputs of the OK 15 depends on the state of register 25 (Fig. 5). Node 19 (Fig. 2) transmits the test information read from node 23 (Fig. 4) to the key 18 in the form of potentials, if O is written in this discharge register 25, and in the form of a pulse, if in this discharge de register 25 it is written 1. Pulse temporal parameters depend on the state of the generator 10. Allowing the transmission of a packet of pulses to the inputs of the OK 15 triggers trigger 20 (FIG. 2) on the Work signal (block 17). The sequence of pulses to the inputs of the OK 15 is transmitted until block 14 receives an Inhibit signal at the output. The Inhibit signal resets the trigger 20 to O, stops the supply of a packet of pulses and. resolves the AND 43 element (Fig. 7) to transmit pulses to the input of the counter 48 and the signal Record via the amplifier-transmitter 52. The amplifier-transmitter 53 transfers the address code to the nodes 23 and 24 simultaneously. For the synchronous operation of the blocks 13, the input 43 : KTT pulses from the driver 10. The control OK 15 test sets, counted from node 3, occurs until the circuit 49 comparing the counter codes 48 and register 47 yields a match signal. In this case, the trigger 50 is reset to O and generates a signal The end of the control coming into the computer 16. Thus, unit 1, under the control of blocks 14, 17 and 3, can send to the input groups a repeating sequence of control signals, in particular, pulses of positive or negative field polarity, and the addresses of the group of inputs are determined by the register register 25, and the polarity of the pulses depends on the set test set at the output of the node 23. The OK 15 response signal falls into block 14 as follows. The output OK 15 (regardless of the input or output OK) 112 is connected to the corresponding bit of block 1 and input 1M of the register 21 and the element AND-OR 22. The procedure for recording the reaction OK 15 to register 21 is indicated earlier. The information recorded in register 21 is gated with pulses with predetermined temporal characteristics received from the generator 11. Therefore, the information on the output of the OK 15 in the steady state (potential information) may differ from the information recorded in the corresponding register 21. The AND-OR element 22 allows, depending on the signal at the 310 output of node 13, to write to the register 24 of unit 3 and analyze the response of the OK 15 in the steady state directly from the output of the OK 15 or from the output of the register 21.. Thus, the proposed device in comparison with the known provides control of objects, the response to the outputs of which occur, starting with some predetermined point in time. In addition, it reduces the amount of RAM in the information collection unit.

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Claims (1)

DEVICE FOR EXCHANGE OF CONTROL COMPUTER WITH OBJECTS OF CONTROL by ed. No. 783780, because of the fact that, in order to expand the class of monitored objects, a control cycle control unit and a response decryption unit are introduced into the device, the first and second inputs of the control cycle control unit and decryption unit the responses are connected respectively to the output of the control information reception unit and the control input of the device, and the third inputs, respectively, to the second output of the control information reception unit and the output of the driver of time intervals of the control signals, the output of the soy response decryption unit inen with the fourth input of the control signal block and the control loop control unit, the first output connected to the fifth input of the control signal output unit, and the second and third outputs, respectively, to the resolution input of the information collection unit and the output of the device cycle end signal, and the control cycle control unit contains four And elements, a group of amplifiers-transmitters, a counter, a register, a trigger, a comparison circuit and a group of AND-OR elements, with the first and second inputs of the first And element and the information input the register are the third, fourth and second inputs of the control unit for the control cycle, the group of outputs of the register is connected to the first group of inputs of the comparison circuit, the output of which is the key to the reset input of the trigger, and the second group of inputs to the group of outputs of the counter and the first * inputs of the corresponding elements -OR groups, the second inputs of which are connected to the direct output of the trigger and the first inputs of the second and third elements AND, and the third inputs - to the inverse output of the trigger and the first input of the fourth AND element, the outputs of the third and the fourth element And are coot- g respectively the first and third outputs of the loop control unit, the second input of the second element And is connected to the output of the first element And and the clock input of the counter, the reset input of which is connected to the output of the third element And, the fourth inputs of the elements AND-OR group , the synchronizing register input, the trigger trigger input and the second ₄ inputs of the third and fourth AND elements form the first input of the loop control unit, the output of the second AND element, the direct trigger output and the outputs of the AND-OR elements of the group to the inputs of the respective transmitter amplifiers, the outputs of which form the second output of the loop control unit.