SU1188755A1 - Device for syntactic analysing of programs - Google Patents

Abstract

A SOFTWARE FOR SYNTACTIC PROGRAM ANALYSIS containing a code entry node whose information input is the first information input of the device, first and second reading nodes, whose outputs are connected respectively to the inputs of the output block whose output is the output of the device, four comparison blocks, first information inputs which are connected to the second information input of the device, and the outputs are connected respectively to the information inputs of the first, second, third and fourth memory nodes; Thus, in order to extend the functionality by converting an infix record into a postfix one, a register block, a buffer register, a microprogram control block and a multiplexer are inputted into it, the output of which is connected to the second information inputs of the first to fourth comparison blocks, the first and the second information inputs of the multiplexer are connected respectively with the outputs of the buffer register bits and the information output of the register block; the information input of the buffer register is It is integrated with the output of the code entry node whose read input is connected to the first output of the firmware control unit, the second, third and fourth outputs of which are connected respectively to the setup input of the buffer register, to the enable input of the first readout node and to the enable input of the second readout node, fifth output the microprogram control unit is connected to the installation inputs of the memory nodes (L ti, the outputs of which are connected respectively to the first, second, third and fourth inputs of the microprogram control, the fifth input of which is the device start input, the sixth output of the firmware control block is connected to the gates of the comparison blocks, the seventh and eighth outputs are connected respectively to the synchronizing input of the register block and the enable input of the multiplexer, the information inputs of the register block and the first The readout control nodes are connected to the outputs of the buffer register bits, and the output of the block of registers is connected to the information input of the second readout node.

Description

The invention relates to computing and can be used for preprocessing discrete information, namely, to convert an infix notation of an alegbraic formula into a postfix one, which is widely used in creating specialized computational tools for modeling dynamic objects described by polynomial equations, as well as in determining Sequences for computing complex algebraic expressions in operating systems.

The purpose of the invention is to expand the functionality by converting an infix record to a postfix one.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the firmware control unit; in fig. 3 - time diagram of the device.

The diagrams denote microprogram control unit 1., Code entry node 2, buffer register 3, read nodes 4, 5, output block 6, register block 7, multiplexer 8, comparison blocks 9, 10, 11 and 12, nodes 13, 14, 15 and 16 of memory, fixed memory node 17, address register 18, address generation node 19, microinstruction register 20, trigger 21, counter 22, pulse generator 23.

Node 19 Serves to form the address of the next micro-command; its inputs receive information from the micro-register register 20, in which the current micro-command is stored, from the output of the 22 (characters) counter to analyze its contents to zero, from the outputs of nodes 13, 14, 15 and 16 ti. The trigger 21 serves to set the control potentials at the output of block 1, the control pulses are fed to the trigger inputs from the register of 20 microcommands. The counter 22 (characters) serves to organize the operation of the device, before starting work in the counter the number of characters of the original recording is set. The unit subtraction signal is fed to the counter input from the microcommand register 20, and if the number stored in the number counter is zero, the device ends the operation.

Code entry node 2 is a memory in which the character codes of the original record are written. The read signals, adding one to the address counter, zeroing the address counter come from block 1.

Buffer register 3 is used for intermediate storage of information; the character code is recorded in the register when reading this code from code entry node 2. The register is cleared by a signal from block 1.

The readout nodes 4 and 5 serve to transfer information from the buffer register 3 and register block 7 to the output of the device through block 6, respectively. The control pulses from block 1 pass information to the read nodes 4 and 5.

Block 6 is used to combine the same-named code bits from the outputs of nodes 4 and 5 and output them to

0 device output.

The register unit 7 serves for intermediate storage of information and consists of shift registers, the number of which is equal to the number of binary bits in the code. The information arriving at the input of a block of registers is written into the zero bits of the registers according to the sync pulse coming from block 1. Simultaneously with the recording, the information shifts to the right (from the lower bits of the registers to the older ones).

0 The shift to the left is effected by the signal from block 1, and the information recorded in the zero bits of the registers is deleted.

Each of blocks 9-12 consists of an interconnected memory node and circuit

 compare. The memory node is connected to one of the inputs of the comparison circuit, to the other input of which the output of multiplexer 8 is connected. The start signal from block 1 compares the code from the output of multiplexer 8 and the codes specified in the comparison blocks. When the codes match, the compare unit generates a code equality signal. This signal is input to the corresponding memory node and is stored there.

The purpose of the outputs and inputs of block 1 is as follows. The first output, which includes three binary bits from the micro-command register 20, is connected to the input of the code input node 2 and serves to emit read signals, add one to the address counter and zero the address counter. The second output is connected to the input of the buffer register 3 and serves to emit a reset signal from the micro-command register 20. The third and fourth outputs are connected respectively to the inputs of readout nodes 4 and 5 and serve to issue control pulses from the micro-command register 20. The fifth output is connected to the inputs of memory nodes 13-16 and serves to output a reset signal from the register micro-commands 20. The sixth output is connected to the inputs of blocks 9-12 and serves to output a start signal for the operation of the comparison blocks. The seventh output, which includes two binary bits, is connected to the input of block 7 of registers and serves to output a write clock and a left shift signal. The eighth output is connected to the input of multiplexer 8 and serves to control this.

multiplexer using a signal from the output of the trigger 21.

The first, second, third, fourth inputs of the unit are connected to the outputs of nodes 13, 14, 15, 16, respectively, and serve to analyze the information stored in these nodes. The fifth input serves to start the operation of the device, as well as to initialize the counter 22 (characters).

The device converts an infix notation into a postfix or so-called "Polish notation." The input to the device is a formula that describes the operands involved in the operations, the signs of the operations, and the order of the actions performed. The formula is written with the following limitations: the entire formula must be enclosed in brackets; the order of action is indicated by brackets; Operands are denoted by symbolic identifiers.

The postfix entry is characterized by the fact that it does not require brackets and clearly defines the order of actions. The rules for converting from infix to postfix notation are formulated as follows: the identifiers in the "Polish record follow in the order as in the infrared record: the signs of the actions in the" Polish record follow in the order in which they should be calculated (from left to right) ; action signs are located directly behind their operands.

The algorithm for converting infix to postfix notation is as follows.

The next character in the record is selected. It checks whether it is the last one in the record. If not, then go to step 2, otherwise the algorithm ends the work.

If the selected pulse is an opening bracket ("("), then go to step 3, if there is an identifier, then go to step 4, if with an action sign, then go to step 5, if the closing bracket ()), then Go to step 6.

The symbol is recorded in the working field. The transition to step 1.

The character is written to the postfix notation. If the previous character is a sign of the action, then go to step 7, otherwise go to step 1.

The symbol is recorded in the working field. The transition to step 1.

Signs of actions recorded in the working field are written into the postfix notation in the order, the reverse order being entered in the working field. Go to step 1.

The action sign is placed in a postfix notation. The number of elements in the working area decreases. Go to step 1.

The device works as follows. Sampling the next character in the record means reading the next character code from node 2 and entering it into the buffer register 3. Entering the character into the working field means writing the character code in block 7 of the registers. Entering a character in a “Polish entry” means sending a character code to the input of the device. Before starting work on the inputs of entering programs in blocks 9-

0 12 is entered in accordance with the codes of symbols, identifiers used, action signs, opening brackets, closing brackets.

When the power is turned on, the counter of the node 2 code entry address is reset, counter 22

 (characters) of block 1, buffer register 3, memory nodes 13-16.

The initial record is entered in node 2, after which the address of the last character is found in the counter of the code input node 2 entry

Q records, in the counter (characters) of block 1 - the number of characters of the original record. On the signal "Start received at the input of block 1, the device starts operation.

The signal from the output of block 1 resets the address counter of the node 2 input codes.

5 Analysis of the contents of counter 22 (characters) is performed.

If the contents of the counter are not equal to zero, the device continues to work, otherwise the node address counter is reset by signals from the outputs of block 1

° 2 code entry, buffer register 3, memory nodes 13-16. In this way, the device is prepared for operation.

The signal "Read from the output of block 1 to the buffer register 3 reads the code

5 of the next write symbol from node 2. With the output signal from block 1, the output of buffer register 3 is connected to the input of multiplex 8. Blocks 9-12 are launched. Occurs, an analysis of the contents of nodes 13-16.

0 If the selected character is an opening bracket, i.e. the memory node 15 is set to one, then the signal from the output of block 1 of the character code recorded in buffer register 3 is written to block 7 of the registers. The signals from the outputs of block 1 add one to the address counter of node 2, reset the buffer register 3, and reset the memory nodes. Thus, the device proceeds to the sample code of the next character.

0 If the selected character is an identifier, i. On signal

5, the output of block 1 resets the memory nodes. The output of register block 7 is connected to the input of multiplexer 8. A signal from the output of block 1 initiates the operation of blocks 9-12. The analysis of the contents of the memory nodes. If the character recorded last in block 7 of registers is a sign, i.e. set to one, the signal from the output of block 1 codes this symbol through the node 5 of the readout and block 6 is transmitted to the output of the device. The signal from the output of block 1 is shifted to the left in block 7 of registers. The device proceeds to sample the next character, as described above. If the character recorded last in block 7 of registers is not a sign of the action, then the device proceeds to the selection of the next character after it was described above.

If the selected character is a sign of action, i.e., memory node 14 is set to one, then, according to the signal from block 1, the code of this symbol written in buffer register 3 is written to block 7 of registers. The device proceeds to sample the next character, as described above.

If the selected character is a closing bracket, i.e., memory node 16 is set to one, the character code recorded last in block 7 of registers is analyzed, as described above. If this symbol is an action sign, its code is transmitted to the output of the device, as described above. At the exit signal

block 1 is shifted to the left in block 7 registers. There is an analysis of the next character written in block 7 of registers. Thus, the action character codes recorded in register block 7 are transmitted to the output of the device in order, the reverse of their writing in register block 7, until the character code issued by the output of block 7 is the code closing brace. In this case, the signal from the output of block I is shifted to the left in block 7 of registers and the device proceeds to fetch the next character, as described above.

Any time the device goes to the next character selection, the signal from the register of 20 micro-instructions is sent

0, the counter (characters) of block I is decremented by one. The device repeats the cycle of operation, starting with analyzing the contents of counter 22 for zero. If the contents of the counter (characters) are zero, the device ends up as described above.

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Claims (1)

DEVICE FOR SYNTACTIC ANALYSIS OF PROGRAMS, containing a code input node, the information input of which is the first information input of the device, the first and second readout nodes, the outputs of which are connected respectively to the inputs of the output block, the output of which is the output of the device, four comparison blocks, the first information inputs of which are connected with the second information input of the device, and the outputs are connected respectively to the information inputs of the first, second, third and fourth memory nodes, characterized in order to expand the functionality by providing the conversion of infix to postfix, a register block, a buffer register, a microprogram control unit and a multiplexer are introduced into it, the output of which is connected to the second information inputs from the first to fourth comparison blocks, the first and the second information inputs of the multiplexer are connected respectively to the outputs of the bits of the buffer register and the information output of the register block, the information input of the buffer register is connected to the output m of the code input node, the read input of which is connected to the first output of the microprogram control unit, the second, third and fourth outputs of which are connected respectively to the installation input of the buffer register, to the enable input of the first read unit and to the enable input of the second read unit, the fifth output of the firmware control unit § connected to the installation inputs of the memory nodes, the outputs of which are connected respectively to the first, second, third and fourth inputs of the microprogram control unit, the fifth input One of which is the start-up input of the device, the sixth output of the microprogram control unit is connected to the gates of the comparison blocks, the seventh and eighth outputs are connected respectively to the clock input of the register block and to the enable input of the multiplexer, the information inputs of the register block and the first readout node are connected to the outputs of the buffer register bits , the output of the register block is connected to the information input of the second read node. SU „„ 1188755> f