SU1185352A1 - Multidimensional statistical analyser - Google Patents

Description

The invention relates to computing and measurement technology and can be used in experimental studies related to multidimensional statistical analysis of random processes.

The purpose of the invention is to simplify the analyzer and increase its speed.

1 shows a diagram of the proposed multidimensional statistical analyzer ·, FIG. 2 is a block diagram explaining the principle of operation of the analyzer *, FIG. 3 is an example of a possible implementation of a key to address conversion unit 15; figure 4 is an example of the organization of the cell of the memory block; figure 5 is an example of the organization of the cell block of the associative memory; figure 6 is an example of a possible implementation of block 20 of the associative memory.

The analyzer (Fig. 1) contains an input register 1, a key-to-address conversion unit 2, an address register 3, a comparison circuit 4, an OR element 25 5, an associative memory block 6, an AND 7 element, a HE element 8, a memory block 9, a register 10 , register 11, switch 12 and block 13 output. The information inputs of the input 30 register 1 are the corresponding inputs of the analyzer, and the output is connected to the first input of the comparison circuit 4, the first information input of the memory block 9 and the input of the key preprogramming unit 2 to the address, the output of which is connected to the input of the address register 3, the output of which connected to the address input of memory block 9, the second information input and output 40

which is connected respectively to the first information output and the input of the first register 10, the output of which is connected to the first input of the switch 12, the output of which is connected to the input of the result output unit 13, the control input of the first register 10 is combined with the control input of the memory unit 9 and connected to the output of the HE element 8, whose input 50 is combined with the control inputs of the block 6 of the associative memory, the second register 11 and is connected to the output of the AND 7 element, the first input of which is connected to the output of the 55 or 5 element, and the second input of the n yield comparison circuit 4, the second input of which is combined with the input

element OR 5 and is connected to the first information output of memory block 9, the second input of switch 12 is connected to the first output of the second register 11, the information input and the second output of which are connected respectively to the output and the first information input of block 6 of associative memory, the second information input of which is connected to output register input 1.

The key-to-address conversion unit 2 can be implemented as a multi-input adder (FIG. 3). The work is as follows. The key, which is a digital binary code, enters the input register 1. The outputs of the input register 1 are divided into groups of "n" bits, where "n" is determined by the size of the memory area equal to 2 ^P , in which the placement of records. The key-to-address conversion unit 2 performs the operation of adding the corresponding bits of the various output groups of the input register 1 and the result is stored in the address register 3, the bitness of which is "n". If the total number of digits of input register 1 is not a multiple of "n", then the last group with the number of digits less than "n" is conditionally padded to "n" with zeros and participates in the addition operation along with the other groups of digits.

The associative memory unit 6 may contain a storage array of cells 14, an address selector and a decoder 15, an encoder 16, a mask register 17 and a search argument register 18, the input of which is one information input of the associative memory block 6, and a trigger connected to the mask register 17, output which is connected to the first information input of the storage array of cells 14, the second information input and output of which are respectively the information input and output of the block 6 of the associative memory, and the address input is connected to the output of the village address and decoder 15, the input of which is combined with the control input of the mask register 17 and connected to the output of the encoder 16, the input of which is connected to the address output of the memory array of cells 17, whose control input is

four

3

control input unit 6 associative memory.

Multidimensional statistical analyzer works as follows.

The numeric code received from external sources of implementations at the analyzer input is entered into the input register 1, the width of which depends on the dimension of the analyzed process. This code goes further to the input of block 6 of the associative memory and to block 2 of the conversion of the key into the address. The key-to-address block 2 by non-linear key conversion generates the cell address of the memory block 9 in which the key should be stored.

The principle of operation of a multidimensional statistical analyzer is based on the placement of incoming keys on the analyzer in some pseudo-random manner. A key is a numeric code that represents one implementation of a random process. The algorithm for generating an address for placing any key is implemented by a special combinational circuit that performs nonlinear conversion of a key to an address, and the range of change of keys can be several times larger than the range of changes of addresses.

The principle of operation is explained by the blockheme in FIG. Before the start of the experiment, the memory of the analyzer is reset to zero. A key that converts a key into an address is used to generate the address of a cell in a memory block from the key that arrives at the analyzer's input. It then analyzes the contents of the cell with this address. If it is free, the key is written into it, and in the digits of the cell allotted for the histogram, one unit is remembered. The key processing ends there. If the addressable cell is occupied by a key that coincides with the newly arrived one, the histogram of this key is completed and the processing is completed. If the new key and the key in the addressable cell differ from each other, the new key is placed in the associative memory, the size of which is 3-7% of the main memory. Each cell of the associative memory can store a key and a histogram .. Keys in the associative memory

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written sequentially as they arrive. When accessing the associative memory, it first turns out that the key that has already been received at the input 5 is written there. If yes, the histogram is completed; if not, the key is written to the first free cell. At the end of the experiment or by filling in the memory, 10 results are output to external media.

After the address is formed, it is entered into the 3 address register and 15 is addressed to memory block 9. The operation of memory block 9 is determined by the state of the control input. If the control input is “0”, the memory block 9 is determined by the status of the equals input up20. If the control input is “1”, the recording of information is permitted. An example of a possible organization of a cell of memory block 9 is shown in FIG. 5. The cell is divided into two 25 parts, the first of which is for storing the key, and the second for constructing the histogram. Since | At the initial moment of time at the control input of memory 9 at _{30 there} is "0", the contents of the second part of the addressable cell are extracted to the first register 10, and the first part goes to the second input of the comparison circuit 4 and the input of the OR element 5. Comparison circuit 4 compares the contents of the addressable cell with the key from input register 1 arriving at its first input. The element OR 5 allows you to determine whether the addressable cell is occupied by a key or not. This is achieved by the fact that the number of inputs of the element OR 5 (assuming the use of a multi-input element OR capable of performing the logical addition operation of several binary digits) is equal to the number of digits of one storage cell of the memory block 9. If the binary number coming from the cell to the input of the element OR 5, contains at least one non-zero digit, i.e. some information is stored in the cell, a single signal is generated at the output of the OR 5 element.

Thus, the comparison circuit 4

and the element OR 5 performs an analysis.

the contents of the addressable cell. Depending on the results of the analysis

five

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there are three options for further

work.

1. The current key from the input register 1 is addressed to the free 5

cell. In this case, at the output of the element OR 5, an "O" is formed, which is fed to the first input of the element AND 7. At the output of the element OR 5

The “O” will generate a single signal at the 10 output of the element HE 8, which increases by one the contents of the first register 10, thereby constructing a histogram, and allows the key entry from the input register 1 15

and histograms from the first register 10 to the addressable cell, which was previously empty. Processing of this key is complete.

2. The key from the input register 1 20

addressed to a cell occupied exactly by the same key. At the output of the element OR 5, a single signal is generated, since the key cannot be

equals zero. At the output of the comparison circuit 4, the signal "0" is generated when the keys coincide, which is fed to the second input of the element 7. And then, as in the first case, a single signal at the output of the element HE 8 increases by one the contents of the first register 10, completing the histogram, and allows the key and updated histogram to be written to the addressable cell. Key processing is completed. 35

3. The key from input register 1 is addressed to a cell occupied by a key other than it. The element OR 5, as in the second case, generates a single signal, since the keys do not match 40, the comparison circuit 4 also generates a single signal. Then

At the output of the element 7, a signal "1" is also generated, which permits the operation of block 6 of the associative memory 45 and the second register 11. At the same time, the signal "0" at the output of the element HE 8 will prohibit the entry of any new information into the memory block 9.

Thus, if the key received at the input of the analyzer cannot be placed in the main memory block 9, since the cell to which it was addressed turned out to be occupied by another key, it is placed in the block 6 of the associative memory. Each memory cell of the associative memory block 6 is the same as the cell

memory block 9, can be divided into two main parts, the first of which stores the key, and the second is intended for the construction of the histogram. There may still be a service level that stores a sign of employment.

The associative memory block 6, made in the form of an associative random access memory (FIG. 6), contains a storage array of cells 14, an address selector and a decoder 15, a search argument register 18, a mask register 17, an encoder 16. A storage array of cells 14 is used to store data , in our case, the key and histogram. Register 18 of the search argument holds the key by which the search is performed. The register 17 of the mask is designed to store the code masking. With a masked search, only a fraction of the digits of the search argument are compared with the corresponding digits of all words of memory. (Masking in associative memory is usually done by blocking some bits). If the required record was found in the result of the key search, the bus corresponding to the number of this cell is excited. The cell number of the encoder 16 and the address selector is fed to the decoder 15, decrypted and fed to the address inputs of the storage array 14, after which the contents of the desired cell, i.e. the histogram arrives on the output bus. Address selector 15 also allows reading or writing to any external address.

To search for a free cell, a special digit is used, which plays the role of the "Busy" checkbox. In the initial state, it is written "0". After the data is written to the cell, the flag is set to "1". To search for a free cell, it suffices to mask all the bits of the search argument, except the flag, and carry out the usual parallel comparison operation.

The search for the key in block 6 of the associative memory begins with the receipt of information in the input register 1 and is conducted simultaneously with the search in block 9 of memory. If the required key is written in block 6

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memory, then his histogram is rewritten in the second register 11, is incremented by a signal at the output of the element And 7 and is remembered again in block 6 of the associative memory.

If the required key in block 6 of the associative memory is not found, then it is overwritten from input register 1 to the first free cell of block 6, and the second register 11 records the unit from the output of AND 7 to the bits of the cell corresponding to the histogram .

When filling the memory, you can either stop the experiment, or continue the accumulation of statistical information about the keys already received.

At the end of the experiment, the accumulated statistical information is extracted from the memory blocks 9 and the associative memory 6 and, respectively, through the first 10 and second 11 registers and the switch 12 enters the result output unit 13. The operation of the switch 12 can be controlled directly from the console.

As a block 13 output can be used any standard peripheral

15 equipment, such as an alphanumeric printer, display, typewriter, external storage device, etc.

Thus, the proposed multidimensional statistical analyzer allows for the rapid construction of histograms of distributions of multidimensional random processes.

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FIG. 3

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Claims (1)

A MULTI-DIMENSIONAL STATISTICAL ANALYZER containing a result output unit, an input register whose information inputs are the input of the analyzer, and the output is connected to the first input of the comparison circuit, the first information input of the memory block and the input of the key-to-address conversion unit whose output is connected to the address input through the address register the memory block, the second information input and the first information output of which are connected respectively to the first information output and information input, the first one, register, exc aspirants in order to improve speed, it contains an associative memory block, a second register, a switch, a NOT element, an AND element and an OR element whose input is combined with the second input of the comparison circuit and connected to the second information output of the memory block whose control input combined with the control input of the first register and connected to the output of the element NOT, the input of which is combined with the control inputs of the block associative memory and the second register and connected to the output of the element And, the first and second § inputs of which are connected to responsibly to the outputs of the comparison circuit and the OR element, the first information input of the associative memory block is connected to the output of the input register, the second information input and the output of the associative memory block are connected respectively to the first information output and the information input of the second register, the outputs of the first and second registers are connected respectively to the first and the second information inputs of the switch, the output of which is connected to the input: of the output unit. 1Ϊ 85352 > one 1185352 2