SU1179351A1 - Interface for linking computer with peripheral units - Google Patents

Abstract

A DEVICE FOR PAIRING ELECTRON-COMPUTING MACHINE WITH PERIPHERAL DEVICES, containing a memory block and a first address decryption unit, the input group of the first address decryption unit connected to the address bus and the service signal bus of the electronic computer, and a single set of cores, and a detached set to one. hardware costs and speeds through the independent use of a RAM block by an electronic computing machine and peripheral devices; a second an address decryption block and a RAM block are two-channel, the group of information inputs-outputs of the first channel of the RAM block is connected to the information bus of the electronic computer, the group of information inputs-outputs of the second channel of the RAM block is connected to the peripheral information bus devices, the group of inputs of the second address decoder is connected to the address bus and the service signal bus of the peripheral device, the output group of the first address decoder address united with the address input kn and the mode control input of the first channel of the RAM, the group of outputs from the second address decoder is connected to the address input and the mode control input of the second channel of the RAM. CO WITH SD

Description

The invention relates to computing and can be applied in computing and control systems for interfacing computers with peripheral devices or other computers connected to peripheral devices.

The purpose of the invention is to reduce hardware costs and increase speed by independently using the RAM block by the electronic computer and peripheral devices.

The device allows asynchronous (independent) data exchange between the external device, the memory unit and the central processor. Moreover, the exchange between an external device (for example, a specialized computing device, a microprocessor or information sensors) and a block of RAM controls the external device, and the exchange between the processor and the block of RAM is controlled by the processor. Data read or write control commands are contained in an address word format, the address part of which defines the address of a cell (register).

FIG. 1 shows a block diagram of the device; in fig. 2 - the functional diagram of the address decoding block; in fig. 3 is a temporary diagram of the operation of the address decryption unit.

The proposed device comprises a processor 1, a system trunk 2, an external highway 3, a RAM block 4, the first 5 and second 6 address decryption blocks, and a peripheral device 7.

Block 5 (6) address decryption contains (Fig. 2) register 8, one-shot 9, the element AND NOT 10 and the elements NOT 1 1 and 12. FIG. 2 also indicates the group of address inputs 13 and address outputs 14 of register 8, synchronization input 15 of register 8, gate input 16 of address 5 block 6 (6) addressi channel output 17 (1 or 2) of address decryption block 5 (6), input 18 and output 19 records of block 5 (6) of address decryption, input 20 and output 21 of read block 5 (6) of address decryption.

The device works as follows.

During the write cycle from processor 1, the information on system bus 2 arrives at the information inputs / outputs of the first channel of the operational write block 4, where it is written into memory cells whose addresses are determined by block 5. During a read cycle from block 4, the system data line 2 enters processor 1. The cell addresses are also determined by block 5.

Similarly, the data of the external trunk 3 from the peripheral device 7 (for example, a microprocessor in a multiprocessor system, information sensors

or actuators) and read from the cells of the block 4 peripheral device. Cell addresses are determined by block 6.

Block 5 receives via system trunk 2, and block 6 receives through external highway 4 a sign that the incoming information is a control word. This notification may be, for example, a clock sequence if the control words and data are transmitted in the time division mode, or the control word is transmitted over a special line or group of lines.

According to the diagram in FIG. 2, at the beginning of the cycle, a control word is always written, then in the same cycle one of two actions can be performed: writing or reading a data word. Blocks 5 and 6 are completely identical with respect to the external highway 3.

The main clock sequence arriving at input 20 has the form shown in diagram 16 (FIG. 3). Two cycles are shown: write and read, consisting of two clock periods. In the first period, a control word is received from system trunk 2 containing the cell address and mode information: write or read. The cell 4 address of the inputs 13 is written to the address register 8 by pulse 15 (FIG. 3) generated by the one-shot 9 on the leading edge of the clock sequence 16. In the second period, the output of the AND-10 element is using the clock sequence 16 and the inverse signal 15 the second output of the one-shot 9; a first-channel resolution signal 17 is generated. The address of the cell at the outputs 14 (diagram 14) arrives at the address inputs of block 4 of the first channel and selects the addressable cell. In the second period of the recording cycle, system data 2 goes to the information inputs / outputs of the first channel of block 4 and a data word is input to input 18 of the NOT 11 element - a recording signal, which from output 19 (diagram 19) goes to the recording input of the first channel and data word is written to the selected cell of block 4. In the second period of the read cycle, the read signal arrives at input 20 of the element HE 12 from system trunk 2, which from output 21 (diagram 21) goes to the input of read permission of the first channel and from information inputs / outputs Channel 4 word block of data from a selected cell is output to the line 2.

As a result, information can be read by processor 1 and peripheral device 7 from any cell of block 4 at any time, including simultaneously on both channels.

Recording information from processor 1 and peripheral device 7 can also

be produced in any cell of unit 4, except in the case of simultaneous recording in the same cell. This can lead to the recording of false information. To eliminate this case, the memory array of the recording mode 4 can be divided into two parts so that the recording of information from the processor 1 can be made into one part, and the recording from the external device into another, or divide the recording into one and the other in time. same cell.

Thus, the device has the ability to accumulate and quickly retrieve data, provides the possibility of autonomous and asynchronous operation of it with several peripheral devices. For example, integrated circuits of the type K1802IR1 can be used as a two-address memory.

The application of the proposed device doubles the speed and reduces hardware costs by 60% as there is no need for communication units, switching, control, address modification, output buffer memory.

A 2-fold increase in speed is achieved as a result of separate (independent) control of data exchange between the processor and the memory block and between the block of operational memory, memory and an external device.

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Claims (1)

A device for interfacing an electronic computer with a peripheral device, comprising a random access memory unit and a first address decryption unit, the input group of the first address decoding unit being connected to the address bus and the service bus of the electronic computer, characterized in that, in order to reduce hardware costs and increase speed through independent use of the RAM block by an electronic computer and peripheral devices, the second block is introduced into it address encryption, and the RAM block is two-channel, while the group of information inputs / outputs of the first channel of the RAM block is connected to the information bus of the electronic computer, the group of information inputs and outputs of the second channel of the RAM block is connected to the information bus of peripheral devices, the group of inputs the second address decoder is connected to the address bus and the service signal bus of the peripheral device, the group of outputs of the first address decoder is connected to the address nym input and the input of the first control channel mode memory block, a group of outputs of the second address decoder connected to the address input and the input of the second control channel mode memory block. 179351