SU1150740A1 - Single pulse generator - Google Patents

Abstract

A SINGLE PULSE FORMER containing two triggers, the synchronizing input of the first of which is connected to the clock bus, to the second input of the AND-OR element and to the input of the first inverter, the output of which is connected to the third input of the AND-OR element and the synchronizing input of the second trigger, first installation input in the “About which is connected to the installation bus in“ O and to the first input of the installation in “About the first trigger, the second input of the installation in“ About the second trigger is connected to the inverse output of the first trigger, and the direct and inverse outputs to the second trigger, respectively, with the fourth input of the AND-OR element and the second input of the installation into the About First Trigger, whose direct output is connected to the first input of the AND-OR element, the output of which is the output of the single pulse former, the AND-NO element, the control bus, characterized in that, in order to extend the functionality by providing the possibility of generating pulses with a control signal duration longer than the clock period and increasing reliability of operation, the trigger and the second inverter, whose input is connected to the control bus and to the information inputs of the first and second triggers, and the output — With the first input of the NAND element, the second and third inputs of which are connected to s, respectively, with the inverse outputs of the first and second triggers, and the output is from the installation location in “About the third trigger, the inverse dynamic input of which is connected to the output of the AND-OR element, and the output of the third trigger is connected to the third inputs of the installation to“ About the first and second triggers. ate about 4

Description

The invention relates to a pulse technique and can be used in devices for various purposes, in particular in discrete automation and electrical measuring equipment. A single pulse shaper is known, which contains two clocked Drigggers. This single pulse shaper is simple in its structural construction and requires minimal equipment for its implementation 1. However, in a known single pulse shaper, the output pulse starts from the leading edge of the control pulse after a time equal in the worst case to the sync pulse period. The duration of the output pulse in a known driver is equal to the duration of the sync pulse, i.e. half the period of the following clock pulses. Thus, the formation of the output pulse requires a time equal to one and a half periods of the following clock pulses, which also determines the slow response of the known single pulse generator. The known driver will work only under the condition that the response time of the output D-flip-flop on input R is several times longer than the response time of the input D-flip-flop on input T and the edges of the clock pulses are perfectly straightforward, which is almost impossible. Such restrictions require the selection of elements in the implementation of the known shaper. In addition, over time, the parameters of the elements change, which may lead to the violation of the above ratios, the output D-trigger will not start and a single impulse will not be generated at the output of the known device. This disadvantage significantly reduces the reliability of this shaper. The closest to the proposed technical essence and the achieved result is a single pulse shaper containing two 3-K flip-flops, five AND-NOT elements and an inverter, the syringe of which is connected to the second input of the AND-OR element and to the sync input of the first trigger, and the inverter output is connected to the third input of the AND-OR element and the synchronizing input of the second trigger, the first input of the installation in “About which is connected to the installation bus in“ O and to the first input of the installation in “About the first trigger, the inverse output of which is It is connected to the second input of the installation in “About the second trigger, the outputs of which are respectively connected to the fourth input of the AND-OR 1 0 element and to the second input of the installation to“ About the first trigger, the direct output of which is connected to the first input of the AND-OR 2. K The disadvantages of such a device can be attributed to the fact that it forms a single single pulse only if the duration of the control pulse does not exceed the sync pulse period. If the duration of the control pulse is longer than the period of the sync pulses, then the output of the device will form several pulses instead of one. The possibility of forming a false output pulse with a known device reduces the reliability of its operation and leads to failure and malfunction of the equipment in which it is used. The purpose of the invention is to enhance the functionality by allowing the formation of pulses with a control signal duration longer than the clock period and increasing reliability of operation. The goal is achieved in that in a single pulse shaper containing two flip-flops, the synchronization input of the first of which is connected to the clock bus, to the second input of the AND-OR element and to the input of the first inverter, the output of which is connected to the third input of the AND-OR element and synchronizing the second trigger input, the first input of the installation in “About which is connected to the installation bus in“ O and the first input of the installation in “About the first trigger, the second input of the installation in“ About the second trigger is connected to the inverse output of the first three gera, and the direct and inverse outputs of the second trigger, respectively, with the fourth input of the AND-OR element and with the second input of the installation in the “About the first trigger”, the direct output of which is connected to the first input of the AND-OR element, the output of which is single impulse, the NAND element, the control bus, the third trigger and the second inverter are entered, the input of which is connected to the control interface and the information inputs of the first and second triggers, and the output to the first input of the NAND element, the second and third inputs of which connected soo respectively with the inverted outputs of the first and second flip-flops, and the output - to the input of the installation in "On the third flip-flop, the inverse dynamic input of which is connected to the output of AND-OR and the output of the third flip-flop is connected to the third setting inputs in" On the first and second flip-flops. FIG. 1 shows a functional diagram of a single pulse shaper; in fig. 2 - time diagram of his work.

Fo |) MT | 10 11 Ii.ib;.;. Ii () r () impulse contains. TjViri (.i) i ;; 2,. ;; cMiHT AND-OR 3, inverter 4, -Aicvicni AND 5, third trigger 6, second 11) () 7, control bus 8, bus 9 sync pulses, bus 10 installation in the "O.

A single pulse shaper contains two triggers 1 and 2, synchronizing, the first input of which is connected to the bus 9 sync pulses, to the second input of the AND-OR element 3 and to the input of the first inverter 4, the output of which is connected to the third input of the AND-OR element 3 and the synchronization input of the second trigger 2, the installation input in “About which is connected to the installation bus 10 in“ O and the first input of installation in “About the first trigger 1, the second input of installation in“ About the second trigger 2 is connected to the inverse output of the first trigger 1, and direct and inverse outputs in the second trigger 2, respectively, with the fourth input of the element AND-OR 3 and with the second input of the installation on the first trigger 1, the direct output of which is connected to the first input of the element AND-OR 3, the output of which is the output of a single pulse former, the element AND - NO 5, the third trigger 6 and the second inverter 7, the input of which is connected to the control length 8, and with the information inputs of the first and second triggers 1 and 2, and the output - with the first input of the AND-NE element 5, the second and third inputs of which connected respectively to the inverse outputs of the first and second trigger 1 and 2, and the output with the installation input in “About the third trigger 6, the inverse dynamic input of which is connected to the output of the AND-OR element 3, and the output of the third trigger 6 is connected with the third inputs of the installation in“ About the first and second triggers 1 and 2

Shaper single pulse works as follows.

In the initial state, the triggers 1 and 2 are zeroed by applying a negative polarity pulse to the setting bar 10 in the "O" associated with the first zero inputs of the triggers 1 and 2.

With the arrival of control pulses UI1 and UI2 (Fig. 2c), the leading fronts of which are inside the synchro pulses SI1 and CI2, respectively (Fig. 2a), the first trigger 1 (Fig. 2e) is triggered. The zero level of the inverse output of the first flip-flop 1 acts on the second zeroing input of the second flip-flop 2, keeping it in the zero state.

The unit level of the direct output of the first trigger 1 acts on the second control unit iiiiiiiuiii nhol .it-MiM 1ГП, П. pppepeiiuiji Ti-M c; iM), -4 41. iiiu. (, с () and Cl-11 li (.),; no.) rnn ())

15X0NU ate the words TiMb post :; C 111Xp (). 1bcov pa output 11 f () pm11r () i1tel (fig. 2 .№). The third trigger 6 triggers on the rear front of the output pulse 1 {fig. 2l), the bullet level of the inverse output of which, acting on the third nulling inputs of the flip-flops 1 and 2, flushes the first flush-trigger 1 (Fig. 2 (3) and confirms the zero state of the second flip-flop 2 (Fig. 2e).

After zeroing the first trigger 1 (Fig. 2e), the second and third inputs of the AND-NE element 5 are in the same state.

5 If at this moment the control pulse is absent (in the case of U1, the duration of which is less than the period of the following clock pulses), then the first input of the AND-NE element 5 associated with the output of the second inverter 7 (Fig. 2 g) is in the unit state . The AND-NE 5 element is triggered (FIG. 2 s) and the third trigger 6 is zeroed. The shaper is ready for processing the next control pulse.

In the case of a control pulse UI2,

5, the duration of which is longer than the period of the following clock pulses, the resetting of the third trigger 6 (Fig. 2h) occurs after the termination of this control pulse (Fig. 2c, d, i).

With the arrival of control pulses

 and UI4 (Fig. 2c), the leading edges of which are in the pause between the sync pulses of the PPE, SI4 and SI5 (Fig. 2a), trigger the second trigger 2 (Fig. 2e). The zero level of the inverse output of the second flip-flop 2 acts on the second gangway input of the first flip-flop 1, keeping it in the zero state. The unit level of the direct output of the second flip-flop 2 acts on the first control input of the AND-OR 3 element, thereby allowing the passage of the sync pulses SI4 and PPE (Fig. 2 a) to the output 11 of the imager (Fig. 4ls).

Further operation of the single pulse shaper occurs as described.

Thus, the proposed single pulse shaper allows one to generate a single pulse regardless of the duration of the control pulse and to eliminate the formation of false output pulses with the duration of the control pulse.

0 pulses are longer than the period of the sync pulses, which greatly expands the functionality and increases the reliability of the device.

Fit ...

Claims (1)

A SINGLE PULSE SHAPER containing two triggers, the synchronizing input of the first of which is connected to the clock bus, with the second input of the AND-OR element and with the input of the first inverter, the output of which is connected to the third input of the AND-OR element and the synchronizing input of the second trigger, the first installation input at “0” which is connected to the installation bus at “0” and with the first installation input at “0” of the first trigger, the second installation input at “0” of the second trigger is connected to the inverse output of the first trigger, and the direct and inverse outputs of the second trigger - respectively, with the input of the installation set to “0” of the first trigger, the direct output of which is connected to the first input of the AND-OR element, the output of which is the output of a single pulse shaper, the AND-NOT element, the control bus, characterized in that, in order to expand functionality by providing the ability to generate pulses with a duration of the control signal greater than the period of the synchronization pulses and increase the reliability, it introduced a third trigger and a second inverter, the input of which is connected is not with the control bus and with the information inputs of the first and second triggers, and the output is with the first input of the NAND element, the second and third inputs of which are connected respectively to the inverse outputs of the first and second triggers, and the output is with the installation input at "0 »The third trigger, the inverse dynamic input of which is connected to the output of the AND-OR element, and the output of the third trigger is connected to the third inputs of the installation at“ 0 ”of the first and second