SU1013953A1 - Exponential function computing device - Google Patents

Abstract

A DEVICE FOR CALCULATING THE INDICATIVE FUNCTION, containing the first counter, the decoder added. no impulse, a group of elements And,. elements. AND, and the output of the first AND element is connected to the first input of the OR element, the second input of which is connected to the output of the second AND element, from which, in order to increase the accuracy of the function, the second the counter, the shift register, the pulse skip decoder, the first and second delay elements, the bits of the first counter are connected to the corresponding inputs of the add-on decoders, and the pulse skip / output of the pulse addition decoder is connected to the first inputs of the first element And second The first input of which is connected via the first delay element to the input of the device connected to the input of the first counter and the first input of the second element I, the second input of which through the second delay solvent is connected to the output of the pulse skip decoder, the overflow output of the first counter is connected to the input of the shift register, whose outputs are connected to the first inputs of the AND elements of the group, the second inputs of which are connected to the output of the OR element, the outputs of the AND elements of the co- group. Dinenov s. inputs of the second counter, the output of which is connected to the output of the device. . . OR with SP O9

Description

The invention relates to digital computing and can be used in digital and digital-analog computing and information-measuring devices and systems, as well as in automation devices for calculating or generating an exponential function.

A device for improving performance based on a binary-decimal counter, binary counter, coefficient input unit, pulse generator, two triggers, binary coefficient setting counter, control circuit, six keys and multiphase multivibrator is known. 13 The disadvantages of this device are complex operation mode and large calculation error.

The closest to the invention according to the technical solution is a digital device for calculating exponential functions comprising a decoder, a counter, groups of elements AND, elements AND and OR, a trigger, two adders and a comparison circuit 2

The disadvantages of this device are complex multi-cycle operation logic and relatively large calculation error.

The aim of the invention is to improve the accuracy of the function calculation.

The goal is achieved by the fact that the device for calculating does not have an exponential function containing the first counter, a decoder for adding a pulse, a group of elements AND, elements AND, OR, and the output of the first element AND is connected to the first input of the element OR, the second input of which is connected to the output the second element And, entered the second counter, shift register, pulse decoder, the first and second delay elements, the bits of the first counter are connected to the corresponding inputs of the add and skip decoders, The output of the pulse addition decoder is connected to the first input of the first element I, the second input of which through the first delay element is connected to the input of the device connected to the input of the first counter and the first input of the second element And, the second input of which through the second delay element is connected to the output of the pulse skip decoder, the overflow output of the first counter is connected to the input of the shift register, the outputs of which are connected to the first inputs of the elements AND of the group, the second inputs of which are connected to the output of the element OR, the outputs And lementov group are connected to the inputs; second counter.

the output of which is connected to the output of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 and 3 are graphs that explain the principle of its operation.

The device contains the device input 1, the first binary counter 2, the device output 3, the shift register 4, the group of elements 5, the binary counter b, the add decoder 7 and the pulse skip decoder 8, the delay elements 9 and 10, the elements 11 and 12, element OR 13.

15 The operation of the proposed device is based on the following algorithm.

Let some argument X of the exponential function Y 2 take values, i.e. for a binary-coded representation, it also contains bits, with K representing the integer and α the fractional part. We denote the integer part of the argument | Ta as SHD (О,), and the fractional

Part 5 - X (O X). By virtue of

properties of an exponential function holds

2 2 2 2 ti; If we consider that the multiplication by

0 is equivalent to a binary shift

codes on Cx bits in the direction of the older ones, in order to reproduce function 2, in principle, it is sufficient to calculate the values of its mantissa 2 only for the set of values of the fractional part-argument X that lie within the first octave (). (An octave is the range of argument values between its two

0 by successive integer values).

In the case when the argument X is represented at a certain scale by a number-pulse code, i.e. The arrival of each pulse is equivalent to an increment of the argument equal to the reproduction of the function. In a 2, a cyclic procedure can be used. For each of the 2 current values of the fractional part of the argument, the corresponding value of the mantissa 2 is calculated, and then, when forming the next increment of the integer part of the argument, the result is shifted by one bit.

5 to the higher order and the function starts playing in the next octave. In this case, the set of codes of mantissa values within each octave will be repeated, and their weight will be

0 as the accumulation of an integer part of the argument will increase by 2C times.

FIG. 2 shows the graph of a mantissa Y 2 and the graph b of the linear function Y 1 + X, which

5 is often used as its approximation. Approximation error of the Cs function. Y 2 has a linear dependence Y 1 n-X is equal to L 1 + X - 2X (2; Its graph is asymmetrical relative to the middle octave and is shown on an enlarged scale in Fig. 3. We find the coordinate X / maximum error value, for which the derivative of the expression (2 ) equal to zero 1 2 In 2 О, from where. X eoeLlU The maximum error value at X X is equal to s. (, obom ... (1 The algorithm of the proposed device is based on reproducing the approximate exponential function of piecewise linear in octaves) according to the error curve in the result in Calculating the mantissa corrections carried out by the SB rate of arrival of the pulses of the input code so that the absolute value of the error of calculating Leny does not exceed half the error of the discreteness of the function in each octave. The points at which correction must be made can be determined both by calculation and graphically As an example, Fig. 3 shows the choice of coordinates of correction points for the case / when the number of bits In the fractional part of the argument and the mantissa of the computed exponential function is eight. The coordinates on the abscissa axis are determined by the moments of the transition of the linear curve. linear approximations in terms of values equal to (j - 0.5) 2, where j is 1, 2, 3 ..., namely, equal values of 0.5, 1.5, 2.5, etc. discretization errors. Due to this choice of correction points, the absolute error of the calculations will have an alternating character and should not exceed modulo half the discreteness at any value of the argument. Correction can be made by skipping or adding pulses to the linear approximation of the mantissa on the upstream and downstream parts of the error curve, respectively, with the argument values corresponding to the selected correction points. The numbers of correction points for the considered case E 8 are given in the table.

0,00000010

2

one

five

2

9

3

12 16 20 23 27 31 35 0.00001100

four

five

b

7

eight

9

0 11 12, 00101000 ..40 44 49

3

. 0,10011100

“D0101001

00000101

10110010 00001001

0,10111010

11000000 00010000

11000110 00010100. 11010011 0.0010111

11010000 00011011

11010101 00011111

11011001 00100011

11011101

11100000 00101100

11100100 00110001

The proposed device works as follows.

In the initial position, all bits of counters 2 and 6, except for the (-1 +1) -th bit of counter 6, are set to the zero state. In the first digit of the shift register 4, the unit is recorded, so that the first element of group 5 is opened. Argument X in the pulse code comes to the input 1 of the device and then to the counter input of counter 2, the element 11, and also through the delay element 9 to the element 12. Until one of the decoders 7 or 8 works add and skip pulses, respectively, AND 11 is open, and AND 12 is closed, and the input sequence pulses through AND 11 and OR 13 elements to the second inputs of AND 5 group elements. .

Every time when in counter 2, which calculates the drrb part of the argument, the code value corresponding to the next correction point on the upstream part of the error curve is set, the decoder 8 of the impulse pass passes. After a time determined by the delay element-10, which must not be less than the duration of the input pulses, the element 11 closes and the next input pulse after the succession to the counter b does not pass, but only goes to counter 2. The code in the counter 2 is changing

Table continuation

and after the delay time of the element 10, the prohibition from the element 11 is removed.

In the second half of the octave, all previously deducted pulses at the appropriate points in time must be added. For this purpose, when the counter code value is set to the next correction point on the downstream part of the error curve, the decoder 7 adds a pulse and opens element 12. And the input sequence corresponding to this code delayed by delay element 9 adds an extra unit to the contents of counter b. The delay time of element 9 should also exceed the duration of the input pulses, in order to ensure the reliable resolution of the pulses with the aim of error-free operation of the counter b. The subsequent impulse of the input sequence establishes in-counter 2 a code in which the enabling signal from the output of the decoder 7 is removed and the element 12 closes.

Since the number of pulses added during correction on the downstream part of the error curve is always equal to the number of previously transmitted pulses in the upstream region, by the time of the next octave the number of pulses received in the counter 6 is equal to the total number of input pulses per octave, due to which the transition the next octave is carried out accurately, namely at the moment of arrival of the input pulse with a number equal to 2. In this case, the output of counter 2 generates an overflow signal, which enters the clock input of the shift register 4. By the time the shift signal arrives, the contents of the low-order bits of the counter are also overflowed, and since the (+1) -6m bit was previously recorded the unit will transfer to the (2 + 2j-fi bit). The falling edge of the overflow signal is counting 2 units in the register, the shift 4 will move to another.

shchinou bit

As the input argument pulses belonging to subsequent octaves arrive, the device operates in the same way, only in counter 6 will be filled: from bit i-ro to (1 + & 1)

where i is the octave number. Thus, in the proposed device c. real time i. at the rate of arrival of the input information, codes of values of exponential function 2 are formed in the counter b with an error not exceeding half the discrete error of each octave.

The total number of bits of counter 6 and register 4 must be at least () and (1) bits, respectively.

The number of correction points M depends on the fraction E of the fractional part of the argument and is equal to „I

M, (5) where is the definition of expression (4). For example, for a resolution of e 8, 12, 1b; M 44.704 and 11280, respectively. .

The technical and economic efficiency of the proposed device in comparison with the known exponential function using the mant.ssy exponential function as a result of a linear approximation (graph b in Fig. 2) is that the calculation accuracy of the proposed device is higher because the absolute methodical error of the calculations at any point in the range does not exceed half the discrete error, and iyenno. Easy to take-; It should be noted that the resulting gain in accuracy is equal to the number of correction points used in the proposed device and defined by the ratio (5). In particular, at B, 8, 12, 16, the gain in accuracy is 44.704 and 11280 times.

At the same time, the proposed device provides the calculation of the binary exponential function of the argument represented in the pulse number code, which allows its use in real-time systems, as well as as a generator of the exponential function in digital and digital-analog devices. .

Claims (1)

DEVICE FOR CALCULATING INDICATOR FUNCTIONS, containing the first counter, a pulse adding decoder, a group of elements. AND, elements. AND, OR, and the output of the first AND element is connected to the first input of the OR element, the second input of which is connected to the output of the second AND element, with the aim of increasing the accuracy of calculating the function, a second counter, a shift register, a pulse skip decoder, first and second delay elements, the outputs of the bits of the first counter are connected to the corresponding inputs of the add decoders, and a pulse skip; the output of the add pulse decoder is connected to the first input of the first element And, the second input of which through the first delay element is connected to the input of the device connected to the input of the first counter and the first input of the second element And, the second input of which is connected to the output of the pass decoder through the second element of the power * pulse, the overflow output of the first counter is connected to the input of the shift register, the outputs of which are connected to the first inputs of the AND elements of the group, the second inputs of which are connected to the output of the · OR element, electronic output And cops soe- group, c ^ dineny inputs of the second counter whose output is connected to the output n ^ device. ‘ 4hrt.l 1 1013953