SU1001486A1 - Binary pulse counter - Google Patents

Description

(5) Binary PULSE COUNTER

one

The invention relates to a pulse technique and can be used in the design of digital computing device counters.

A binary pulse counter is known that is implemented on ternary logic elements. However, the known binary pulse counter has a complex implementation, since each bit of the counter is executed on three ternary logic elements.

A binary pulse counter is known, which contains an input bus, a bus of the first phase of the clock supply, a bus of the second phase of the clock feed and n bits, each of which contains installation buses at zero and one, three four-input ternary logic elements, the first input of the first four-input ternary logical element in each bit except the first is connected to the output of the first four-input ternary logic element of the previous bit, the first input of the first four-input three-way logic element of the first bit is connected to the input bus; the output of the second four-input ternary logic element in each bit is connected to the second input of the first four-input three-way logic element, the fourth input of which in odd and even bits is connected respectively to the tires of the second and first phases of the clock power, in each bit de output of the second four-input ternary logical element. The element is connected to the first input of the third four-input ternary logic element, the output of which is connected to the first and second inputs of the second four-input ternary logic element, the fourth input of which is connected to the installation bus to zero, the first input of the first four-input ternary logic element is connected to the fourth input of the third four-input ternary logical element, the second input of which is connected to the installation bus in the unit. The discharge of the known binary pulse counter is performed on three elements, each of which performs ternary operations presented in the table. These operations form a functionally complete system of logical functions and can be implemented on the basis of ternary elements, for example, on ferrite logic elements | 2 However, the known binary counter. Pulses has a complex implementation, since each counter discharge is performed on three ternary logic elements. The purpose of the invention is to simplify the account. chi ka This goal is achieved by the fact that a binary pulse counter containing an input bus, a bus of the first phase of the clock supply, a bus of the second phase of the clock feed and n bits. each of which contains a bus set to zero and one, two four input ternary logic elements, the first input of the first four-input ternary logic element in each bit, except the first one connected to the output of the first four-input three-way logic element of the previous bit, first input of the first four-input ternary logic element of the first row is connected to the input bus, the output of the second four-input ternary logic element in each bit is connected to the second input of the first par The three-input ternary logic element, the fourth input of which in odd and even bits is connected respectively to the buses of the second and first phases of the clock supply, the first input of the second four-input three-way logic element in odd and even bits is connected respectively to the tires of the first and second phases of the clock feed , in each discharge, the third input of the first and the second input of the second four-input ternary logic elements are connected with the installation buses to zero and one, the output of the first four-cho ovogo ternary logic element coupled to the third and fourth inputs of the second NAND gate chetyrehvhodovogo threefold. FIG. 1 shows a three-bit binary pulse counter circuit; in fig. 2 shows a time diagram of the operation of a three-bit binary pulse counter. The device contains ternary logic elements 1-6, buses 7–9 of installation into a unit, respectively, of the first discharge on ternary logic elements 1 and 2, second discharge on ternary logic elements 3 and 4, and the third bit on the ternary logic elements 5 and 6, the bus 10-12 sets to zero, respectively, the first, second and third bits, input bus 13, bus I and 15, respectively, the second and first phase of the clock power. The outputs of the ternary logic elements 2, A and 6 are connected respectively with the second inputs of the ternary logic elements 1,3 and 5, the third inputs of which are connected respectively to the buses 10, 11 and 12 of the setting to zero, the buses 7, 8 and 9 of the installation to one are connected The second inputs of the elements 2, 4 and 6, the bus 14 of the second phase of the clock supply are connected to the fourth input of the elements 1 and 5 and the first input of the element k, the bus 15 of the first phase of the clock supply is connected to the first input of the elements 2 and 6 and the fourth input of the element 3, input bus connected to the first The second input of element 1, the output of element 1 is connected to the third fourth input of element 2 and the first input of element 3, the output of which is connected to the third, fourth input of element C and the first input of element 5, the output of which is connected to the third, fourth input of element 6. In FIG. . 2 shows timing charts 16 and 17, respectively, on tires of the first and second phases of the clock feed; timing diagram 18 si | - cash on input tire 13; timing diagrams of signals, respectively, at the outputs of logic elements 1-6. The device works as follows. When a pulse arrives at the input bus 13, the first digit of the counter on elements 1 and 2 changes its internal state to the opposite. When the counter discharge goes from state 1 to line 0, output transfer pulse 1 appears at the output of element 1. The presence of feedback allows you to store the result of 5 addition. The state (the positive pulse of the first discharge of the counter is removed from the output of element 1, the second discharge from element 3, and the third discharge from element 5.

FIG. 1 at the counter outputs are given the corresponding degrees of its bits: 2 °, 2 -P-,

When the pulses on the buses 10–12 are set to zero on elements 2, i and 6, the pulses are compensated for the state of the meter bits, i.e. counter reset.

If it is necessary to write the code of a certain number, the values of the digits of the recorded number are supplied to the unit buses 7–9 of the unit.

The clock supply system of the counter circuit is two-phase, with each next input impulse of the term arriving via bus 13 through two phases (one clock) of transmitting information along the circuit elements (Lig.2, Chart 18).

The first-phase clock pulse reads information from elements 1, 3 ° and 5, the second phase reads from elements 2, 3, and 6. The pulses arrive on the input bus 13 during the second-phase clock pulse.

The clock supply bus H (phase 2) 35 is connected to the fourth input of elements 1 and 5 and the first input of element k, and the clock supply bus 15 (phase 1) to the fourth input of element 3 and the first input of element 2 and 6. This means that the inputs during the clock pulses of the first and second phases of each clock cycle are given signals, i.e. in the absence of pulses on the first and second inputs of elements 1.3 and 5, they 5 are generators of negative polarity signals, and in the absence of -. VII pulses at the third and fourth inputs of elements 2, k, and 6, they are positive-50 polarity signal generators.

Example 1: The first-cycle clock pulse of the first clock cycle, according to the logic of an element recorded in the truth table, records bus 15 + 1 to the first input of element 2; a negative signal from element 1 is transmitted to the third input of the element

2 and -1 is written to it. So that-. The second pulse of the first phase transmits the first (positive) pulse through the bus 13 to the first input of element 1 and writes +1 into it, and also writes to the fourth input of the element 1 on the bus T -1. The clock pulse of the first phase of the second cycle records the bus 15 +1 at the first input of element 2. The clock pulse in the second phase of the second cycle records bus 1 1-1 I to the fourth input of element 1, a positive signal from element 2 records +1 to the second input of element 1 and leaves the counter to form the first bit d.

The resulting counter status is 0.01.

Example 2. The second pulse of the second phase of the second clock cycle is transmitted via bus 13 to the second (positive) pulse at the first input of element 1 and writes +1 to it. The clock pulse of the first phase of the third clock cycle transmits a positive signal from element 1 and writes -1 to the fourth input of element 2 and +1 to the first input of element 3, and also records bus 15 -1 to the fourth input of element 3 and +1 to the first input element 2, the second-cycle clock pulse of the third cycle records the k + bus at the first input of the element C and -1 at the fourth input of the element 1. The clock pulse of the first phase of the fourth cycle transmits a positive signal from the element k, which is recorded +1 at the second input of the element

3and exits the counter (the image of the second bit d.

The resultant state of the counter is 010.

Example 3. A third-phase pulse (pulse pulse) is transmitted by the pulse pulse of the second phase of the third cycle to the first input of element 1, and +1 is written to it. The clock pulse of the first phase of the fourth cycle records bus 15–15 to the fourth input of element 3 and +1 to the first input of element 2. The second phase clock pulse of the fourth cycle transmits a positive signal from element 2, which is written +1 to the second input of element 1 and goes from the counter, the image is the first bit and also writes on the bus} k +1 to the first input of the element and -1 to

7 1001i 868

the fourth input of the element 1. The clock counter is generated by the ano-impulse of the first phase of the fifth tact. A positive signal is transmitted from

element k, which is recorded by the use of the proposed second input of the element zlie, the switch provides, in comparison with iziz counter, a second bit, known technical solution also simplifies to write down the meter bus 15, namely reducing

on the first input of the element 2 and -1 on the equipment of each bit of the record the fourth input of the element 3. on one four-input ternary

The resulting count-to-logic state and the decrease in the number of 011. Of the quality of connections between the elements, and

With the arrival of subsequent them, also reducing the number of phases of tact-pulses on a mine of 13 working double feeds to two.

Claims (2)

Invention Formula Binary pulse counter containing the input bus, the bus of the first phase of the clock supply, the bus of the second phase of the clock supply and the bits, each of which contains installation buses to zero and one to two four-input ternary elements, the first input of the first four-input ternary logic element in each bit de, except for the first one, is connected to the output of the first four-input ternary logic element of the previous bit, the first input of the first four-input logic common element of the first bit of the connection is connected to the second input of the first four-input ternary logic element, the fourth input of which in odd and even bits is connected to the tires of the second and first phases of the clock power supply, differing in that, that, in order to simplify the scraper, the first input of the second four-input ternary logic element in odd and even bits is connected respectively to the buses of the first and second phases of the clock supply, each 10,610 ohm discharge the third input of the first and the second input of the second chetyrehvhodovyh ternary logic elements are connected respectively to install rails and zero to one, the output of the first metyrehvhodovogo ternary logic element coupled to the third and fourth inputs of the second NAND gate chetyrehvhodovogo threefold. Sources of information taken into account in the examination 1. USSR author's certificate number 692095, class, H 03 K 23/10, 1979. 2. Authors certificate of the USSR .G 782166, cl. H 03 K 23/10, 1980 (prototype. g / 5 / ng T 70 // 0JL iFulses source power t record write „4 read„ about f Well - & counts & (knowing, 1, 1 04 .g 8x. G7 9 l x.J OGT R q) us.i P (ROZO 18 IS 1 (II  b (g) 0 fie2 gamt i fOffr / I TOftr 31 tant 5 taff t 7 TerffrS kU m ill ll PU:, v b Y,