SU1084982A1 - Versions of code-to-pulse repetition frequency converter - Google Patents

Abstract

1. Code converter to pulse repetition rate, containing a pulse counter, the outputs of which are connected to the corresponding first inputs of the code matching unit, the output of which is connected to the output bus, characterized in that, in order to increase the speed of the converter, a delay element is inserted into it, a reversible counter pulses, the storage register, the first and second controlled frequency dividers, the frequency divider, the output of which is connected to the control input of the storage register and through a delay element with summing A reverse pulse counter, whose setup input is connected to a pulse counter recording enable input, a frequency divider zero setting inputs, and first and second controlled frequency dividers, an output bus and a storage register unit setting input, the installation inputs of which are connected to the corresponding outputs of a reverse pulse counter and the control inputs of the second controllable frequency divider, and the outputs are connected to the corresponding control inputs of the first controllable frequency divider, the even input is connected to the reference frequency bus and the counting input of the frequency divider, and the output is connected to the counting input of the second controlled frequency divider, the output of which is connected to the subtracting input of the pulse counter, the setup inputs of which are respectively connected to the constant number code buses, the input code buses are respectively connected to the second inputs of the match block (L Codes. 2. Code converter to pulse repetition rate, containing a pulse counter, the outputs of which are connected to the corresponding first outputs of the code matching unit, the output of which is connected to the output bus, characterized in that, in order to increase the speed of the converter, a delay element is inserted into it, a reversible counter pulses, the storage register, the first and second controlled frequency dividers and the frequency divider, the output of which is connected to the control input of the storage register and through the delay element with the subtractor the input of the reversible pulse counter, the setup input of which is connected to the resolution enable input of the pulse counter, the installation input of the zero frequency divider and the first and second controlled frequency dividers, the output bus and the installation input of the storage register unit

Description

The set inputs of which are connected to the corresponding outputs of the reversible pulse counter and the control inputs of the second controlled frequency divider, and the outputs are connected to the corresponding control inputs of the first controlled frequency divider, the counting input of which is connected to the output of the second controlled frequency divider, the counting input which is connected to the bus

the reference frequency, wherein the output of the first controlled frequency divider is connected to the counting input of the frequency divider and the subtractive input of the pulse counter, the setup inputs of which are respectively connected to the buses of the constant number code, and the buses of the input code are respectively connected to the second inputs of the code matching block.

The invention relates to automation and can be used in devices for generating pulse frequency signals.

A known converter of a code into a pulse repetition rate, comprising a pulse generator, the output of which is connected to the input of a pulse counter, the setup inputs of which are respectively connected to the outputs of the register, the inputs of which are connected to the corresponding outputs of the counting device c} The disadvantage of the device is low speed operations and the inability to directly enter the frequency code.

The closest to the invention to the technical essence is a code converter into a pulse repetition rate, comprising a pulse counter, the outputs of which are connected to the corresponding first inputs of a code matching unit, the output of which is connected to an output width, the second inputs are connected to the corresponding outputs of a digital function code converter, and the output is connected to the output bus and the reset input of the pulse counter, the counting input of which is connected to the width of the reference frequency NW.

A disadvantage of the known converter is the low speed due to the need to pre-convert a digital code according to a given law.

The purpose of the invention is to increase the speed of the converter.

The goal is achieved by the fact that a pulse counter with outputs connected to the corresponding first inputs of the code match block whose output is connected to the output bus is added to the code converter in order to repeat the pulses, the output of which is connected to the output bus, a delay element is added, a reversing pulse counter, a storage register , the first and second controlled frequency dividers, a frequency divider, the output of which is connected to the control input of the storage register and through a delay element with a summing input reverse pulse counter, the setup input of which is connected to the enable input of the pulse counter recording, the inputs of the zero frequency divider installation and the first and second controlled frequency dividers, the output bus and the installation input of the storage register unit, the setup inputs of which are connected to the corresponding outputs of the reversing pulse counter and controlling the inputs of the second controlled frequency divider, and the outputs are connected to the corresponding Control inputs of the first controlled frequency divider, the counting input It is connected to the reference frequency bus and the counting input of the frequency divider, and the output is connected to the counting input of the second controlled frequency divider, the output of which is connected to the subtractive input of a pulse counter, the setup inputs of which are respectively connected to the constant number code buses

In this way, the input code buses are respectively connected to the second inputs of the code matching block.

In the code converter to the pulse repetition frequency according to the second variant, containing a pulse counter, the outputs of which are connected to the corresponding first inputs of the code matching unit, the output of which is connected to the output bus, a delay element is additionally inserted, a reversible pulse counter, a storage register, and the first and second controlled frequency dividers and a frequency divider whose output is connected to the control input of the storage register and through a delay element with the subtractive input of a reversible pulse counter, The input of which is connected to the enable input of the pulse counter recording, the installation input of the zero frequency divider and the first and second controlled frequency dividers, the output bus and the setup input of the storage register unit, the installation inputs of which are connected to the corresponding outputs of the reversing counter, pulses and control the inputs of the second controlled frequency divider, and the inputs are connected to the corresponding control inputs of the first controlled frequency divider, the counting input of which is connected to the output of the first controlled frequency divider, the counting input of which is connected to the reference frequency bus, while the output of the first controlled frequency splitter is connected to the counting input of the frequency splitter and the subtracting input of the pulse counter, the setup inputs of which are respectively connected to the fixed-code code and the input code respectively connected to the second inputs of the code matching block.

FIG. 1 shows the structural electrical circuit of the converter according to the first embodiment; in fig. 2 - the same, according to the second option.

The converter in both variants contains frequency divider 1, delay element 2, reversible pulse counter 3, storage register 4, controlled frequency dividers 5 and 6, pulse counter 7, code matching unit 8, reference frequency bus 9, output bus 10, bus 11 output codes, 12 constant code codes

The elements of the device in the first embodiment are connected as follows.

The counting inputs of dividers 1 and 5 are connected to bus 9, the output of frequency divider 1 to the inputs of delay element 2 and storage register 4, the output of delay element 2 to summing input of a reversible counter 3 pulses, the outputs of which are connected to the corresponding inputs of controlled divider 6 frequency and with the inputs of the storage register 4, the outputs of which are connected to the control inputs of the controlled frequency divider 5, the counting output of which is connected to the counting input of the frequency divider 6, the output of which is connected to the subtracting input of the pulse counter 7, the output You are associated with the first. the inputs of the block 8 matches the codes to the second inputs of which the converted frequency code is fed over bus 1 and the output is connected to the output bus 10, to the recording resolution input of the subtracting counter 7 pulses, to the inputs of setting zero dividers 1, 5, and 6 frequencies, as well as the inputs of the recording unit of the reversing counter of 3 pulses and the storage register 4. Tires 12 of a constant number code are connected to the corresponding setup inputs of the subtracting counter 7 pulses.

The elements of the device according to the second embodiment are connected as follows.

Reference frequency bus 9 is connected to the counting input of controlled frequency divider 5, the output of which is connected to the subtractive input of a pulse counter and counting input of divider 1. The output of divider 1 is connected to the control input of the storage register 4 and to the input of delay element 2 whose output is connected with the subtracting reversing input of the pulse counter 3, the outputs of which are connected to the corresponding inputs of the storage register 4 and the frequency divider 6. The inputs of the frequency divider 5 are connected to the outputs of the register 4 storage. The outputs of the subtracting counter 7 pulses are connected to the first inputs of block 8, the codes, to the second inputs of which the output frequency code is fed through bus 11, and the output of block 8 is connected to the recording enable input of the pulse counter 7, from the output

bus with the inputs of the installation of zero frequency dividers 1, 5 and 6, with the entry for recording the number 10 of the reversing counter of 3 pulses and the input for writing the unit of the register 4. Tires 12 of a constant number code are connected to the corresponding setup inputs of the subtracting counter 7 pulses.

The Converter in the first embodiment works as follows.

At the moment the next pulse arrives at the output frequency bus 10, the dividers 1, 5 and 6 frequencies are set to zero, the starting number, for example 2000, the register 4 and the counter 3 is written to the unit code, is written to the bus meter 12. The duration of these operations performed simultaneously does not exceed the reference frequency period, after which the next cycle begins to form the output frequency period: at the first step ut, the total divisor ratio of the 5 and 6 frequencies is equal to one and the code in the subtracting counter 7 pulses decreases from 2000 to 1000. At the second step, ut, a pulse is sent from the output of the 1 frequency divider, rewriting the unit code from the reversible counter of 3 pulses to the register 4 and adding 3 units to the counter, as a result of which the total division factor divides 5 and 6 becomes equal to (p-1), where n is the step number, and the code in counter 7 decreases in the second step to 5000. The process of decreasing the code in counter 7 continues until it becomes equal to the frequency code set on the second inputs of block 8, match codes. At this point in time, the output of block 8 receives a pulse, which completes the formation of the next period of the output frequency and the nodes of the device are set, as described, to their original position. The code change in counter 7 is related to the change in the parameters of the device nodes and the current time, measured from the beginning of the next period as follows:

2 166

% UN

126

1000 500

250

52-5

where NJ is the number in

counter 3; DN-, counter 7; N-. - change the code in

numbers in the counter 7; tiller value is the total division ratio of dividers 5 and 6; - current time from the beginning of the next period. It is clear from the example that at the moment of equality of the number in the counter 7, the frequency code specified on the buses 11 on the bus 10 of the output frequency receives a pulse with a period corresponding to the given frequency,

When the code of the frequency being changed is changed, the change in the generated period occurs immediately, i.e. The device has good dynamic properties, which allows it to be implemented as a complete functional module (for example, in the CAMAC or GPS standard), which is interfacing with any digital automation device.

In the first variant, the error of the converter is less in the region of small values of frequency. If it is necessary to form high values of frequency, it is preferable to use the converter according to the second variant, since in the first case the nodes of the polyline realized by the device are arranged with an equal step in time, and in the second variant - with an equal step in frequency.

The Converter according to the second variant operates as follows.

At the moment the next pulse arrives at the output bus 10, the dividers 1, 5 and 6 are set to zero, the initial number, for example, 1100 Hz, is written to the counter 7 via bus 12, the number 10 to the register 4, and the duration simultaneously The operations performed do not exceed the reference frequency period, after which the formation of the next output frequency period begins; in the first step, the division ratio of dividers 5 and 6 is equal to ten and during 1000 μs (at reference frequency 10 ° Hz) the code in counter 7 is reduced to 1000 Hz, and the output divider 1 p steps one

7

the pulse, which registers the number 10 from counter 3 into register 4, after this, the contents of counter 3 are decremented by one. In the second step, the transfer ratio of dividers 5 and 6 is equal to

90

, resulting in a code

100

g-s

Now let's say that the code for the output frequency is 500 Hz. The result of the integration is compared with a given code at a point in time, which is 2000 µs behind the beginning of the generated period, and due to the location of kinks with a step of 4F, the error in the region of small period values is small.

Technical and economic effect of the proposed code converter

eight

counter 7 decreases by 100 Hz in 111 µs, i.e. for the current time value of 1111 µs, the 900 Hz code in counter 7 corresponds. The code change in counter 7 is associated with the parameters of the nodes and the current time, counting from the beginning of the next period, as follows:

The pulse repetition frequency in both variants is to increase the speed and improve the dynamic characteristics in comparison with the known devices, which makes it preferable to use it in digital automation devices and measuring equipment, in particular, in a software-controlled test signal generator for automating the control of a specialized process control system.

v) 1t.g

Claims (2)

1. A code to pulse repetition rate converter, comprising a pulse counter, the outputs of which are connected to the corresponding first inputs of the code matching block, the output of which is connected to the output bus, characterized in that, in order to increase the speed of the converter, a delay element is introduced into it, a reverse counter pulses, storage register, first and second controlled frequency dividers, frequency divider, the output of which is connected to the control input of the storage register and through the delay element with a summing input p a versatile pulse counter, the installation input of which is connected to the enable input of the pulse counter recording, the zero-frequency divider and the first and second controlled frequency dividers, the output bus and the installation input of the storage register unit, the installation inputs of which are connected to the corresponding outputs of the reversible pulse counter and control the inputs of the second controlled frequency divider, and the outputs are connected to the corresponding control inputs of the first controlled frequency divider, the counting input to torogo coupled to bus reference frequency and counting input of the frequency divider, and an output connected to the counting input of the second managed divider often ¹ you whose output is connected to the subtraction input of the pulse counter, adjusting the inputs of which are respectively connected to buses code constant number, wherein the input code bus respectively connected to the second inputs of the block matching codes. 2. A code to pulse repetitive frequency converter, comprising a pulse counter, the outputs of which are connected to the corresponding first outputs of the code matching unit, the output of which is connected to the output bus, characterized in that, in order to increase the speed of the converter, a delay element is introduced into it, a reverse counter pulses, storage register, first and second controlled frequency dividers and a frequency divider, the output of which is connected to the control input of the storage register and through a delay element with a subtracting input p an eversive pulse counter, the installation input of which is connected to the enable input of the pulse counter recording, the input of zero setting of the frequency divider and the first and second controlled frequency dividers, the output bus and input of the installation of the register register unit 1084982, the installation inputs of which are connected to the corresponding outputs of the reverse the pulse counter and the control inputs of the second controlled frequency divider, and the outputs are connected to the corresponding control inputs of the first controlled frequency divider the input of which is connected to the output of the second controlled frequency divider, the counting input of which is connected to the reference frequency bus, while the output of the first controlled frequency divider is connected to the counting input of the frequency divider and the subtracting input of the pulse counter, the installation inputs of which are respectively connected to the buses of the constant code code, and input code buses are respectively connected to the second inputs of the code matching block.