SU1064444A1 - Device for checking pulse sequences - Google Patents

Abstract

A DEVICE TO CONTROL THE PULSE SEQUENCE, containing an input bus, an OR element, three triggers, the first and second AND elements, the first inputs of which are connected to the inverse and npHNEJM outputs of the first trigger, which are different in that Two counters are introduced, a clock bus, the third, fourth, fifth, sixth and seventh elements. And the output of the latter is connected to the first input of the OR element, the second and third inputs of which are connected respectively to the outputs of the third and fourth elements. And the first inputs of which are connected respectively to the direct and inverse outputs of the first trigger, the clock input of which is connected to the input bus, to the first input of the seventh And element and from the second .tm inputs of the first and second And elements, the outputs of which are connected respectively to the zero inputs of the first and second counters and are connected respectively to the clock inputs of the second and third flip-flops, the forward outputs of which are connected respectively to the second and third inputs of the seventh And element and are connected respectively to the first the inputs of the fifth and sixth elements And, the outputs of which are connected respectively to the clock inputs of the first and second counters, the outputs of which are connected respectively to the zero inputs of the second and third triggers and are connected respectively to the second inputs S of the third and fourth elements And, the clock bus is connected to the second inputs of the fifth and sixth elements I.

Description

The invention relates to a pulse, and computing technology and can be used in devices that control the information processing equipment.

A device for controlling pulses is known, which contains two elements OR, a delay element, a trigger, a reversible counter and an actuator ij.

However, this device does not detect the loss of an even number of pulses, since after this the first incoming input pulse will overturn the trigger in the opposite state, which will correspond to the normal operation of the device, and does not detect the appearance of excess pulses. So, for example, if there are two spurious impulses between two main buses: impulses occur on different input buses, then the normal cycle of the trigger and counter operation does not break. Besides, this

device does not show up

spurious pulses, the duration of which exceeds the period of the pulses at one of the input buses, and does not reveal the appearance of a constant false 1 in the input sequence.

The closest to the present invention is a device comprising an input bus, an OR element, two delay elements, three flip-flops and two AND elements, the second inputs of which are connected to the output of the OR element, the first inputs of the first and second elements AND are connected respectively to inverse and direct outputs the first trigger, the clock input of which is connected to the output of the first element And, with zero inputs of the second and third triggers, is connected through the first delay element to the clock input of the second trigger and to the input of the second delay element the stroke of which is connected to the clock input of the third flip-flop, whose information input is connected to the forward output of the second flip-flop and to the zero input of the flip-flop 2J.

However, the known device is characterized by insufficient reliability of control, since it does not reveal the appearance of spurious pulses, the duration of which due to a malfunction of the source of pulses or interference in the communication line exceeds the time interval between two or more pulses in a controlled sequence. This is because at the beginning of the

the interrogation signal at the output of the second delay element the second trigger will be in OJ since it will work later after the first delay element has been processed. Thus, due to the overlap in time of single (interrogation) signals, at the outputs of the elements of delays. The fault indicated is not you wits. .

In addition, the lack of reliability of the control of the pulse sequence by a known.-Device also lies in the fact that it does not detect the appearance of a false signal in the sequence in the form of a constant potential of the type false 1. This is due to the fact that the first two triggers of the known devices are triggered on the falling edge, which cannot be due to the specified fault. The purpose of the invention is to increase the reliability of the control.

I.

The goal is achieved by

that the device for controlling the pulse sequence containing the input bus, the OR element, three triggers, the first and second elements AND, the first inputs of which are connected respectively to the inverse and direct outputs of the first trigger, includes two counters, a clock bus, third, fourth, n the second, sixth and seventh elements are AND, the output of the last is connected to the first input of the OR element, the second and third inputs of which are connected respectively to the outputs of the third and fourth elements AND, the first inputs of which are connected respectively with and inv pc outputs of the first trigger, the clock input of which is connected to the input bus, with the first input of the seventh element And and with the second inputs of the first and second elements And, the outputs of which are connected respectively to the zero inputs of the first and second counters and connected respectively to the clock inputs of the second and third triggers , the direct outputs of which are connected respectively. but with the second and third inputs of the seventh element And and connected respectively to the first inputs of the fifth and sixth elements And whose outputs are connected respectively to the clock inputs of the first and second counters, the outputs of which are connected respectively to the zero inputs of the second and third triggers and connected respectively to the second the inputs of the third and fourth elements And, the clock bus is connected to the second inputs of the fifth and sixth elements And Figure 1 shows the functional diagram of the proposed device; 2-4 - temporary diagrams of “l his work. The device (figure 1) contains the input bus 1, the first trigger 2, the first and second elements And 3 and 4, the second and third triggers 5 and 6, the fifth and sixth elements And 7 and 8, the first and second counters 9 and 10 , the third, -the true and the seventh elements And 11-13,. the element OR 14, the clock bus 15, the output bus 16 of the device. In Fig. 1, the input bus is connected to the clock input of the trigger 2, the first input of the element I 13 and the second inputs of the elements I. 3 and 4, the first inputs of which are connected respectively to the inverse and direct outputs of the trigger 2 and connected respectively to the first inputs of the elements And - 11 and 12, the second inputs of which are connected respectively with zero inputs of flip-flops 6 and 5 and connected respectively to the outputs of counters, kov 10 and 9, the zero inputs of which are connected respectively to the outputs of elements I 4 and 3 and connected respectively (5 with clock inputs flip-flops 6 and 5, etc. The output outputs of which are connected respectively to the eye and the third inputs of the elements AND, and connected respectively to the first inputs of the elements AND 8 and 7, the outputs of which are connected respectively to the clock inputs of the counters 10 and 9, the clock bus 15 connects to the second inputs of the elements AND 7 and 8, the input and output of the element OR 14 are connected respectively by the outputs of the elements 11-13 and the output bus 16. Figure 2 shows the timing diagrams of the signals respectively on the input bus 1, on the inverse output of the trigger 2, on the output of the AND 3 element, at the trigger output 5, element output And 7, at the output of the counter 9, at the output of element And 4, at the output of trigger 6, at the output of element And 8, at the output of counter 10, at the outputs of the elements. and 11-13 on bus 15 with no errors in the controllable sequences. In FIG. 3, signals are shown on the input bus 1, on the inverse of the trigger 2, at the output of the element 3, at the output of the trigger 5, at the output of the element 7, at the output of the counter 9, at the output of the element 4, at the output of the trigger 6, at the output of the element I 8, at the output of the counter 10, at the outputs of the elements 11-13, on the bus 15 when there is a loss of impulses and if there is a false occurrence of impulses in the trowned sequence. Figure 4 shows the timing diagram of the signals, respectively, on the input bus 1, on the inverse output of the trigger 6 (2) at the output of the element And 3, at the output of the trigger 5, at the output of the element And 7, at the output of the counter 9, on. the output of the element 4, at the output of the trigger 6, at the output of the element 8, at the output of the counter 10, at the outputs of the elements 11 11-13, on the bus 15, when a controlled sequence of spurious pulses appears, whose duration exceeds the follow-up period of the controlled pulses. In the initial state, all the triggers and counters are in the zero state. The operation of the device in the absence of errors in the monitored pulse sequence is illustrated by the timing diagram (Fig. 2). The first pulse of the monitored pulse sequence with its trailing edge switches trigger 2 into one state, and through element 3 it confirms the zero state of counter 9 and with the rear front it switches trigger 5 into unit state. As a result, at the end of the first monitored pulse, blocking occurs at the first input of element 3 and unblocking the first input of element 4 at the end of the specified impulse. In addition, at the end of the specified impulse, an enable signal (single) is applied to the first input of element 7, after which From the bus 15, through the element 7, arrive at the clock input of the counter 9, which is configured for at least one period of the pulse sequence of the monitored sequence. The next second pulse of the controlled sequence with its trailing edge throws trigger 2 into the zero state, and through the second element And 4 confirms the zero state of the counter 10 and with the trailing edge switches the trigger 6 into the single state. Since the counter 9 is set for the period of the following impulses, at the end of the second controlled (input) pulse it triggers and, with its output (single) signal, resets the trigger 5 to the zero state. Thus, at the end of the second monitored pulse, blocking occurs at the first input of element 4 and unblocking the first input of element 3 at the end of this pulse. In addition, at the end of the specified pulse, the first input of the element 8 comes from the output of trigger 6 , and the prohibitory (zero) signal is connected to the first input of the element 7 from the output of the trigger 5. After that, the clock pulses from the bus 15 through the element And 8 pass.

| D t to the clock input of counter 10, which is configured, like counter 9, for at least one period of the pulse sequence of the input sequence. During the counting of clock pulses by the counter 10, the counter 9, with its output signal, polls the state of flip-flop 2 using the element 12. Since by the time the counter 9 is triggered, the flip-flop 2 of the second (even) monitored pulse translates into the zero state, triggered and the original zero signal is preserved at its output. In this case, the output of the element And 13 also retains the original. Zero signal, since the triggers 5 and b work in anti-phase. The next third pulse of the controlled sequence, with its trailing edge, switches trigger 2 to one state, and, through the IZ element, resets counter 9 to the zero state and cocks trigger 5 to one state. After that, the counter 9 is restarted, and the counter 10 is triggered and by its output single signal resets the trigger 6 to the zero state. During the counting of clock pulses by the counter 9, the counter 10 produces with its output signal a polling of the state of the first trigger, and consequently, the state of the pulse sequence at a given time, using element 11. Since by the time the counter 10 triggers, the trigger 2 has a third (odd ) the controlled pulse is transferred to the single state, the And 11 cell fails to operate and the initial zero signal is preserved at its output. In the future, the device will work. Similarly to that described above. Thus, if there are no errors in the monitored pulse sequence, then at the outputs of the elements 11 11 and 13, and therefore on the device bus 16, no alarms are generated. In this case, the polling pulse state is polled alternately by counters 9 and 10.

Consider the operation of the device with the loss of pulses in a controlled sequence and if they appear false in this sequence. The principle of operation of the device in these cases is explained by the timing diagram (Fig. 3). The first pulse of the controlled pulse sequence produces in the circuit of the device the same changes that were described above. Suppose that the second and third pulses fall out of the pulse sequence (in FIG. 3).

these pulses are shown by a dotted line). At the end of the specified first period of the pulses of the monitored sequence, the counter 9 is triggered, which, with its output signal, resets the trigger 5 to the zero state and polls the trigger state 2. As the second pulse occurs, the trigger 2 retains its previous (single) state As a result, the element And 12 is triggered and at its output an error signal is generated, which comes through the element OR 14 to the bus 16 of the device. This error signal will retain its value until a next pulse arrives on the input bus 1, since the latter switches trigger 2 to the zero state. After this, the normal operation of the device is restored.

Suppose that between two main pulses there are one spurious pulse, in this case (timing diagram in FIG. 3), the sequence of operation of the triggers 5 and 6, t counters 9 and 10 is broken. Due to the presence of a false pulse, a premature triggering of the trigger 6 (5) occurs, which triggers the element I 13, at the output of which a pulse is generated. This alarm signal comes in the form of a cut OR 14 on the bus 16 of the device.

When an even number of false pulses appear between the two main pulses (two false pulses are shown between the two main pulses in the time diagram of FIG. 3), the sequence of operation of the triggers 5 and 6 is also disturbed, as well as when an odd number of false pulses appear. In this case, counters 9 and 10 do not have time to work, since they are prematurely reset to O by false pulses. As can be seen from the timing diagram of FIG. 3, the operation of the flip-flops 5 and 6 overlap in time, which leads to the triggering of element I 13, at the output of which pulsed signals are emitted. These signals pass through the element OR 14 to the bus 16 of the device, signaling that there are errors in the pulse train. Thus, the proposed device detects the disappearance of a subset of an even number of pulses, as well as the appearance of any number of false pulses.

Consider the operation of the device when false pulses appear in a controlled pulse sequence, the duration of which exceeds the pulse duration of the specified sequence and the appearance of a false false signal of the false one type. The device operation in these cases is explained by the time diagram (Fig. 4) . Suppose that, after the first two normal pulses, the bus 1 of the device receives a false signal at the time the third impulse begins to operate. At the same time, the duration of this false signal overlaps in time the next fourth pulse. In this case, there is a disruption in the normal operation of the circuit elements due to the fact that instead of two successive pulses, it appears with one long pulse. This leads to the fact that there is a desynchronization of the operation of the trigger 2 and the counter 10. As a result, the element 11 is triggered and an error signal is generated at its output, which passes through the element 14 on the device bus 16. If a false pulse of the specified duration occurs at the moment of the start of a clear pulse, then the trigger 2 and counter 9 are out of sync. In this case, an error signal is generated at the output of the AND 12 element, which passes through the OR 14 element to the device bus 16. After the arrival of successive normal pulses, operation of the device is restored. Suppose that, after successive normal pulses, the bus 1 of the device arrives at the instant the next pulse starts to act, a false constant signal of the false 1 type. Then, the counter 9 (10) will start from the previous pulse of the normal pulse, and a single polling signal will be generated at its output. Since the trigger 2 retains its previous state after the arrival of this false signal, the polling signal from the counter output (10) passes through the AND 12 (AND 11) element and the OR 14 element to the bus 16 of the device as an error signal. Thus, the proposed device detects the appearance of spurious pulses, the duration of which exceeds the period of the pulse sequence in the monitored sequence and reveals the appearance of spurious signals in the form of a constant signal of the false 1- type. Thus, the use of new elements and connections allows us to obtain a new set of features that favorably distinguish the proposed device from the prototype, since it increases the reliability of the control. The use of the proposed device in comparison with the prototype increases the reliability of monitoring the pulse sequence due to the possibility of detecting false pulses, the duration of which exceeds one period of the pulse of the sequence being tested and detecting false signals in the form of a false potential of the type I.

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Claims (1)

DEVICE FOR CONTROLLING A PULSE SEQUENCE, containing an input bus, an OR element, three triggers, the first and second AND elements, the first inputs of which are connected respectively to the inverse and direct outputs of the first trigger, characterized in that, in order to increase the reliability of control, two counter, clock bus, third, fourth, fifth, sixth and seventh AND elements, the output of the latter is connected to the first input of the OR element, the second and third inputs of which are connected respectively to the outputs of the third and fourth element s, the first inputs of which are connected respectively with the direct and inverse outputs of the first trigger, the clock input of which is connected to the input bus, with the first input of the seventh element And and with the second inputs of the first and second elements of And, the outputs of which are connected respectively with zero inputs the first th second counters and are connected respectively to the clock inputs of the second and third triggers, the direct outputs of which are connected respectively to the second and third inputs of the seventh element And and are connected respectively to the first inputs p of the sixth AND element, the outputs of which are connected respectively to the clock inputs of the first and second counters, the outputs of which are connected respectively to the zero inputs of the second and third triggers and disconnected respectively from the second inputs of the third and fourth I elements, the clock bus is connected to the second inputs of the fifth and the sixth elements of I. ’ Fig f SU. „, 1064444