SU1064275A1 - Information input device - Google Patents

Abstract

1. A DEVICE FOR INPUT OF INFORMATION, containing a keyboard, the bit buses of which are connected to the inputs of the encoder, the elements OR-NOT and TH-NOT, the output register of which are the outputs of the device, characterized in that, in order to increase the reliability of the inputted input and increase the speed of the device, it introduced a priority block, counter, inverter and one-shot. the inputs of the Eluent I-NOT are connected to the keyboard by the keyboard buses, the control output of which is connected to the second input of the OR-NOT element, the installation inputs of the counter and the decoder, the outputs of which are connected to the register synchronization inputs, the information inputs of which are connected to the outputs of the parallel code of the priority block informational inputs of which are connected to the outputs of the encoder, the output element AND-NOT connected to the input of the one-shot, the output of which plug to the first input of the element OR-NOT, the output of which is connected to the mouth By the single input of the priority block, the control output of which is connected to the counter input of the counter and through an inverter with a gate input of the decoder, the information inputs of which are connected to the outputs of the counter ..: -. c & 2. The software device of claim 1, which is based on the fact that the priority block contains triggers and the element ILY NOT, the C-inputs of the triggers are informational inputs of the block, the output of the element OR-NOT connected to the J-inputs and K - the trigger inputs are the control output of the block, the R inputs of the triggers is the Setup input of the block, the 3D outputs of the triggers are the output of pa4 ;; the parallel block code. ND: L

Description

The invention relates to computing and can 6fcjTb used in keypads for entering information.

A device for inputting information is known, comprising a keyboard, a one-shot, the input of which is connected to the output of the NAND circuit, the NOR circuit, the counter and the register 1.

The disadvantage of this device is the low accuracy of the input, since when two or more keys are simultaneously triggered, the input information is distorted.

Closest to the present invention is an information input device containing an OR-NOT circuit, a register, an AND-NOT element, an encoder, and a keyboard, with the closing contacts of the first switches connected to the output of the AND element, the breaking contacts of the first switches connected to the corresponding inputs of the indicator and the OR element, and the disconnecting contacts of the second switches are connected in series with each other and connected to the zero input of the trigger, the single input of which is connected to the output of the OR element, and the output connected to The first input of the element is And, the second input of which is connected to the output of the higher register bit, the outputs of the other bits of which are the device outputs, and the inputs are connected to the output of the encoder (2.

A disadvantage of the known device is also low reliability of the input information, due to its distortion when you press two or more keys and from the bounce of the keyboard contacts.

The purpose of the invention is to increase the reliability of the input information and increase the speed of the device.

The goal is achieved by the fact that in the input device containing the keyboard, the bit buses of which are connected to the inputs of the encoder, the elements OR-NOT and NAND, the register, the outputs of which are the outputs of the device, the priority block, the counter, the decoder, are additionally entered. an inverter and a one-shot, and the inputs of the element AND-NOT are connected to the keyboard bit buses, the control output of which is connected to the second input of the element OR-NOT, the installation inputs of the counter and the decoder, the outputs of which are connected to the synchronizing the register inputs / informational inputs of which are connected to the outputs of the parallel code of the priority block whose information inputs are connected to the outputs of the encoder, the output of the AND-NOT element is connected to the input of the one-vibrator, the output of which is connected to the first input of the Element OR NOT, the output of which is connected to the installation input of the block the priority, the control output of which is connected to the counter input of the counter and through an inverter with a gate input of the decoder, the information inputs of which are connected to the outputs of the counter.

The priority block contains triggers and an OR-NOT element, the C inputs of the triggers are information inputs of the block, the output of the OR element NOT is connected to the 1 inputs and the K inputs of the triggers, and the TH inputs of the triggers are The installation input of the block, the outputs of the flip-flops are the outputs of the parallel code of the block.

FIG. 1 shows a diagram of the proposed device; in fig. 2 is a priority block diagram.

The device comprises a keyboard 1, an encoder 2, an AND-HE element 3, a one-shot 4, an element OR-NOT 5, a priority block 6, a counter 7, a decoder 8, an inverter 9, decades 10 / components of register 11.

The priority block 6 will erase from the five triggers 12-16 and the element OR NOT 17.

The information input device operates as follows.

The device is brought to its original

Reset

keystroke status

connected to the control output of the keyboard 1, while the signal of the logical unit arriving at the second input of the element OR NOT 5 sets 1K-triggers 12-16. unit 6 priority to the zero state, when the outputs of the latter set the signals zero, which are received at the information inputs of the decade 10 register 11. The same control signal is fed to the installation, the inputs of the counter 7 and the decoder 8, while the counter is reset in which the direct outputs of the flip-flops contain logic zero signals, and the logic outputs of the decoder 8 generate signals of the logical unit at the outputs of the reset signal frame 10, and since the information inputs of decade 10 contain logical zero signals, then decades are set to the initial (zero) state.

When operating the device, characters (symbols) are encoded by pressing certain keys. Before encoding the next character (symbol), you must release all the keys.

The device allows you to work with a short key press.

those. keys do not need to hold and; pressed state until the information is read into the technical system, it is enough to hit them with your fingers.

When the keys of the keyboard 1 are pressed, the signals of the logical zero are sent: (voltage drop from one to zero) to the corresponding inputs of Shifter 2, where the character (symbol) is encoded in the hexadecimal system.

Encoded signs (symbols) in the form of signals. Logical zero and units are received at the information inputs of priority block 6, while signals in the form of voltage drops from high level to low (logical zero) switch the corresponding 1K triggers 12-16 of priority block 6, at the same time, the signal from the direct output of one of the triggers, block 6 of priority through the element OR NOT through inputs I and K prohibits the triggering, i.e. blocks all IK triggers from repeated tripping or bounce, i.e. when two keys are pressed, a lock occurs — priority triggering of triggers in time on the first event, which eliminates the repeated typing of information and increases the device speed (the time for entering information into the technical system is reduced).

Simultaneously with pressing any key, the logical zero signal is fed to the inputs of the NAND 3 element, while the logical unit signal from the output of the NAND 3 element is inverted at the input of the one-vibrator, the first KS flip-flop which switches d capacitance (the time constant of the KS circuit is chosen longer than the chatter time) i.e. -for capacitance charging at the output of the second SK-flip-flop of the one-shot 4, holding the signal of the logical unit and the Priority unit does not zero. In addition, the signal from the element OR-NOT 17 of the priority block through the inverter 9 is fed to the inputs of the decoder 8 logic circuits and gates it so that at the corresponding output of the circuit there appears a signal of the logical unit that permits the recording of information in the corresponding decade 10 of the register 11 .

For example, if when entering the decimal number 1256 the last key of the character 6 was pressed, then the code of the digit 6 will be written in the fourth decade, i.e. Rchetchik counts the number of keystrokes, depending on this occurs in the corresponding decade of the register.

In addition, as soon as the capacity is charged, the second SR flip-flop of the one-vibrator 4 switches and the priority block 6 is reset by the R-inputs, and the signal from the OR-NOT element at the front of the J and K inputs inhibits operation, i.e. blocks all IK triggers from repeated tripping or bounce, i.e. in the case of pressing two keys, blocking to priority triggering of triggers in time occurs at the first event, which eliminates the repeated typing of information and increases the speed of the device (the time for entering information into the technical system is reduced).

Simultaneously with pressing any key, the signal of a logical zero enters the inputs of the AND-NOT 3 element, and the signal of a logical unit

0 from the output of the element AND-NOT 3 is inverted at the input of the one-shot, the first SK flip-flop of which is switched, at the same time the capacitance starts charging through a resistor (constant

5 times, the CC circuit is chosen longer than the bounce time, i.e. during the charging time of the capacitance, the output of the second SK-flip-flop of the one-shot 4 holds the signal of the logical unit and

0 priority scheme is not zero. In addition, the signal from the element ILINE 17 of the priority block through the inverter 9 is fed to the inputs of logic circuits of the decoder 8 and gates 5 its inputs so that a logical Unit signal appears at its corresponding output, which allows recording information in the corresponding decade 10 of register II.

0

For example, if when entering the decimal number 1256 the last one was pressed. that key of the 6 character, the code of the digit 6 will be recorded in the fourth decade, i.e. the counter counts the number of keystrokes and depending on

5 this is recorded in the corresponding decade of the register.

In addition, as soon as the capacitance is charged, the second SK-flip-flop of the one-shot 4 switches and

0 reset of block 6 of priority by R-inputs, and the signal from the element OR-NOT 17 on the front from zero will increase the content of counter 7 by one,. The address of the next character (symbol) in the corresponding decade will be prepared.

When all keys are released, the first SR flip-flop of the one-shot 4 switches / gs to the initial state and

0 device is ready to enter the next character (symbol). .

Thus, the device is triggered on the first event, i.e. on the 25 § 25 keys, while locked

fixing other events, i.e. Pressing another key or bounce contacts. In addition, the performance is improved when entering large amounts of information, since

Under

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the device allows to correct input code errors character-by-character, in case of marked distortions not to resort to resetting from the register 11 correctly typed characters.

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FIG 2

Claims (2)

1. A DEVICE FOR INPUT INFORMATION, comprising a keyboard, the bit buses of which are connected to the inputs of the encoder, OR-NOT and Y-NOT elements, a register, the outputs of which are the outputs of the device, characterized in that, in order to increase the reliability of the input information and increase the device’s performance, a priority block, a counter, a decoder, an inverter and a single-vibrator / input of the AND element are entered — NOT connected to the bit buses of the keyboard, the control output of which is connected to the second input of the OR-NOT element, the setting inputs of the counter and an decoder whose output is connected to the synchronizing inputs of the register, the information inputs of which are connected to the outputs of the parallel code of the priority block, the information inputs of which are connected to the outputs of the encoder, the output of the AND gate is connected to the input of the one-shot, the output of which is connected to the first input the OR-NOT element, the output of which is connected to the installation input of the priority block, the control output of which is connected to the counter input of the Counter and through the inverter with the gate input of the decoder, information s inputs are connected to the outputs of the counter. 2. The device according to claim 1, characterized in that the priority block contains triggers and an element ILL-NOT, where the C-inputs of the triggers are information inputs of the block, the output of the OR-CE element is connected to J-inputs and 'K-inputs of the triggers and is the control output of the block, the R-inputs of the triggers are the installation input of the block, the outputs of the triggers are the outputs of the parallel code of the block. Q sl> 0