SG11201508969QA - Method for producing hybrid substrate, and hybrid substrate - Google Patents
Method for producing hybrid substrate, and hybrid substrateInfo
- Publication number
- SG11201508969QA SG11201508969QA SG11201508969QA SG11201508969QA SG11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA SG 11201508969Q A SG11201508969Q A SG 11201508969QA
- Authority
- SG
- Singapore
- Prior art keywords
- hybrid substrate
- producing
- substrate
- producing hybrid
- hybrid
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013096512 | 2013-05-01 | ||
PCT/JP2014/061807 WO2014178356A1 (en) | 2013-05-01 | 2014-04-21 | Method for producing hybrid substrate, and hybrid substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201508969QA true SG11201508969QA (en) | 2015-12-30 |
Family
ID=51843484
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201508969QA SG11201508969QA (en) | 2013-05-01 | 2014-04-21 | Method for producing hybrid substrate, and hybrid substrate |
Country Status (7)
Country | Link |
---|---|
US (1) | US9741603B2 (en) |
EP (1) | EP2993686B1 (en) |
JP (1) | JP6168143B2 (en) |
KR (1) | KR102229397B1 (en) |
CN (1) | CN105190835B (en) |
SG (1) | SG11201508969QA (en) |
WO (1) | WO2014178356A1 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3034252B1 (en) * | 2015-03-24 | 2018-01-19 | Soitec | METHOD FOR REDUCING METALLIC CONTAMINATION ON THE SURFACE OF A SUBSTRATE |
US10014271B2 (en) * | 2015-11-20 | 2018-07-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and method of manufacturing the same |
JP6549054B2 (en) | 2016-02-02 | 2019-07-24 | 信越化学工業株式会社 | Composite substrate and method of manufacturing composite substrate |
US11361969B2 (en) * | 2017-07-14 | 2022-06-14 | Shin-Etsu Chemical Co., Ltd. | Device substrate with high thermal conductivity and method of manufacturing the same |
US11211259B2 (en) | 2018-04-20 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for embedded gettering in a silicon on insulator wafer |
FR3087297B1 (en) * | 2018-10-12 | 2021-01-08 | Commissariat Energie Atomique | THIN FILM TRANSFER PROCESS |
US11232974B2 (en) | 2018-11-30 | 2022-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication method of metal-free SOI wafer |
KR102250895B1 (en) * | 2019-12-23 | 2021-05-12 | 주식회사 현대케피코 | Method for fabricating the semiconductor device |
CN112599470B (en) * | 2020-12-08 | 2024-10-29 | 上海新昇半导体科技有限公司 | Silicon-on-insulator structure and method thereof |
KR102427718B1 (en) | 2021-01-11 | 2022-08-01 | 주식회사 트랜스코스모스코리아 | A customer consultation system and method through two-way screen sharing |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3237888B2 (en) * | 1992-01-31 | 2001-12-10 | キヤノン株式会社 | Semiconductor substrate and method of manufacturing the same |
JP2895743B2 (en) * | 1994-03-25 | 1999-05-24 | 信越半導体株式会社 | Method for manufacturing SOI substrate |
DE69917819T2 (en) * | 1998-02-04 | 2005-06-23 | Canon K.K. | SOI substrate |
FR2816445B1 (en) | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE |
KR100401655B1 (en) * | 2001-01-18 | 2003-10-17 | 주식회사 컴텍스 | A smart process with alumina dielectric layer formation using ALE and a manufacturing method of unibond type SOI wafer |
JPWO2003046993A1 (en) * | 2001-11-29 | 2005-04-14 | 信越半導体株式会社 | Manufacturing method of SOI wafer |
JP4720163B2 (en) * | 2004-12-02 | 2011-07-13 | 株式会社Sumco | Manufacturing method of SOI wafer |
FR2935536B1 (en) * | 2008-09-02 | 2010-09-24 | Soitec Silicon On Insulator | PROGRESSIVE DETOURING METHOD |
FR2938702B1 (en) * | 2008-11-19 | 2011-03-04 | Soitec Silicon On Insulator | SURFACE PREPARATION OF SAPHIR SUBSTRATE FOR THE PRODUCTION OF HETEROSTRUCTURES |
FR2938975B1 (en) * | 2008-11-24 | 2010-12-31 | Soitec Silicon On Insulator | METHOD FOR PRODUCING A SILICON-TYPE HETEROSTRUCTURE ON SAPPHIRE |
JP5443833B2 (en) * | 2009-05-29 | 2014-03-19 | 信越化学工業株式会社 | Method for manufacturing bonded SOI substrate |
FR2950734B1 (en) | 2009-09-28 | 2011-12-09 | Soitec Silicon On Insulator | METHOD FOR BONDING AND TRANSFERRING A LAYER |
FR2954585B1 (en) * | 2009-12-23 | 2012-03-02 | Soitec Silicon Insulator Technologies | METHOD FOR MAKING A HETEROSTRUCTURE WITH MINIMIZATION OF STRESS |
FR2957190B1 (en) | 2010-03-02 | 2012-04-27 | Soitec Silicon On Insulator | PROCESS FOR PRODUCING A MULTILAYER STRUCTURE WITH THERMOMECHANICAL EFFECT DETOURAGE |
CN102130037B (en) * | 2010-12-27 | 2013-03-13 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process |
KR101512393B1 (en) * | 2010-12-27 | 2015-04-16 | 상하이 심구 테크놀로지 주식회사 | Method for preparing semiconductor substrate with insulating buried layer by gettering process |
JP5926527B2 (en) * | 2011-10-17 | 2016-05-25 | 信越化学工業株式会社 | Manufacturing method of transparent SOI wafer |
JPWO2013105634A1 (en) * | 2012-01-12 | 2015-05-11 | 信越化学工業株式会社 | Thermal oxidation heterogeneous composite substrate and manufacturing method thereof |
CN104488081B (en) * | 2012-07-25 | 2017-09-19 | 信越化学工业株式会社 | The manufacture method and SOS substrate of SOS substrate |
-
2014
- 2014-04-21 US US14/785,724 patent/US9741603B2/en active Active
- 2014-04-21 WO PCT/JP2014/061807 patent/WO2014178356A1/en active Application Filing
- 2014-04-21 EP EP14792333.8A patent/EP2993686B1/en active Active
- 2014-04-21 JP JP2015514836A patent/JP6168143B2/en active Active
- 2014-04-21 CN CN201480024384.9A patent/CN105190835B/en active Active
- 2014-04-21 SG SG11201508969QA patent/SG11201508969QA/en unknown
- 2014-04-21 KR KR1020157030444A patent/KR102229397B1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JPWO2014178356A1 (en) | 2017-02-23 |
US9741603B2 (en) | 2017-08-22 |
JP6168143B2 (en) | 2017-07-26 |
EP2993686B1 (en) | 2021-05-26 |
CN105190835A (en) | 2015-12-23 |
KR102229397B1 (en) | 2021-03-17 |
KR20160002814A (en) | 2016-01-08 |
EP2993686A4 (en) | 2016-11-30 |
EP2993686A1 (en) | 2016-03-09 |
WO2014178356A1 (en) | 2014-11-06 |
CN105190835B (en) | 2018-11-09 |
US20160071761A1 (en) | 2016-03-10 |
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