SE534346C2 - Integrated chip including trench - Google Patents

Description

30 534 346 without joints in the waveguide. The chip includes a number of waveguides and components, all of which are formed by etching this basic structure. Such a chip offers low manufacturing costs in combination with a high manufacturing yield, so-called yield.

A problem when transmitting and receiving optical signals is the risk of optical and electrical crosstalk between different components. This is especially true in the case where laser components and light detector components are arranged in the same integrated chip. There may be problems with unwanted reflections in joints or interfaces such as the connection port to the optical fiber or from other interfering scattering lights.

In addition, there may be unwanted such light from externally arranged components of the type lasers, LEDs and the like, as well as scattered light from imperfections in waveguides and gratings as well as spontaneous emission from optically active material in the chip itself.

Especially in integration applications, the physical distance between components is often small, and the risk of both electrical and optical crosstalk is therefore great.

Thus, the invention relates to an integrated chip for data or telecommunication or optical analysis for one, two or more wavelengths, wherein the chip has a basic structure equal from a carrier and upwards over the entire surface of the chip, where formed at the upper surface of the chip, and where the chip comprises monolithically the basic structure comprises projecting waveguides, integrated components, and is characterized in that a trench is etched along at least one of the sides of one of the waveguides and down to an etching depth at least so large that the trench is optically insulating and at least 534 346 a wall of the trench arranged closest to a waveguide exhibits at least one of the properties firstly that it is corrugated, the corrugated wall constituting a lattice-based optical component, and secondly that it is angled so that light incident on the waveguide is reflected towards the ditch wall and towards the substrate of the chip or out of the chip.

The invention will now be described in detail, with reference to exemplary embodiments of the invention and the accompanying drawings, in which: Figure]. is a perspective view of a monolithic integrated optical signal chip according to a first preferred embodiment of the present invention; Figure 2 is a top view of the integrated chip shown in Figure 1; Figure 3 is a perspective view of a monolithic integrated optical signal chip according to a second preferred embodiment of the present invention; Figure 4 is a top view of the integrated chip shown in Figure 3; and Figures 5a-5c are cross-sectional views through A-A in Figure 2, illustrating the detailed design of a trench wall in accordance with the present invention.

Figure 1 schematically shows a monolithically integrated chip 1, before metallization, with a connection waveguide 2, a A chip with such properties is known from the Swedish patent optical coupler 6 and two output waveguides 4, 5. 4. One or both of the waveguides 4, 5 can also function as an input waveguide for the coupler 6. According to the invention, the chip 1 is intended for data or telecommunication or optical analysis for one, two or more wavelengths.

The chip 1 comprises a waveguide 2 with a first port 3, where the port 3 is arranged to conduct light into or out of the guide 2. The waveguide 2 is expanded, in an expanded part in the form of an optical coupler 6, from the first the gate 3 in the direction of a second waveguide 4 and a third waveguide 5. The various components of the chip 1 are monolithically integrated. In other words, the chip has a basic structure that is equal from a carrier and upwards over the entire surface of the chip, and the waveguides 2, 4, 5 are formed at the upper surface of the chip by etching the basic structure down so that projecting waveguides are formed.

Figure 2 shows an integrated chip similar to that of Figure 1.

Corresponding parts have the same reference numerals in all figures.

The monolithically integrated components included in chip 1 share a common ground plane, namely the substrate in chip 1, which constitutes the n-side of the structure. In addition, there are layers of material which form a p-side of the chip 1, whereby a p-junction arises.

Along at least one of the sides of one of the waveguides there is a ditch 7. The ditch 7 is produced by etching the monolithically integrated material structure in the chip 1 from the top of the chip 1 down to an etching depth which is at least so large that a ditch achieved which is optically and preferably also electrically insulating. According to a preferred embodiment, at least one n-layer of the chip 1 is etched down. through, or at least to a depth reaching down to the pn junction itself or down to the pn junction itself except in only a few, preferably a maximum of 3, material layers, alternatively at least down to the first occurring, in the etching direction down the genonx material , the n-layer except soul on only a few, preferably a maximum of 3, material layers, alternatively to a depth that at least passes the actual pn junction.

It is especially preferred that the ditch 7 reaches a depth of between 50 and 5000 nm, preferably between 200 and 2000 nm.

Such etching depths provide good insulating properties optically as well as electrically (see below).

The trench 7 illustrated in the figures runs on both sides of all the waveguides 2, 4, 5 of the chip 1. However, the trench 7 can run either along only parts of one or more waveguides, surround one or more waveguides or surround one or more components on chip 1. This is shown below.

By means of the ditch 7 an effective optical isolation of the affected waveguide is achieved with respect to stray light which falls towards the waveguide from directions which are shielded by means of the ditch 7. Such stray light may originate from adjacent components or sub-components such as from an integrated laser, but may also be of, for example, spontaneously emitted light from the coupler 6 itself or light incident on the chip 1 from the outside.

Figure 5a illustrates in cross section a preferred embodiment of a ditch 7 according to the present invention. A waveguide, in this case the third waveguide 5, is provided with a ditch 10 15 20 25 30 534 346 7. The figure is not scalable for clarifying reasons. According to a preferred embodiment, at least one wall 55 of the ditch 7 which is arranged closest to the waveguide 5 is vertical.

In this case, the chip 1 is advantageously formed of absorbent material 8 on the side of the ditch 7 on which the waveguide 5 is not located.

Since incident, unwanted stray light L is reflected back into the absorbent material 8 due to the vertical wall 55, such stray light L can be prevented from spreading further. It is preferred that the amount of absorbent material 8 between components or sub-components of the chip 1 insulated from each other is sufficient to extinguish substantially all such reflective scattering light L. Thus, according to a preferred embodiment, the smallest distance between two adjacent, parallel ditches, each are arranged to insulate each waveguide, at least 25 μm. It is also preferred that grounded or back-tensioned contact surfaces be used with the chip 1 to improve the absorption of unwanted light L in the absorbent material 8.

Figure 5b illustrates, in a manner similar to Figure 5a, a second preferred design of the wall 55. At least one wall of the ditch 7 arranged closest to the waveguide 5 is thus angled so that light L incident on the waveguide 5 is reflected against the ditch wall 55. out of the chip l.

Similarly, Figure 5c illustrates a third preferred embodiment of the wall 55, wherein at least one wall of the ditch 7 arranged closest to the waveguide 5 is angled so that light L incident on the waveguide 5 is reflected against the ditch wall 55 down towards the substrate 1 of the chip 1, which is generally not absorbent. This can in many cases lead to the unwanted stray light being distributed over a larger volume of material, which is desirable. On the other hand, the light risks being reflected back to sensitive areas in the chip. In addition, there is a risk of interfering patterns between the walls of the chip. Therefore, in some applications, it is preferred to use either the first or the second preferred design of the wall 55 as described above.

As appears from the Swedish patent 0501217-4, the material system in a monolithically integrated chip 1 according to the present invention can be designed with different materials. However, the material structure usually consists of a number of layers of different semiconducting materials, mainly consisting of As, P, Ga, In and / or Al. There are several suitable ways of making a monolithic integrated grating that can be used as a laser cavity or filter in accordance with the present invention. The active material may further consist of a bulk storage, a MQW structure (Multiple Quantum Well) or a combination of QD (Quantum Dots).

In order to achieve a good insulation of a certain guide, it is preferred that a respective ditch runs along both sides of at least one guide. In other words, the waveguide in question is optically used by means of a ditch in accordance with the invention along its two sides, so that the influence of incident scattering lights in the waveguide and on components arranged along the waveguide is significantly reduced.

According to a particularly preferred embodiment, which is also illustrated in Figures 1-4, the ditch 7 is arranged to run along and around all the guides 2, 4, 5 arranged in one component, so that all these guides 2, 4, 5 are surrounded by the ditch 7. In fact, the ditch 7 as illustrated in Figures 1 and 2 does not describe a closed curve. The reason for this is that light is conducted in and out of the first waveguide 2 through the gate 3, so an opening in the ditch 7 must be arranged in front of the gate 3. That the ditch 7 "surrounds" all waveguides 2, 4, 5 is here also intended to comprise designs where the ditch 7 has such openings where connections to one or more waveguides are present. As mentioned above, the waveguides 4, 5 may also comprise gates for directing in and out light, in which case the ditch 7 is provided with openings in front of such gates.

If several components are arranged next to each other with transport waveguides arranged to conduct light between components, it is preferred that a ditch is arranged to surround all these components including transport waveguides, however with openings for any external gates. In case a chip is to be split, it is preferred that no ditch is arranged along a waveguide at the place of splitting, as such a ditch can cause splitting errors.

The unwanted currents that cause electrical crosstalk between different components in the chip 1 occur largely in the p-material or via the pn-transition. Thus, in the case where the ditch 7, when surrounding the group of waveguides 2, 4, 5, intersects the p-side and the pn junction of the chip 1 around the whole group, the group will be substantially electrically isolated from interfering electrical crosstalk from other parts. of the chip 1. Such an arrangement thus means that a very good optical as well as electrical insulation can be provided by a group of waveguides 2, 4, 5 on the chip 1.

According to a particularly preferred embodiment, an array of components is arranged on one and the same chip 1. Such a chip may for instance comprise a number of components of the type illustrated in Figures 1 and 2, wherein each component comprises a first waveguide 2, a second waveguide 4 and a third waveguide 5. The second waveguide 4 comprises a laser for emitting light. The third waveguide 5 includes a light detector for detecting light. In this case, the sub-components can advantageously be monolithically integrated.

Through an expanded part in the form of an optical coupler 6, light is conducted from the laser to the first waveguide 4 and further out through the gate 3, and light is conducted from the gate 3, via the first waveguide 2 and up to the light detector in the third waveguide. Different components are provided with respective lasers and light detectors to emit and receive light of different respective wavelengths.

Each component in this case is preferably isolated from other components by means of a respective surrounding ditch in accordance with the above described, which means that a number of such components can be produced on one and the same chip 1 and can be operated there without significant crosstalk between components. nenter. Such fabrication of a plurality of component conductors on one and the same chip entails low manufacturing costs, for example for applications in which lights with a plurality of different wavelengths are to be handled in parallel.

Those skilled in the art will appreciate that a plurality of components may be arranged on one and the same monolithically integrated chip 1 in several different ways. For example, a plurality of lasers and / or light detectors for different wavelengths can be arranged in separate waveguides isolated from each other on one and the same chip 1. Some components of the chip 1 can also be cascaded one after the other, by means of optical couplers, where each each component is optically and electrically isolated from other components in the manner described above, with openings in the trench for transport waveguides and so on. In this way, for example, triplexers can be built up, with two lasers and a photodetector operating at separate wavelengths.

The individual components of the chip can then be encapsulated individually without the material itself being divided. A chip with arrays of components can then be packaged (optically aligned) against a fiber ribbon, or a ribbon cable of parallel optical fibers, allowing all components in the array to be connected to a common multi-channel control electronics circuit, which is cost-saving and in addition, it saves physical space. This in turn means that smaller premises are required and therefore means an energy saving.

In many applications, optical filters are used as components of monolithically integrated chip 1 of the present type. According to a preferred embodiment, at least one such optical filter is provided in the chip 1 by modifying a trench which runs along the waveguide in which the filter is to be arranged.

This is illustrated in Figures 3 and 4, in which an optical filter 52 is arranged along the third waveguide 5.

Thus, the part of the ditch 7 which runs along the section of the third waveguide 5 at which the filter 52 is arranged is located at such a distance from the waveguide 5 that the optical mode in the waveguide 5 is influenced by the inner wall of the ditch 7 closest to the waveguide 5. 53, and also possibly the bottom of the ditch 7. 54, so that the ditch wall 53 and / or the bottom of the ditch is corrugated so that a first-order filter function is achieved.

The corrugation 54 of the ditch wall 53 or the bottom of the ditch is effected, like the ditch 7 itself, preferably by means of etching, in a manner known per se. The distance of the ditch 7 from the guide wire 5 and the physical geometry of the corrugated wall 53 determines the functionality of the filter 52 in terms of filtration strength, fitting / blocking band, etc., in a conventional manner.

The present inventors have surprisingly discovered that the size, in the planes 1 and 4 of the chip 1), (the plane illustrated in the figures of the ditched area of the ditch 7 and the total etched volume of material affects the quality of the corrugated side wall 53 or ditch bottom. Too small an area makes it difficult for the process gases to access the etching front, resulting in deteriorating physical structure of the corrugated wall, which is of course not desirable as this affects the properties of the filter 52. to vigorous regrowth during etching, which also impairs the structure of the corrugated side wall 53 or ditch bottom.

It has been found that good etching results can be obtained regarding the corrugation of the ditch wall 53 if the ditch 7 is at least 0.1 μm, preferably at least 0.5 μm, wide and a maximum of 1000 μm, preferably a maximum of 250 μm wide. The width of the ditch 7 is the dimension of the ditch 7 seen in Figure 4 perpendicular to the longitudinal direction of the third waveguide 5.

It has also been found that particularly good etching results can be achieved in the case where the cross-sectional area of the ditch 7, perpendicular to its main direction of propagation, is between 0.005 and 5000 μm, preferably between 0.1 and 500 μm.

In order to achieve good filtering ability, it is preferred that such a monolithically integrated filter 52 comprises at least about 100 grating periods, each grating period being about between 50 and 300 nm. The distance between the ditch 7 and the waveguide 5 is preferably between 0 and 10 μm at the location of the filter 52, and in other places preferably between 0 and 500 μm.

In accordance with a preferred embodiment, the ditch may be exposed to air, which gives a high refractive index difference.

It can also be covered by a dielectric such as SiO 2, SiNm BCB or equivalent, which gives a lower refractive index difference but on the other hand better physical protection for the filter and / or the ditch. This choice depends, for example, on the enclosure used for chip 1.

It is also possible to provide other grid-based optical sub-components by adapting a wall of the ditch 7 which is closest to a certain waveguide. Examples include lasers and diffractive couplers, the latter of which can be used to couple light from the waveguide to an adjacent waveguide.

By providing lattice-based optical sub-components in the wall of the existing trench 7 rather than as stand-alone, separately manufactured, either monolithically integrated or not, components, it is achieved that the production of the chip 1 becomes simpler and therefore cheaper. Specifically, in many cases the ditch 7 and the filter 52 can be manufactured in one and the same step.

Preferred embodiments have been described above. However, it will be apparent to those skilled in the art that many changes may be made to the described embodiments without departing from the spirit of the invention. Thus, the invention should not be limited by the described embodiments, but may be varied within the scope of the appended claims.

Claims (10)

10 15 20 25 30 534 346 13 P A 1? E N T IC R A V Integrated chip (1) for data or optical analysis for one, or telecommunication two or more wavelengths, wherein the chip (1) has a basic structure which is equal from a carrier and upwards over the entire surface of the chip, where the basic structure comprises suspension waveguides (2; 4; 5), formed at the upper surface of the chip (1), and where the chip (1) comprises monolithically integrated components, characterized in that a trench (7) is present etched along at least one of the sides of a of the waveguides and down to an etching depth which is at least so large that the ditch is optically insulating and that (53:55) closest to a waveguide has at least one of the properties at least one wall of the ditch (7) which is arranged first to it is corrugated, the corrugated wall constituting a lattice-based optical component, and secondly that it is angled so that light incident on wave (55) (1) substrate or out of the chip (1). the daren is reflected against the ditch wall and towards the chips An integrated chip (1) according to claim 1, characterized in that the etching depth is at least so large that a ditch is provided which is also electrically insulating. Integrated chip (1) according to claim 1 or 2, characterized in that the chip (1) is arranged for data or telecommunication or optical analysis for one, two or more wavelengths and can be used to emit light and to be able to detect light, and since the chip (1) comprises- (3), is expanded from the first port, a first waveguide (2) takes a first port where the first waveguide (2) (3) in the direction of at least a second waveguide (4) and a third waveguide (5). 10 15 20 25 30 35 534 345 14 An integrated chip (1) according to claim 1, 2 or 3, characterized in that at least one wall (55) of the trench (7) arranged closest to a waveguide is vertical. Integrated chip (1) according to one of the preceding claims, characterized in that the width of the ditch (7) is between 0.1 and 1000 μm. Integrated chip (1) according to one of the preceding claims, characterized in that the width of the ditch (7) is between 0.5 and 250 μm. An integrated chip (1) according to any one of the preceding claims, characterized in that the etching depth of the ditch is between 50 and 5000 nm. Integrated chip (1) according to one of the preceding claims, characterized in that the trench (7) is arranged to run along both sides of at least one waveguide. An integrated chip (1) characterized according to any one of the preceding that the ditch (7) claims, is arranged to run along all waveguides (2; 4; 5) in a component of the chip (1), on all sides of all these waveguides (2; 4; 5), so that the waveguides (2; 4; 5) are surrounded by the ditch (7) except for openings for ports in the component. An integrated chip (1) according to any one of the preceding claims, characterized in that at least one wall (53) of the ditch (7) arranged closest to a waveguide is corrugated, the corrugated wall (53) and that the grating-based optical component a grid-based optical component, nenten is an optical filter.