RU2821349C1 - Method for testing non-volatile memory chips and device for its implementation - Google Patents

Abstract

FIELD: testing non-volatile memory chips.

SUBSTANCE: invention relates to a method and device for testing non-volatile memory chips. In the method, Test 1, Test 2, Test 3, designed for testing non-volatile memory chips, are carried out selectively or sequentially after each other, at the end of each test, and the commands inside each test are executed in strict sequence: Test 1 is performed with the following sequence: C; ↑ (R1, S); ↓ (R0): the operation of erasing values in all memory cells, followed by the operation of reading memory cells in a straight sequence incrementally, and if the value of the cell is equal to logical 1, then the logical 0 is set to this cell, next comes the reading operation in the reverse sequence by decrement with the expectation of a logical 0 value; Test 2 is performed with the following sequence: C; ↑ (R1,S,R0); ↓ (R0): begins with the operation of erasing and setting logical 1, followed by the operation of reading memory cells from the beginning to the end incrementally from waiting for logical 1, after that each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all cells are read in reverse order; Test 3 is performed with the following the sequence: C; ↑ (R1,S);C; ↓ (R1,S,R0); ↑ (R0), which begins with the erase operation, after that, read and set operations to 0 from the beginning to the end, followed by the operation of reading memory cells from the end incrementally with the expectation of a logical 1, after that, each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all cells are read in direct order.

EFFECT: technical result is to expand the range of detection of defects in non-volatile memory.

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Description

The invention relates to the field of testing integrated circuits of non-volatile memory with a serial interface and can be used for testing memory chips for compliance of static parameters with technical specifications and for correct operation during operations of reading, writing and erasing data.

Testing memory chips is an important step in the manufacturing process. The increasing complexity of the structure of memory chips leads to an increase in the percentage of defective chips produced. According to experts, in the near future, 90% of the total area of a silicon wafer will be occupied by various types of memory [International Technology Roadmap for Semiconductors, 2007 Edition. URL: https://www.semiconductors.org/wp-content/uploads/2018/08/2007Design.pdf Access date: 05/27/2023]. For this reason, there is an increase in requirements for high-quality testing of memory chips. In addition, the development of memory programming technologies leads to the emergence of unknown defects.

Non-volatile storage devices are widely used in various fields of application. The main feature of this type of memory is the possibility of long-term data storage without powering the microcircuit. The complex structure (metallized layers) and high data density makes it possible to use non-volatile memory in circuits with low power consumption and low voltage, which emphasizes the importance of this type of storage devices.

Non-volatile memory chips with a serial interface have a small number of pins, due to which they take up little space on the printed circuit board, while simplifying the design of connections and wiring the chip on the board, increasing reliability and reducing noise levels.

Due to the fact that faults of random access memory devices do not fully describe the existing defects of permanent storage devices, there is a need to determine the features of the occurrence of faults in non-volatile memory.

The issue of the effectiveness of tools for testing and diagnosing faults in non-volatile memory remains relevant. The effectiveness of solutions consists of two parameters: the number of detected defects and the duration of diagnostics.

There is a known method for testing static random access memory devices in order to identify counterfeit microcircuits that were in use, based on the degradation properties of static random access memory devices (RU 2757977, IPC G01R 31/30, 10/25/2021), the essence of which is as follows: unstable bits are counted by writing the value 1 or 0 at the rated supply voltage (Vp=Vnom) into all bits of the static random access memory. Then the supply voltage is reduced to a value selected from the range 0≤Vp≤2/3Vp, which is guaranteed below the critical level of information retention by the chip. Then all the bits of the static random access memory sequentially along the word line are put into read mode for a period sufficient to discharge the RC constant of the electrical circuit. Next, the contents of the static random access memory are read and the number of bits that have changed their value (N) is counted. A static random access memory chip with a value of 1 or 0 written to all cells is subjected to stress by exposure to elevated temperature and voltage (Vstress) for a period of time Δt. The method is implemented through a combination of counting unstable bits and at least two iterations of the stress effect and counting unstable bits, wherein after the first counting of unstable bits the initial number of unstable bits N0=N is initialized, after the second counting of unstable bits the incremental number of unstable bits is counted relative to the first count of the first stress iterations ΔN1=N-N0, after the third count of unstable bits, the total incremental number of unstable bits is calculated relative to the second count ΔN2=N-N0, then the truth of the expression is calculated , whose true value indicates that the SRAM chip is “new”, and whose false value indicates “used”. Technical result: identification of used static random access memory chips using simple digital equipment without the use of precise analog measuring instruments, through the standard interface of the chip, without special requirements for its electrical and topological circuit, without a priori primary information about the properties of its physically non-clonable functions.

The disadvantages of this known method include the inability to qualitatively and accurately determine a fault on a specific bit. This method is applicable to testing random access memory devices to determine the general state of the memory based on the increment in the values of unstable bits, that is, a probabilistic determination of the suitability of the memory is made. In addition, this method is not applicable for permanent storage devices, since erasing operations are not taken into account. The method does not allow assessing the compliance of the static parameters of the memory chip with the norm.

A non-volatile memory device and a method for self-testing are known (US 2007/0165454, IPC G11C I6/04, 07/19/2007), according to which the test interface receives a test command indicating the execution of a test for a memory cell. The test storage scheme stores the test information needed to execute the test. The test memory circuit includes an erasable programmable memory block. The decoder decodes the test command entered into the test interface and selects test information stored in the test memory circuit. The sense amplifier reads from the test storage circuit the test information selected by the decoder. The storage circuit contains test information read by the sense amplifier. The control circuit controls the test operation of checking whether the memory cell is operating normally based on the test information stored in the storage circuit. A defect storage circuit is formed for a memory cell and stores fault information indicating that the memory cell is faulty if the memory cell does not operate normally in test mode. The technical result is a reduction in the testing time of a non-volatile storage device.

The disadvantages of this known method include the inability to determine which fault a specific memory cell contains. Test information is written to a specific memory cell and compared with a template (expected value), but the influence of the write operation on the value in memory cells on one bit line is not checked. The storage circuit does not analyze the effect of the erase operation on the state of the cell. This method also does not allow assessing the compliance of the static parameters of the memory chip with the norm.

A device and method for testing memory are known, intended for restoring a memory cell in a memory testing system (US 9831003B2, IPC GIIC 29/44, GIIC 29/56, 11/28/2017), in which the test device detects the fault address by checking the memory device in accordance with test command, and temporarily stores the fault address in the failure address memory (FAM). The fault address is transmitted to the storage device according to the fault address transmission mode, temporarily stored in the temporary fault address memory of the storage device, and then stored in the fuse protection array, which is a non-volatile storage device. To ensure data reliability, the stored data can be read to verify the data, and the verification result can be transmitted serially or in parallel to the test device. The technical result is an increase in the operational reliability of the storage device.

The disadvantages of the known method include the possibility of an error in transmitting the fault address from the device under test according to the algorithm for transferring the fault address. The storage circuit does not analyze the effect of the erase operation on the state of the cell. The known method is expensive and also does not allow assessing the compliance of the static parameters of the memory chip with the norm.

There is a known method for providing programmable test conditions for the built-in self-test circuit of a flash memory device (WO 2006081168, IPC G11C29/12, 08/03/2006). The method includes providing an interface (built-in self-test, BIST) adapted to configure the test conditions used in the BIST circuit, providing memory cells of the flash memory device, and providing a BIST circuit adapted for testing the flash memory. The method further comprises passing with the BIST interface one or more global variables associated with the test condition, setting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations in flash memory in accordance with the configured test condition , and report the results of memory testing operations. The method may further include a serial communication environment and using a serial test protocol to communicate global variables to the BIST interface and test results from the interface. Global variables can also be provided by the storage device user. The technical result is timely memory testing with a sufficiently high degree of fault coverage without the need for constant interactive (sequential) monitoring using external test equipment.

The disadvantages of this method include an increase in the service area of the microcircuit itself, with a possible negative impact on the functionality of the memory. The known method is mainly used for pass/fail production testing without identifying the specific fault and fault detection address necessary for process monitoring and device repair.

It should be noted that when creating a universal and reliable method for testing non-volatile memory chips, it is necessary to limit the number of fault models detected during testing, since, firstly, it makes sense to consider faults that are basic for the occurrence of other types of defects (Hamdioui S. et al . Memory fault modeling trends: A case study // Journal of Electronic Testing - 2004. - T. 20. - P. 245-255.). Since basic defects are easier to detect than more complex fault models, a faulty memory chip can be unambiguously identified with fewer resources. Secondly, the number of most likely defects is limited. In the work (Kang D. et al. Probability level dependence of failure mechanisms in sub-20 nm NAND flash memory //IEEE Electron Device Letters. – 2014. – T. 35. – No. 3. – P. 348-350. ) shows that the fault models SAF, TF, WED, WPD, BED and BPD have a higher probability of appearing in memory compared to other defects. Descriptions of all models are presented in Figure 1.

The first block of defects applies to all types of memory:

SAF – persistent faults of memory cells. The defect is characterized by the fact that the cell takes the same logical value 0 or 1 and cannot change its state when performing any actions with this cell.

TF – memory cell switching defect. The defect is characterized by the fact that when writing a value, no changes occur in the memory cell and logical 0 cannot go into logical 1 and vice versa (Kang D. et al. Probability level dependence of failure mechanisms in sub-20 nm NAND flash memory //IEEE Electron Device Letters. – 2014. – T. 35. – No. 3. – P. 348-350.).

The following block of fault models is typical for non-volatile memory.

WED (word-line erase disturbance) fault model. The violation occurs when programming a cell causes a logic 0 value in an adjacent cell on the same word line to be erased.

WPD (word-line program disturbance) fault model. The defect occurs when programming a cell causes programming at logic 0 of an adjacent cell on the same word line.

BED (line erase disturbance) fault model. BED violations are similar to WED violations, except for the location of the defective cells. For this type of interference, the affected cells are on the same bit line as the selected cell.

BPD (bit-line program disturbance) fault model. BPD violations are similar to WPD violations, but the defective cells are on the same bit line as the cell being programmed.

Fault model RD (read disturbance). The essence of the RD malfunction is that after reading the value of a memory cell, the value changes to the opposite.

OED (over-erase disturbance) fault model. OED is characterized by the fact that the threshold voltage of the selected cell is low and it is impossible to program it (in any case, the cell is in the “erased” state).

There are many ways to test memory: marching tests, chess code, galloping test and many others. The methods differ in testing time and the number of defects detected.

Below are the most commonly used memory testing methods.

Galloping test. An example of use is presented in the development of a memory testing system for measuring voltage surges on power lines (Mohammad M. G. Fault model and test procedure for phase change memory //IET computers & digital techniques. – 2011. – Vol. 5. – No. 4. – C . 263-270.). The essence of this method is to constantly write a byte into a memory cell and compare the written value with the reference value. First, byte 0000 0000 is written to the memory cell, then 0000 0001 is written and the first 7 bits are checked for changes (comparison with the standard 0000 0001). After this, the next byte 0000 0010 is written to the same cell and is also compared with the template. The process continues until the value 1000 0000 is written to this cell. Next, a cycle is started to check logical 0 and the number 1111 1111 is written to the same memory cell. The value of the number changes from the zero bit, followed by checking the remaining bits with the reference value. Thus, the galloping test allows you to carry out two test cycles to check logical 1 and 0. The described test works slowly and can require hundreds of hours on memory volumes of hundreds of MB; accordingly, this method of memory testing is advisable to use on small amounts of memory, not exceeding 6-8 KB. This method allows you to detect SAF and TF defects.

"Chess code". The essence of the algorithm is as follows: logical 1 and 0 are written to the memory cells of the cell array in a checkerboard pattern. The algorithm divides the cells into two alternating groups so that each adjacent cell is in a different group. The checkerboard pattern is mainly used to detect SAF defect and failures resulting from leakage, short circuits between cells. The steps of the algorithm include writing a "chessboard" code with the addressing order up; reading chessboard code with addressing order up; writing a reverse "chess" code with the addressing order up; Reading reverse chessboard code with addressing order up.

Marching test. These tests use patterns that "march" up and down a memory address as they write values to and read values from known memory locations. The number of march elements is finite, and each march is determined by the address sequence and the order of write and read operations. The sequence is determined by increment, decrement, or simultaneous increase and decrease of the memory cell number. The sequence is determined from the simplest operations: writing a logical 0 value to a memory cell; reading the value of a memory cell expecting a logical 0; writing a logical 1 value to a memory cell; reading the value of a memory cell and waiting for logical 1. Marching tests are easier to implement and faster to execute, which meets the requirements of the business of testing memory chips. For this reason, the diploma students chose this type of testing to implement a hardware and software complex for testing non-volatile memory chips (Li Y. et al. Design of Memory Test System for Measuring Transmission Lines Galloping //Journal of Physics: Conference Series. – IOP Publishing, 2019. – T. 1187. – No. 2. – P. 022027.; Analysis of flash memory testing methods // Reports of the Belarusian State University of Informatics and Radioelectronics. – 2010. – No. – P. 62-68.).

For non-volatile memory, conventional testing algorithms are not enough. Operations and test requirements for non-volatile memory differ from volatile memory (Yarmolik V.N., Levantsevich V.A., Demenkovets D.V. Analysis and synthesis of marching tests of storage devices //Digital Transformation. – 2021. – No. 2. – pp. 45-55.; Mohammad M.Gh., Saluja K.K., Yap A. Testing flash memories // VLSI Design 2000. Wireless and Digital Imaging in the Millennium. – P. 406–411.; Yeh J. C. et al. Flash memory testing and built-in self-diagnosis with march-like test algorithms //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems – 2007. – T. 26. – No. 6. – P. 1101-1113.). RAM, in addition to being volatile, differs from permanent memory in the absence of an erase operation. Thus, it is necessary to study testing methods taking into account the introduction of an erase operation into them (Mohammad M. G., Saluja K. K. Flash memory disturbances: Modeling and test //Proceedings 19th IEEE VLSI Test Symposium. VTS 2001. - IEEE, 2001. - pp. 218-224. ; Van der Velde D. P., vd Goor A. J. Designing a memory module tester // Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing. - IEEE, 1999. - P. 91-98.; in testing of memory using an on-chip compact testing scheme //IEEE Transactions on Computers. – T. 100. – No. 10. – P. 862-870.; ., Krupkina T. Yu. Research and development of a serial access scheme for flash memory // News of higher educational institutions. Electronics - 2016. - T. 21. - No. 5. - P. 478-481.).

To test non-volatile memory, advanced marching testing algorithms are used - Flash-March and March-FT.

Flash-March is one of the first marching tests designed for non-volatile memory (Yeh J. C. et al. Flash memory testing and built-in self-diagnosis with march-like test algorithms //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . – 2007. – T. 26. – No. 6. – P. 1101-1113.).

Its sequence is as follows (formula (1)):

C;↑(R1,S);↕(R0);C;↓(R1,S);↕(R0) (1)

Where:

Operation C - Clear means erasing memory, it sets the values of all cells to 1, the arrows indicate the direction of operations, from beginning to end or from end to beginning.

Operation R1 – Read 1 read with wait 1 in cells.

Operation R0 – Read 0, respectively, a read operation with the expectation of 0 in the read cells.

S – Set setting to 0.

The operations indicated in parentheses are performed one after another to one cell and only after execution there is a transition to the next (in the direction of the arrow) cell until the iteration reaches the end or beginning of memory.

The complexity of this test is calculated by the total number of read cycles R (Qr), set operations S (Qs), erase C (Qc) and the main argument is the memory capacity Q. Accordingly, the complexity of Flash-March I is calculated using formula (2):

(2)

March-FT is the next representative of the generation of marching tests for non-volatile memory (Yeh J. C. et al. Flash memory testing and built-in self-diagnosis with march-like test algorithms //IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. – 2007. – T. 26. – No. 6. – P. 1101-1113.).

March-FT is the following sequence (3):

C;↑(R1,S,R0);↕(R0);C;↓(R1,S,R0);↕(R0) (3)

Unlike Flash-March, this test performs a double reading of the logical zero setting. Complexity N is calculated using formula (4):

(4)

The main disadvantage of the considered marching tests is their complexity and the length of time it takes to perform diagnostics.

A method for testing non-volatile memory chips and a device for its implementation are proposed.

The method of testing non-volatile memory chips differs in that Test 1, Test 2, Test 3, intended for testing non-volatile memory chips, are carried out selectively or sequentially one after another, upon completion of each test, and the commands within each test are executed in strict sequence: Test 1 is performed with the following sequence: C;↑(R1, S);↓(R0): an operation to erase values in all memory cells, followed by an operation to read memory cells in direct incremental sequence, and if the cell value is equal to logical 1, then setting a logical 0 to this cell, then a read operation occurs in the reverse order of decrement, waiting for the value of logical 0; Test 2 is performed with the following sequence: C;↑(R1,S,R0);↓(R0): begins with an erase operation and setting logical 1, followed by an operation of reading memory cells from beginning to end incrementally with waiting for logical 1, after this means that each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and read immediately, then all cells are read in reverse order; Test 3 is performed with the following sequence: C;↑(R1,S);C;↓(R1,S,R0);↑(R0), which begins with the erase operation, after which the read and set operations go from beginning to end 0, followed by the operation of reading memory cells from the end incrementally with the expectation of logical 1, after which each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all are read cells in direct order.

A device for implementing a method for testing non-volatile memory chips contains a central computing device for supplying control signals to a power source, a multimeter and a microcontroller, a power source necessary for supplying an input voltage to the non-volatile memory chip and relay circuits, a multimeter for measuring the static parameters of the non-volatile memory chip, a microcontroller equipment board, wherein the microcontroller board of equipment consists of a microcontroller designed to send commands corresponding to the sequences of execution of the Test 1, Test 2, Test 3 commands to a non-volatile memory chip and receive from it the tested values, relay circuits designed to switch the operating mode during measurement static parameters of a non-volatile memory chip, and a transistor matrix that provides relay control from the microcontroller. The central computing device is connected to the power supply and multimeter via the USB interface and to the microcontroller of the equipment board via the USB-UART interface. A non-volatile memory chip with serial access is connected to the microcontroller via an I2C interface.

The technical problem to be solved by the claimed invention is to conduct high-quality functional testing of non-volatile memory chips.

The technical result of the claimed invention is to expand the range of detection of non-volatile memory defects: identifying SAF, TF, WED, WPD, BED, BPD, RD and OED in non-volatile memory chips, reducing the complexity and duration of testing.

To solve the stated technical problem, a method for testing non-volatile memory chips and a device for its implementation are proposed.

The method of testing non-volatile memory chips differs in that Test 1, Test 2, Test 3, intended for testing non-volatile memory chips, are carried out selectively or sequentially one after another, upon completion of each test, and the commands within each test are executed in strict sequence: Test 1 is performed with the following sequence: C;↑(R1, S);↓(R0): an operation to erase values in all memory cells, followed by an operation to read memory cells in direct incremental sequence, and if the cell value is equal to logical 1, then setting a logical 0 to this cell, then a read operation occurs in the reverse order of decrement, waiting for the value of logical 0; Test 2 is performed with the following sequence: C;↑(R1,S,R0);↓(R0): begins with an erase operation and setting logical 1, followed by an operation of reading memory cells from beginning to end incrementally with waiting for logical 1, after this means that each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and read immediately, then all cells are read in reverse order; Test 3 is performed with the following sequence: C;↑(R1,S);C;↓(R1,S,R0);↑(R0), which begins with the erase operation, after which the read and set operations go from beginning to end 0, followed by the operation of reading memory cells from the end incrementally with the expectation of logical 1, after which each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all are read cells in direct order.

A device for implementing a method for testing non-volatile memory chips contains a central computing device for supplying control signals to a power source, a multimeter and a microcontroller, a power source necessary for supplying an input voltage to the non-volatile memory chip and relay circuits, a multimeter for measuring the static parameters of the non-volatile memory chip, a microcontroller equipment board, wherein the microcontroller board of equipment consists of a microcontroller designed to send commands corresponding to the sequences of execution of the Test 1, Test 2, Test 3 commands to a non-volatile memory chip and receive from it the tested values, relay circuits designed to switch the operating mode during measurement static parameters of a non-volatile memory chip, and a transistor matrix that provides relay control from the microcontroller. The central computing device is connected to the power supply and multimeter via the USB interface and to the microcontroller of the equipment board via the USB-UART interface. A non-volatile memory chip with serial access is connected to the microcontroller via an I2C interface.

Implementation of the described method of testing non-volatile memory chips and the device for its implementation makes it possible to achieve the stated technical result - expanding the range of determination of non-volatile memory defects: identifying SAF, TF, WED, WPD, BED, BPD, RD and OED in non-volatile memory chips, reducing complexity and duration performing testing.

Thus, the technical problem of conducting high-quality functional testing of non-volatile memory chips is solved by scaling the fault coverage. Fault models can be detected at the stage of reading values in memory. In order to determine what faults the algorithm can detect, it is necessary to sequentially analyze the test commands.

Test 1 presents an algorithm with the following sequence: C;↑(R1, S);↓(R0): first, the operation of erasing values in all memory cells is performed. This is followed by an operation of reading memory cells in direct sequence by increment, and if the value of the cell is equal to logical 1, then a logical 0 is installed in this cell. Next comes a reading operation in reverse sequence by decrement, waiting for the value of logical 0.

Test 1 detects SAF and OED defects. A SAF malfunction can be detected by the first pair of commands C erase and R1 read with the expectation of logical 1. During the execution of the erase command, logical 1 is written byte-by-byte to all memory cells, then the command to read the values in these cells is triggered with direct addressing with the expectation of logical 1 and if If a logical 0 is detected, then this cell is identified as “infected” with the SAF fault constant. OED can be detected by the subsequent pair of commands S by setting 0 and R0 by reading with expectation of 0. Accordingly, if after setting 0 a logical 1 is detected by reading with reverse addressing, then an erase fault is detected in this memory cell.

Test 1 allows you to reduce testing time by 2 times.

The complexity of this test is minimal and is calculated using formula (5):

(5)

Test 2 is defined as the sequence: C;↑(R1,S,R0);↓(R0: begins with the erase operation and setting logical 1. This is followed by the operation of reading memory cells from beginning to end incrementally, waiting for logical 1. After this, each the cell from the first to the last is read, in case any of the cells have changed their values, is set to logical 0 and then read all the cells in reverse order.

Test 2, in addition to the previously described defects, allows you to detect a malfunction in reading the RD. This error can be detected at the last reading stage. After the first read with an expectation of 0, a second read with an expectation of 0 is performed, and if the read byte values differ from the first read, then this is characterized by the presence of an RD defect.

Test 2 allows you to reduce testing time by 2 times compared to the more complex Flash-March and March-FT tests.

The difficulty of this test can be determined by the following formula (6):

(6)

Test 3 has the following sequence: C;↑(R1,S);C;↓(R1,S,R0);↑(R0).

Like previous tests, the algorithm begins with an erase operation. After this, the operations of reading and setting to 0 go from beginning to end. This is followed by a repetition of the operations from Test 2, but the “march” is performed in the opposite direction. Test 3 is much more difficult than the first and second tests and, accordingly, it is assumed that this test allows detecting a larger number of defects. SAF defect can be detected on the first reading. Next, commands are made to set 0 by direct addressing, followed by an erase operation. After this pair of operations, reading with reverse addressing and waiting for 1, it will be possible to detect the switching defect of the TF. The subsequent R0 read operation detects the OED erase fault in the same way as in test 1 and 2. The last read command detects the RD read fault.

The complexity of the test is determined by formula (7):

. (7)

The device for implementing the claimed method contains a central computing device, a 5.0 V power supply with a resolution of 1 mV, a multimeter that measures direct current in the range of 200,000 μA with a resolution of 1 nA, a microcontroller at 400 kHz, a matrix of transistors (a set of switches) 50.0 V 0.35 A, electromagnetic relay 10 A, connected to outputs 1C-7C of transistor matrices, the inputs of which are connected to inputs RD0-11 of the microcontroller, operational amplifier 160 MHz, USB connector, capacitors 33 pF - 100 nF, resistors 27 - 15 k Ohm, diodes 10 V, 500 mW. Electromagnetic relays are used as switches, which are connected to the control module through transistor matrices. Using a relay instead of a microammeter allows you to reduce material costs. It is also necessary to ensure switching between contacts to set the desired measurement mode. Manual switching is time-consuming, but relays will provide a simple solution for automatic switching. Instead of a relay, you can use a simple connection and, by changing it, measure in different modes, however, using a relay controlled by the module, it is possible to measure all leakage currents without any additional actions with the measurement circuit. In addition, the use of active elements instead of relays would lead to the need to carry out metrological operations.

Memory contacts SCK, SDA are connected to the microcontroller contacts SCL and SDA, the WP input is grounded. This interface has only two communication lines - SCL and SDA, through which it is necessary to carry out parametric control. Unlike I2C, the SPI interface has 4 communication lines, which makes the process of measuring static parameters twice as complicated.

The USB/UART interface is used for communication between the microcontroller and the central computing device, as it is suitable for connecting one device and allows for fast data exchange. UART is a universal receiver-transmitter that allows you to configure the connection between a computer and a microcontroller. The UART hardware module of the microcontroller is used for reception and transmission. When transmitting data via the USB/UART interface, the exchange rate is 19200 bits, 1 stop bit.

For communication between the central computing device and the equipment, the USB/USB interface is used, since it allows you to simultaneously connect many equipment devices, in particular a power supply and a multimeter.

The device for testing non-volatile memory chips works as follows. Signals are received from the personal computer via the USB interface, containing information about all the parameters of the ROM chip being tested, as well as about all the testing conditions and the selected algorithm. Through the USB to UART interface converter, this information via the UART interface enters the microcontroller, which processes it and supplies control signals to the power source selection unit, based on which the required source is connected to the memory chip under test.

The relays are connected to outputs 1C-7C of ULN2003A transistor matrices, the inputs of which are connected to inputs RD0-11 of the microcontroller. The use of ULN2003A in key mode is due to the fact that the relay current is quite high and it is impossible to connect the relay directly to the microcontroller outputs. The circuit with relay RL1-9 allows you to measure leakage currents in different modes, switching RL10 allows you to measure current consumption, and switching RL11 allows you to measure the output voltage. By controlling the relay using a microcontroller, you can set different measurement modes. For example, by default the memory contacts SCK, SDA are connected to the microcontroller contacts SCL and SDA, respectively, the WP input is grounded. When power is applied to the RD4 input by the microcontroller, relays RL4 and RL5 switch to another position, thereby connecting SCK and SDA to ground. This switching of the relay allows you to complete the functional control and begin parametric testing, that is, begin to measure the leakage current of the microcircuit in various operating modes. The topology of the device's printed circuit board is shown in Fig. 2. Leakage current is measured at three given inputs and outputs (SDA, SCL and WP) under different operating modes of the microcircuit. Operating modes are set by supplying power or grounding each of the contacts of the memory chip. In total, it is possible to implement 6 modes of operation of the microcircuit. 4 modes for measuring leakage currents: SCL- SDA+ WP-, SCL+ SDA+ WP-, SCL+ SDA- WP+, SCL+ SDA+ WP+. One mode for measuring current consumption SCL+ SDA+ WP- and one mode for measuring low level output voltage SCL+ SDA+ WP+. A complete description of the status of the SCL, SDA and WP signals is presented in Table 1.

Table 1 – Microcircuit operating modes

Letter designation of the parameter Output to be tested IC output Supply and test voltages, V Switchable relays ILIL SCL, W.P. SCL VIL= 0 SCL: RL9, RL6, RL5; WP: RL9, RL8, RL7, RL5 S.D.A. VIH = 5.5 W.P. 0 ILIH SCL SCL VIH = 5.5 RL9, RL6, RL5, RL2 S.D.A. VIH = 5.5 W.P. 0 ILOL S.D.A. SCL VIH = 5.5 RL8, RL4, RL3, RL1 S.D.A. VO = 0 W.P. VIH = 5.5 ILOH S.D.A. SCL VIH = 5.5 RL8, RL4, RL3, RL2, RL1 S.D.A. VIH = 5.5 W.P. VIH = 5.5 ICCS VCC SCL VIH = 5.5 RL10, RL9, RL8, RL5, RL2, RL1 S.D.A. VIH = 5.5 W.P. 0 VOL S.D.A. SCL VIH =2.5 RL11 S.D.A. IOL = 3.0 mA W.P. VIL = 0.3Vcc = 0.75

A program containing ready-made algorithms for testing non-volatile memory chips, as well as various interfaces and key flags necessary for working with peripheral devices is loaded into the memory of the microcontroller (MK).

After supplying the supply voltage to the tester, the supervisor generates a reset signal and runs the program from the microcontroller’s memory. According to the program, the ports and interfaces of the microcontroller are initialized. To organize a node, you need to initialize it. To do this, you need to make the direction of the Tx port an output, and the Rx an input. Tx is the sixth bit of the TRISC register, Rx is the seventh. Next, you need to determine the value of the baud rate generator SPBRG. The value can be determined by formula (8):

SPBRG = (F_CPU /(ω*φ))-1 (8)

where F_CPU is the processor frequency, defined as the ratio of the microcontroller frequency to the clock frequency (#define F_CPU 10000000/64);

ω – processor clock frequency;

φ – data transfer rate (φ=19200).

After this, it is necessary to initialize the status and control and data transmission register TXSTA and the status and reception control register RCSTA. Next, you need to configure the serial port to use interrupts. To do this, it is necessary to set bits 4 (TXIE) and 5 (RCIE) of the PIE1 interrupt enable register to the “enable” mode, assigning the bits the value logical 1. The TXIE bit allows you to enable interruption of message transmission via UART, and RCIE will enable interruption of reception. This completes the UART initialization.

Next, the message must be transmitted via the serial port directly to the computer, according to the block diagram of the complex and timing diagram. To do this, we first wait for the interrupt flag to be received and after that it is necessary to start checking the filling of the status register and control of the RCSTA receiver, the first overflow bit is responsible for this. If it takes the value of logical 0, then there is no acceptance error, otherwise there is an error. If there is no receive error, it is necessary to disable reception by setting the CREN bit to 0. After the reception delay time has expired, it is necessary to enable reception as follows: RCSTA.CREN=1.

To write the operation of the I2C algorithm, it is necessary to describe the initialization of registers, functions for sending start, restart, stop pulses, acknowledge and reject pulses, as well as write and read functions. The write and read functions are written in several variations, to allow sending a single byte or an array of bytes. The SSPSTAT, SSPCON1 and SSPCON2 registers are required to enable the MSSP module, which allows clock signals to be supplied to the SCL module. These registers are configured differently depending on whether the interface is SPI or I2C.

The TRISC register sets the PORTC bits as inputs or outputs. For example, in order to set B6 as an output, you need to set B6 to 0. Accordingly, to configure the register as an input, you need to set the bit value to logical 1. The SSPADD register sets the frequency of data exchange via the I2C protocol, so variables are used there to calculate required frequency.

After this, it is possible to implement word transmission and reception via the I2C interface. To do this, you need to open communication between the master and slave, run a while loop, sending the memory address with the write command. While waiting until the slave device is free, restart the interface to send the message and use a for loop to write each byte.

The algorithm for reading a message received in a slave device is similar to writing, but with its own set of commands. It is important to set the NACK register correctly here, otherwise the reading will be broken. Throughout the entire duration of the active programming cycle, the microcircuit does not perceive external access via the I2C bus. The erase/write cycle time is measured (controlled) by setting the access time to the chip. If the microcircuit issues a confirmation upon subsequent access, then the programming cycle has already ended. If it does not issue, then the programming cycle still continues.

After confirming the serviceability of the tester in the software (software), you need to set all the main parameters of the memory chip under test:

operating voltage of the I2C bus of the tested microcircuit;

supply voltage;

COM port to which the tester is connected;

address bus width;

value of leakage current at the terminals depending on the test mode;

permissible value of leakage current deviation, according to specifications.

All of the above data necessary for the tester to work correctly with this memory chip is written to the registers of the microcontroller and is automatically retrieved by it during program execution. The required power source is immediately connected, the settings of drivers, comparators and loads activate the corresponding modes for measuring static parameters that control the data bus outputs.

To control devices, the IEEE-488 specification is used, which describes the interface for connecting to digital devices. This specification describes standard commands for programmable digital devices. One of these commands is the command “*IDN?” which requests the device ID. Using this command in the hardware and software complex, the multimeter and power supply are initialized by their ID. After initializing the devices, special commands from the RIGOL command system are used. This system is different for devices and is described in the documentation for them. To set the voltage, use the command ":APPLy CH1,5,0", which sets the voltage of channel 1 in the power supply to five volts. After this, the command ":OUTPut CH1,ON" is used, which opens/turns on this channel. To measure current and send measurement results to the multimeter, issue the command “:MEASure:CURRent:DC?”.

After successfully connecting the equipment and establishing communication between the control device and the microcontroller, you are given a choice of the type of testing of the integrated memory chip. To carry out functional testing (fault detection), you must select one of the tests on the left side of the screen, depending on what faults need to be investigated. Based on the testing results, a file in xml format will be generated with a detailed description of the assessment of the control performed, according to Fig. 3.

This format was chosen because it is platform independent, follows an international standard, and has a strict syntax that allows the document to be simple and consistent.

Based on the test results, an assessment of the serviceability of the integrated circuit will be provided. If a fault is detected, information about the number of faulty bytes will be provided.

In addition, the total percentage of bad bytes will be calculated. A more detailed test report will be saved in a log file.

The protocol format is as follows:

<Memory_name> declares the name of the monitoring object. Data is taken from the prepared file by user </Memory_name>

<Functional_testing> description of the functional control: name - name of the testing method, time - testing time and memory_size - capacity of the control object.

a list of faults and the bit number where the fault was detected are announced.

<Functional_outcome> declares the number of faulty bytes </Functional_outcome>

<Functional_result> declares the result of the functional control - Pass/Fail </Functional_result>. Functional test completed </Functional_testing>.

<Param_testing> start of description of parametric testing results.

<param> description of the leakage current measurement mode according to Table 1.

<Standart> description of the standard value: unit of measurement of the leakage current standard value, permissible measurement error in % and standard value according to specifications </Standart>

<acceptance> declares the result of parametric control for a given mode - Normal / Not normal <acceptance>

<Param_result> declares the result of parametric control for the microcircuit. Parametric testing completed </Param_testing>.

<Result> declares the result of functional and parametric testing - Pass/Fail </Result>

If a malfunction is detected during functional testing, the chip is considered unusable.

With parametric control, if a parameter deviates from the norm, the microcircuit is considered unusable.

As a result, the proposed invention allows for full functional and parametric control of non-volatile memory chips.

The claimed invention is illustrated by drawings, where:

in Fig. 1 provides a description of all fault models detected during testing;

in Fig. Figure 2 shows the topology of the device's printed circuit board;

in Fig. 3 presents a file in xml format with a detailed description of the assessment of the control performed;

in Fig. Figure 4 shows the complete operating algorithm of the device.

The invention is illustrated below by the following examples.

Example 1. Table 2 shows the simulation results for 256 byte (256x8) non-volatile memory, page write buffer up to 8 bytes.

Table 2 – Results of testing the IN24LC02BN memory chip

Memory size SOF CFst BPD SAF Way March FT New March FT New March FT New March FT New 8 bytes 64 (50%) 64 (50%) 3968 (53%) 4033 (58%) 540 (93%) 520 (91%) 128 (100%) 256 bytes 2014 (1%) 2163 (1.9%) 208896 (74%) 268402 (88%) 35896 (80%) 35957 (83%) 4096 (100%)

Table 3 – Average testing time for IN24LC02BN memory chip

Test method Average testing time, sec Test 1 17.58 Test 2 19.26 Test 3 34.72 Flash-March 35.48 March-FT 35.75

When using the claimed method, the fault detection time is reduced from O( ) to O( ).

Example 2. The operation of the complex was carried out according to the following steps:

Checking connected devices - power supplies and measuring instruments.

Reading voltage and current values, determining the COM port to identify the equipment board. Checking the connection of the integrated circuit and microcontroller.

Carrying out functional and parametric testing of the memory chip.

Processing and displaying test results to the user.

The complete operating algorithm of the device is shown in Fig. 4.

Test methods are described in Table 4.

Table 4 - Test methods

No. Name of check Actions Performed Expected Result Checking the connection of external virtual measuring instruments Connect the RIGOL DP832A power supply to the microcontroller equipment according to the circuit diagram of the complex.
Connect the RIGOL DM3068 multimeter to the microcontroller equipment according to the circuit diagram of the complex.
In the application, click on the “Connect power source and ammeter” button The application will display a message indicating that the power supply and ammeter have been successfully connected.
The “Go to memory chip connection” button is available. Checking the connection of the microcontroller and memory chip Set the operating voltage of the I2C bus of the microcircuit under test according to the specifications - 5 Volts.
Set the supply voltage of the microcircuit under test according to the specifications - 5 Volts.
Select the COM port for connecting the complex. If necessary, update the list of available ports.
Select the path to the file in which the microcircuit parameters are filled in according to the sample*. txt file format.
Click on the “Check the connection of the memory chip and microcontroller” button The input file has been processed.
The application will display a message indicating successful connection of the microcontroller and memory chip.
The “Go to memory chip connection” button is available. Checking Test 1 Select Test 1 from the list of functional control methods.
Select the path to save the file with the test result or leave it as default.
Click on the “Start testing” button
Click on the “To Menu” button List of defects and the number of bytes affected by these defects.
Total percentage of bad bytes.
Completed test report.
Record the test execution time. Checking Test 2 Select Test 2 from the list of functional control methods.
Select the path to save the file with the test result or leave it as default.
Click on the “Start testing” button
Click on the “To Menu” button List of defects and the number of bytes affected by these defects.
Total percentage of bad bytes.
Completed test report.
Record the test execution time. Checking Test 3 Select Test 3 from the list of functional control methods.
Select the path to save the file with the test result or leave it as default.
Click on the “Start testing” button
Click on the “To Menu” button List of defects and the number of bytes affected by these defects.
Total percentage of bad bytes.
Completed test report.
Record the test execution time. Flash-March check Select Flash-March from the list of functional control methods.
Select the path to save the file with the test result or leave it as default.
Click on the “Start testing” button
Click on the “To Menu” button List of defects and the number of bytes affected by these defects.
Total percentage of bad bytes.
Completed test report.
Record the test execution time. March-FT check Select March-FT from the list of functional control methods.
Select the path to save the file with the test result or leave it as default.
Click on the “Start testing” button
Click on the “To Menu” button List of defects and the number of bytes affected by these defects.
Total percentage of bad bytes.
Completed test report.
Record the test execution time. Checking leakage currents (can be carried out in parallel with checks in paragraphs 3-7) Select the item “Leakage current testing”.
Select the path to save the file with the test result or leave it as default.
Click on the “Start testing” button
Click on the “Close program” button Completed test report.

Thus, the above description indicates that the following set of conditions are met when using the claimed invention:

the means embodying the claimed invention, when implemented, is intended for testing memory chips for compliance of static parameters with technical specifications and for correct operation during operations of reading, writing and erasing data;

for the claimed method, as described in the stated claims, the possibility of its implementation using the means and methods described in the application has been confirmed;

the means embodying the claimed invention when implemented is capable of achieving the technical result envisioned by the applicant - expanding the range of detection of non-volatile memory defects: identifying SAF, TF, WED, WPD, BED, BPD, RD and OED in non-volatile memory chips, reducing the complexity and duration of testing .

Claims (4)

1. A method for testing non-volatile memory chips, characterized in that Test 1, Test 2, Test 3, intended for testing non-volatile memory chips, are carried out selectively or sequentially one after another, upon completion of each test, and the commands within each test are executed in strict Sequences: Test 1 is performed with the following sequence: C;↑(R1, S);↓(R0): an operation to erase the values in all memory cells, followed by an operation to read the memory cells in direct incremental sequence, and if the value of the cell is equal to logical 1 , then a logical 0 is installed in this cell, then a read operation occurs in the reverse order of decrement, waiting for the value of logical 0; Test 2 is performed with the following sequence: C;↑(R1,S,R0);↓(R0): begins with an erase operation and setting logical 1, followed by an operation of reading memory cells from beginning to end incrementally with waiting for logical 1, after this means that each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and read immediately, then all cells are read in reverse order; Test 3 is performed with the following sequence: C;↑(R1,S);C;↓(R1,S,R0);↑(R0), which begins with the erase operation, after which the read and set operations go from beginning to end 0, followed by the operation of reading memory cells from the end incrementally with the expectation of logical 1, after which each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all are read cells in direct order. 2. A device for implementing the method according to claim 1, which contains a central computing device for supplying control signals to a power source, a multimeter and a microcontroller, a power source necessary to supply the input voltage to the non-volatile memory chip and relay circuits, a multimeter for measuring the static parameters of the chip non-volatile memory, a microcontroller board of equipment, wherein the microcontroller board of equipment consists of a microcontroller designed to send commands corresponding to the sequences of execution of the Test 1, Test 2, Test 3 commands to the non-volatile memory chip and receive from it the tested values, relay circuits intended for switching operating mode when measuring the static parameters of a non-volatile memory chip, and a transistor matrix that provides relay control from the microcontroller. 3. The device according to claim 2, in which the central computing device is connected to the power supply and multimeter via the USB interface and to the microcontroller of the equipment board via the USB-UART interface. 4. The device according to claim 3, in which a non-volatile memory chip with serial access is connected to the microcontroller via the I2C interface.