RU2766271C1 - Method for ensuring fault tolerance of memory elements - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: invention relates to computing technology and automation and can be applicable in heavy duty equipment with increased requirements for reliability, e.g., in control apparatuses of rocket and space technology. The technical result is achieved due to the fact that the method provides a possibility of warding failures in the data bus, in apparatuses for input and output of the bus-forming data, as well as in memory elements. The method is especially effective for a reprogrammable permanent storage apparatus, wherein accurate information needs to be read at long intervals without recording, e.g., after a power failure.

EFFECT: increase in the reliability and fault tolerance of memory elements due to the accuracy of recording and reading of the information in the memory elements in the presence of faults in the data bus circuits.

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Description

The invention relates to computer technology and automation, and can be used in critical equipment that has increased requirements for reliability and does not have access for repair, for example, in spacecraft.

Known "Method of improving the reliability of memory modules" (Bukhanova G.V. "Highly reliable random access memory devices, development trends. Automation and telemechanics", 1993, issue 2, p. 23), which consists in recording and reading direct and reverse codes followed by bitwise comparison.

The disadvantage of this method is the low reliability due to the fact that the failure of one memory module causes the failure of the entire device.

Also known is the “Method of increasing the reliability of memory modules” (Gorshkov V.N. “Reliability of random access memory devices of computers”. L .: Energoatomizdat, 1987), which consists in the fact that in order to reserve two working memory modules, a backup module is introduced into which code combinations obtained by modulo 2 addition of two words from working memory modules with the same addresses. If one of the working memory modules fails, to correct the word written in it, an appeal is made to the working and backup memory modules, and the true word is obtained by adding the selected words modulo 2.

The disadvantage of this method is low reliability, since in the event of a failure in the circuit of any one bit of the data bus (open, short circuit), false information will be written and read into the memory elements.

The closest to the claimed solution in terms of technical essence and the achieved technical result (prototype) is the "Method of ensuring the fault tolerance of memory elements using three-channel majority redundancy" (Bukhanova G.V. "Highly reliable random access memory devices, development trends. Automation and telemechanics", 1993, issue 2, p. 13), in which all three memory elements are accessed simultaneously in the write and read modes, in the read mode information from the memory elements is majorized by the coincidence of most of the output signals.

The disadvantage of this method is low reliability, since in the event of a failure in the circuit of any one bit of the data bus (open, short circuit), false information will be written and read into all three memory elements.

The technical problem is to increase the reliability of the memory elements.

The technical problem is solved due to the fact that in the method of ensuring the fault tolerance of memory elements using three-channel majority redundancy, information is written to three memory elements sequentially: in the first element - without changes in the direct code, in the second element in the inverse code, in the third element in the direct code, but with a swapping of the bits of the first and second half of the data bus; reading is carried out sequentially from the first, second, third memory elements, the read information from the second memory element is inverted, and the information of the first and second half of the data bus bits from the third memory element is swapped, then the read information from the first memory element and the converted information from the second and third memory elements are bit-by-bit majorized. Further, the read information is checked for validity, for which the information from the first, second, third memory elements is compared bit by bit. Moreover, if the read information in the bit coincided with all three memory elements, then this bit on the data bus is faulty, and if the number of such bits located only in the first or only in the second half of the data bus is half or less than the number of data bus bits, then the information is reliable.

The technical result will be the creation of a method that improves reliability due to the reliability of writing and reading information into memory elements in the presence of faults in the data bus circuits.

The essence of the claimed method is explained as follows.

Let's remember the code:

1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - data bus bit numbers.

Suppose, in the first, second, fourth, fifth, eighth bits of the data bus, there is a constant “0” type malfunction, and in the third, sixth, seventh data bus bits there is a constant “1” type malfunction, then the recorded information will be as follows (sequence):

1) to the first memory element (in direct code)

0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

2) to the second memory element (inverted information)

0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

3) to the third memory element (in direct code, but the first byte is interchanged with the second)

0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

When reading, the information will be as follows (sequence):

1) from the first memory element

0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1

2) from the second memory element

0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0

3) from the third memory element

0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 .

Then we invert the information of the second memory element:

1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1

In the information of the third memory element, the first byte is interchanged with the second:

1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0

Now the information received from the first memory element, the inverted information from the second memory element, and the permuted information from the third memory element are bit-by-bit majorized "2 out of 3":

0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1

1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1

1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0

1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 is the result of bitwise majorization .

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - data bus bit numbers.

The value in the first, second, third, fourth, fifth, sixth, seventh, eighth digits recovered. That is, the information was stored correctly, eight faults were parried in the first half of the data bus.

We check the correctness (reliability) of the received information by bitwise comparison of information from the first, second, third memory elements:

0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 from the first memory element,

0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 from the second memory element,

0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 1 from the third memory element.

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 is the result of a bitwise comparison, where: 1 is the match result of the comparison, and 0 is not a match.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 data bus bit numbers. All ones in the first half of the data bus indicate a bus failure (8 bits in which failures were assumed), however, since the number of bits with matching information does not exceed half the bits of the data bus, the data is reliable.

Similarly, information is corrected in case of malfunctions in the second half of the data bus (in the second byte).

This method allows parrying failures in the data bus, in the input-output devices forming the data bus, and also in the memory elements.

The method is especially effective for a programmable read-only memory device, where it is necessary to read reliable information at long intervals without recording, for example, after a power failure.

Claims (1)

A method for ensuring the fault tolerance of memory elements using three-channel majority redundancy, in which information is written to three memory elements, characterized in that the memory elements are written sequentially: to the first element - in the direct code, to the second element - in the inverse code, to the third element - in a direct code, and with a permutation of the bits of the first and second half of the data bus; reading is carried out sequentially from the first, second, third memory elements, the read information from the second memory element is inverted, and the information of the first and second half of the data bus bits from the third memory element is swapped, then the read information from the first memory element and the converted information from the second and third memory elements are bit-wise majorized; then the read information is checked for validity, for which the read information from the first, second and third memory elements is compared bit by bit, and if the read information in the bit matches from all three memory elements, then this bit on the data bus is faulty, and if the number of such bits located only in the first or only in the second half of the data bus, is half or less than the number of bits of the data bus, then the information is reliable.