RU2759801C1 - Method for code frame synchronization for cascade code when applying strict solutions - Google Patents

Abstract

FIELD: discrete information transmitting.SUBSTANCE: invention relates to a means for transmitting discrete information and can be applied in systems of anti-jamming information protection. For the received input sequence, consisting of several consecutive words, each of which is a bitwise sum modulo two of the error-correcting cyclic code, the numbering sequence and the phasing sequence, a syndrome of the error-correcting cyclic code is obtained, which may correspond to one or more numbering sequences. Synchronized counters in parallel form a complete set of numbering sequences. The values ​​of these synchronized counters are incremented in parallel by one at a time interval corresponding to the transmission of one codeword. When the word number of the input sequence coincides with the value of the synchronized counter of the numbering sequence, the value of their coincidence counter is increased by one. If the number written in the corresponding hit counter exceeds or is equal to the threshold value at the end of this numbering sequence, a decision is made on the code frame synchronization of the input sequence.EFFECT: increasing the speed of information transmission in channels with a high level of interference.1 cl

Description

The invention relates to communication technology for systems for transmitting discrete information and can be applied in systems of noise-immune information protection, in which correction codes are used, in particular, concatenated codes.

When developing code frame synchronization devices, an urgent task is to increase the probability of correct synchronization, and, consequently, to increase the probability of correctly received information in communication channels with a high level of interference.

In code frame synchronization devices, synchronization signs are transmitted in words of an error-correcting code, using the redundancy of the code, and therefore the transmission of additional synchronization symbols is not required. In this case, synchronization is ensured by multiple repetition of synchronization signs in different words of the inner code of the concatenated code.

The proposed method of code frame synchronization with a high probability of correct establishment of synchronization is aimed at simplifying its implementation and at increasing the information transfer rate in communication channels with a high level of interference.

The known method of code frame synchronization [RF Patent No. 2401512 IPC H04L 7/08, publ. 10.10.2010, Bul. No. 28], which consists in the fact that the received input sequence, consisting of several consecutive words, each of which is a bitwise sum modulo two of the error-correcting cyclic code, the numbering sequence and the phasing sequence, is first multiplied by the check polynomial of the error-correcting cyclic code and, as a result of multiplication, the sum of the error-correcting cyclic code syndromes, the numbering sequence and the phasing sequence is obtained, then the resulting sum is multiplied by the check polynomial of the numbering sequence and the sum of the error-correcting cyclic code and the phasing sequence syndromes is obtained. From this sum, the phasing sequence syndrome is subtracted and the error-correcting cyclic code syndrome is obtained. Further, if the error-correcting cyclic code syndrome corresponds to an acceptable combination of errors, the numbering sequence of the received error-correcting code is extracted and compared with the numbering sequences of the previously received error-correcting cyclic codes. When comparing the numbering sequence with previously received numbering sequences, the number of hits in one of the F hit counters is stored. When the numbering sequence coincides with the previously received numbering sequences, the number in the corresponding hit counter is increased by one and, if this number exceeds the threshold value, a decision is made on the code frame synchronization of the input sequence. If the numbering sequence does not match with any of the previously received numbering sequences, the value of one is written into one of the m hit counters, the value of which is equal to zero. If there are no hit counters that have a value of zero, the value of one is written to the counter with the least number of hits. In this case, each counter is assigned numbers from one to F, as well as its own attribute in the form of a corresponding numbering sequence, and the search for the corresponding hit counter by the numbering sequence is performed by sequential cyclic selection of hit counters by their numbers, starting with the number of the hit counter to which the last entry was made the number of hits, and the search for the corresponding hit counter by the numbering sequence is performed by comparison with the numbering sequences corresponding to the hit counters, and the search for hit counters, the value of which is equal to zero or the minimum, and writing the value of one to the hit counters is also performed in a cyclic sequence of counter numbers. This method has a fairly simple implementation, however, due to sequential iterative operations using a sliding window, the computational speed decreases and, accordingly, the maximum information transfer rate decreases. The disadvantage of this method is also the insufficient probability of correctly received information in communication channels with interference, since a sliding window is used for synchronization, which is shorter than the block of information along which synchronization is carried out in the proposed method of code frame synchronization. In addition, in this method, synchronization is carried out only by codewords, the number of errors in which does not exceed the correcting ability of the code, i.e. no more than (d-1) / 2 errors, where d is the minimum code distance of the words of the Bose-Chowdhury-Hawkingham-BCH code (31,21,5). The notation (n, k, d) is used for the code parameters, where n = 31 is the code length, k = 21 is the length of the informational part of the code, d = 5 is the minimum code distance. The above method uses slow sequential iterative methods using a sliding window, which reduces the maximum information transfer rate.

Closest to the proposed method is a method of code frame synchronization for a concatenated code when using hard solutions (prototype) [RF Patent No. 2633148 IPC H04L 7/08, publ. 11.10.2017, Bul. No. 29). The method consists in the fact that the received input sequence, consisting of several consecutive words, each of which is a bitwise sum modulo two of the error-correcting cyclic code, the numbering sequence and the phasing sequence, is first multiplied by the check polynomial of the error-correcting cyclic code. As a result of multiplication, the sum of the syndromes of the error-correcting cyclic code, the numbering sequence and the phasing sequence is obtained. Then the resulting sum is multiplied by the numbering sequence check polynomial and the sum of the error-correcting cyclic code and phasing sequence syndromes is obtained. From this sum, the phasing sequence syndrome is subtracted and the error-correcting cyclic code syndrome is obtained. Further, in accordance with the syndrome, the numbering sequence of the received error-correcting code is extracted and compared with the numbering sequences of the previously received error-correcting cyclic codes. The values of the involved counters of the numbering sequences are incremented by one at a time interval corresponding to the passage of each of their words. Each bit in a contiguous sequence equal to the number of bits in the codeword of the cyclic error-correcting code is assigned its own mark, which repeats continuously over a period of time corresponding to the transmission of one codeword. Therefore, such labels define the boundaries of the words of the cyclic error-correcting code and words formed at the junction of two adjacent words of the cyclic error-correcting code. A block of words of a cyclic error-correcting code and blocks of words shifted by multiples of a bit are assigned their synchronized numbering sequence counters and their coincidence counters. Each set of words with the same label, their numbering sequences, has its own list of hit counters and synchronized counters. Comparison of numbering sequences is carried out only within the list with one label corresponding to the boundaries of the word whose number is being analyzed at the moment. Moreover, the comparison of numbering sequences within each list is carried out in parallel in hardware only for the synchronized counters involved, and when two numbering sequences coincide, the value of the corresponding hit counter increases per unit. If the number written in the corresponding hit counter exceeds or is equal to the threshold value at the end of this numbering sequence, a decision is made on the code frame synchronization of the input sequence. Moreover, the threshold value of the number of codewords in the synchronization sequence is equal to the minimum set of codewords required for decoding a block. Synchronization is carried out on code words with the number of errors in them not more than the correcting ability of the code words obtained after removing the synchronizing symbols from the input sequence. If there are no hit counters, the values of which are equal to zero, the values of the hit counters in case of further mismatch of the numbering sequence are not changed and new numbers are not written to the previously used synchronized counters.

This method has a high probability of correct synchronization for channels with an average probability of error per bit no more than 10 "1, but a large number of synchronized counters are required, which complicates its circuit design. In addition, this method has circuit solutions for performing operations where different numbers mismatched numbering sequences of the input sequence are written to the synchronized counters sequentially, which reduces the information transfer rate.

The purpose of the invention is to provide a simpler circuit implementation of the method and a higher information transfer rate compared to the prototype with a high probability of correct synchronization.

To achieve the goal, a method is proposed for code frame synchronization for a concatenated code when using hard decisions, which consists in the fact that the received input sequence consisting of several consecutive words, each of which is a bitwise sum modulo two of an error-correcting cyclic code, numbering sequence and the phasing sequence are first multiplied by the error-correcting cyclic code check polynomial.

As a result of multiplication, the sum of the syndromes of the error-correcting cyclic code, the numbering sequence and the phasing sequence is obtained, then the resulting sum is multiplied by the check polynomial of the numbering sequence and the sum of the syndromes of the error-correcting cyclic code and the phasing sequence is obtained. From this sum, the phasing sequence syndrome is subtracted and a noise-correcting cyclic code syndrome is obtained, which may correspond to one numbering sequence or several numbering sequences. Each bit in a contiguous sequence equal to the number of bits in the codeword of the cyclic error-correcting code is assigned its own mark, which repeats continuously over a period of time corresponding to the transmission of one codeword. Therefore, such labels define the boundaries of the words of the cyclic error-correcting code and words formed at the junction of two adjacent words of the cyclic error-correcting code.

A block of words of a cyclic error-correcting code and blocks of words shifted by multiples of a bit are assigned their synchronized numbering sequence counters and their coincidence counters. If the number recorded in the corresponding hit counter exceeds or is equal to the threshold value, at the end of this numbering sequence, a decision is made on the code frame synchronization of the input sequence. Moreover, the threshold value of the number of code words in the synchronizing sequence is equal to the minimum set of code words required for decoding a block, and synchronization is carried out over code words with the number of errors in them not exceeding the correcting ability of the code words obtained after removing the synchronizing signals from the input sequence.

What is new is that for each word of the blocks, synchronized counters in parallel form a complete set of numbering sequences. The values of these synchronized counters are simultaneously incremented by one in parallel over a period of time corresponding to the transmission of one codeword. When the synchronized counters reach their maximum value, the next value of the counters corresponds to the initial value, and the cycle time of the synchronized counter is equal to the length of the numbering sequence.Each synchronized counter of one specific numbering sequence has its own set of hit counters for all different labels. The values of each synchronized counter from the full set of numbering sequences for the list of one label are hardware-matched in parallel with the numbers of the numbering sequences for the corresponding word of the input sequence that is being analyzed at the moment. When the word number of the input sequence matches the value of the synchronized counter, the value of their hit counter is increased by one. If the number recorded in the corresponding counter of coincidences exceeds or is equal to the threshold value, at the end of this numbering sequence, a decision is made on the code frame synchronization of the input sequence, while all the counters of hits are reset to their initial state. If at the end of the synchronization sequence in its hit counter corresponding to certain words of the input sequence, the value of this hit counter has not reached the threshold value, then this hit counter is reset to its original state.

The proposed method of code frame synchronization for a concatenated code when using hard decisions works as follows.

c_2i

c_3n, представляющую собой поразрядную сумму по модулю два трех последовательностей: последовательности внутренних двоичных кодов каскадного кода с₁, нумерующей двоичной последовательности c_2i=c₂₁c₂₂c₂₃…c_2n и фазирующей последовательности c_3n=с₃с₃с₃…с₃, нарушающей циклические свойства исходного кода и состоящей из повторяющихся циклических последовательностей, где n - число слов кода БЧХ, c_2i - нумерующая последовательность для i-го слова БЧХ.On the transmitting side, a sequence with ₁

c _2i

c _3n , which is a bitwise sum modulo two of three sequences: a sequence of internal binary codes of a concatenated code c ₁ , a numbering binary sequence c _2i = c ₂₁ c ₂₂ c ₂₃ ... c _2n and a phasing sequence c _3n = c ₃ c ₃ c ₃ ... c ₃ , violating the cyclic properties of the source code and consisting of repeating cyclic sequences, where n is the number of BCH code words, c _2i is the numbering sequence for the i-th BCH word.

To obtain a sequence with ₁ on the transmitting side, the initial information with a volume of k m-ary (m> 1) symbols is encoded with an m-ary error-correcting code, for example, an m-ary Reed-Solomon (PC) error-correcting code. The PC code is the outer code or the first stage code of the error-correcting concatenated code.

As a result of such coding of the initial information, a block of words of the PC (N, k) code is obtained, the information length of which is k equal to the word PC, and the block length is equal to N symbols.

Further, the block of information, consisting of words PC, is encoded with a binary code, for example, a binary BCH code with a check polynomial h ₁ (x). The BCH code is an internal code or a second-stage code of an error-correcting concatenated code. The BCH code word has the following parameters: n ₁ is the block length of the code, k ₁ is the information length of the code. As a result of encoding a block of words PC with the BCH code, a block of N binary words of the BCH code (n ₁ , k ₁ ) is obtained, which is a sequence C ₁ .

Further, the words of the BCH code are summed modulo two with the numbering sequence c _2i . As the numbering sequence, a binary code with block length n ₁ and information length k _{2 is} selected, for example, a first-order Reed-Muller (RM) code (maximum period sequence) with a check polynomial h ₂ (x). The information length k ₂ of the PM code corresponds to the binary notation of the BCH word numbers. A one-to-one correspondence is established between the numbers of the BCH words in the concatenated code and the information part of the numbering sequence. The first BCH word is summed modulo two with the sequence obtained as a result of encoding the binary record of the first BCH word number with the PM code, the second BCH word is summed modulo two with the sequence obtained by encoding the binary record of the second BCH word number with the PM code, and so on. This summation operation is performed with all words of the BCH code. If the check polynomials h ₁ (x) and h ₂ (x) of the summed BCH and PM codes are coprime and are divisors of the binomial x ⁿ¹ +1, the summation will result in N words of the cyclic BCH code with length n ₁ and information length k ₁ + k ₂ . This code will correct errors, the number of which is

e≤r / log ₂ (n ₁ +1),

where r = n ₁ -k ₁ -k ₂ is the number of code check symbols.

The third sequence c ₃ , with which the BCH words are added, will be a constant sequence of length n ₁ bits for all words. Such a sequence can be any sequence that is not a BCH code word, for example, a sequence 10000 ... 000.

In real channels, interference is possible, which can be considered as a sequence with ₄ , the presence of ones in which corresponds to the placement of errors in words. For error-free words, the sequence with ₄ contains only zeros.

Let us consider the operation of the method of code frame synchronization for a concatenated code when using hard decisions on the example of a two-stage concatenated code [RS (32,16,17), BCH (31,16,7)]. In the encoder, the original block of information 256 bits is divided into two blocks of 16 × 8 bits, each of which is encoded with a PC code. The PC encoder usually performs encoding by multiplying the information vector by the generator matrix of the code. The operation is performed in the Galois field GF (2 ⁸ ) in accordance with the generating polynomial

P (x) = x ⁸ + x ⁶ + x ³ + x ² +1

As a result of encoding a 16x8 block with a PC code, thirty-two eight-bit PC words are obtained. Further, words from two blocks are grouped by two and receive thirty-two sixteen-bit words, which are encoded with a BCH code.

BCH coding is carried out in accordance with the check polynomial h ₁ (x) = x ¹⁶ + x ¹² + x ¹¹ + x ¹⁰ + x ⁹ + x ⁴ + l

The polynomial is used as a check polynomial for a numbering sequence

h ₂ (x) = x ⁵ + x ² +1

c_2i

c_3n

с₄, сформированной из четырех последовательностей, поступает на информационный вход устройства кодовой цикловой синхронизации. Обычно эта последовательность проходит через коррекционное устройство (КУ). КУ предназначено для синхронизации битов информации с частотой приема и восстановления формы этих битов при возможных искажениях. Вариант КУ, его структурная схема и описание функционирования приведены в источнике [В.И. Шляпобергский. Основы техники передачи дискретных сообщений. М.: «Связь», 1973, с. 275, рис. 5.15]. Далее последовательность записывают в накопитель информации. Одновременно эта последовательность проходит через два фильтра Хаффмена. В накопителе информации последовательность записывают в одно из двух оперативных запоминающих устройств (ОЗУ), пока не будет определен конец блока слов БЧХ, что должно соответствовать правильному определению кодовой цикловой синхронизации. После этого схема управления накопителя начнет запись последующей информации в другое ОЗУ, а из предыдущего ОЗУ начнет считывание информации для дальнейших операций ее обработки и декодирования. Использование накопителя информации, содержащего два ОЗУ, позволяет применить конвейерный способ обработки информации, обеспечив одновременную запись и считывание информации из накопителя информации, что повышает быстродействие способа кодовой цикловой синхронизации.Information in the form of a sequence with ₁

c _2i

c _3n

c ₄ , formed from four sequences, is fed to the information input of the code frame synchronization device. Typically, this sequence goes through a correction device (CU). KU is intended for synchronization of information bits with the frequency of reception and restoration of the shape of these bits in case of possible distortion. The CU version, its structural diagram and a description of its functioning are given in the source [V.I. Shlyapobergsky. Fundamentals of discrete message transmission techniques. M .: "Communication", 1973, p. 275, fig. 5.15]. Next, the sequence is written into an information storage device. Simultaneously, this sequence passes through two Huffman filters. In the storage device, the sequence is written into one of two random access memory (RAM) until the end of the BCH word block is determined, which should correspond to the correct definition of the code frame synchronization. After that, the drive control circuit will start writing subsequent information to another RAM, and from the previous RAM it will start reading information for further processing and decoding operations. The use of an information storage device containing two RAMs makes it possible to apply a pipeline method of information processing, providing simultaneous recording and reading of information from an information storage device, which increases the speed of the method of code cycle synchronization.

In Huffman filters, the sequence is multiplied by the check polynomials of the BCH and PM codes h ₁ (x) and h ₂ (x). Thus, in the first Huffman filter, the syndrome of the BCH code word of the sequence with _{1 is} calculated, and in the second Huffman filter, the syndrome of the PM code of the sequence c _2i .

For an error-free word, the code syndrome is equal to zero, and the combination b ₀ corresponding to the sequence c ₃ transformed in Huffman filters will be written in the syndrome register.

с₄ и однозначно определяющая комбинацию ошибок. Жесткое декодирование принятой последовательности позволяет исправлять не более (d-1)/2 ошибок, где d - минимальное кодовое расстояние слов кода БЧХ.For words with errors, the correction of which is possible within the correcting ability of the code, the syndrome register will contain a combination from a set {b _i } corresponding to the sequence with ₃

with ₄ and uniquely defining the combination of errors. Hard decoding of the received sequence makes it possible to correct no more than (d-1) / 2 errors, where d is the minimum code distance of the BCH code words.

The block of decoders, when a combination of bo or a combination from the set {b _i } is detected in the syndrome register, outputs to the input of the block of adders modulo two corresponding combinations for error correction.

At this moment, the register of the second Huffman filter contains a binary combination of numbers that uniquely corresponds to the sequence c _2i , since the sequence with ₁ is removed by the first Huffman filter, and the sequence with ₃ is constant.

This binary combination of numbers from the register output is fed to the other input of the modulo two adders block. In the block of adders modulo two, the digits of the considered combination of numbers are corrected so that its output is a binary combination corresponding to the assumed true word number of the BCH code. Syndrome combinations that are recognized by the decoder block are obtained by calculating the syndrome for each of the possible error combinations. An example of constructing a block of decoders is presented in the source [Clark J., Jr., Kane J. Coding with error correction in digital communication systems: Per. from English - M .: Radio and communication, 1987, p. 96 - 101].

+

= 465+4495=4960 варианта. Причем 527 синдромам тройных ошибок соответствует по пять вариантов кодовых слов и 465 синдромам двойных и тройных ошибок соответствует один вариант кодового слова для двойной ошибки и по четыре варианта кодового слова для тройных ошибок. Следовательно, трансформированные слова, соответствующие 1860 вариантам кодовых слов с тройными ошибками, могут при синхронизации давать ложный номер как кодовое слово с двойной ошибкой. Откорректированные номера слова кода БЧХ с выхода блока сумматоров по модулю два параллельно поступают на вход схемы сравнения номеров.As a result of summing the words of the BCH code (31,16,7) with the numbering sequence, the words of the BCH code (31,21,5) are obtained. For words of the BCH code (31,21,5), syndromes are calculated for unambiguous correction of their numbers up to one error in a word. For the BCH code (31,21,5), the syndrome corresponds to ten bits. Therefore, only double and triple errors in a word correspond to

+

= 465 + 4495 = 4960 options. Moreover, 527 syndromes of triple errors correspond to five variants of code words and 465 syndromes of double and triple errors correspond to one variant of a code word for a double error and four variants of a code word for triple errors. Consequently, transformed words corresponding to 1860 triple error codeword variants may, when synchronized, give a false number as a double error codeword. The corrected numbers of the BCH code word from the output of the block of adders modulo two are fed in parallel to the input of the number comparison circuit.

The number comparison scheme contains thirty-one lists for thirty-two synchronized counters of the complete set of numbering sequences and 31 × 32 = 992 hit counters. In the proposed method, all synchronization options for numbering sequences and words of the input sequence are taken into account. Each list contains thirty-two common synchronized counters and thirty-two coincidence counters corresponding to them, with the possibility of writing to each of them the maximum number equal to N, where N is the number of BCH code words in a block. This number of counters in each list excludes false erasures of BCH code words during code synchronization. To decode a block of a concatenated code, a set of BCH code words is required at least M, where M is the minimum number of BCH code words sufficient to decode the block. As L increases, where L is the threshold value for the number of words for correct code synchronization, the probability of correct code framing and the probability of false framing decreases. To receive the block of concatenated code, it is necessary to perform correct code frame synchronization and perform decoding of the block of the concatenated code. Therefore, for the threshold value of correct code synchronization during synchronization over codewords with the maximum possible number of errors corrected by hard decisions, the optimal solution will be L equal to M. For a two-stage concatenated code [RS (32,16,17), BCH (31,16, 7)] the L and M values are sixteen.

From the KU, synchronizing pulses are fed to the distributor for the BCH word length based on the Johnson counter. An example of the implementation of a valve variant based on the Johnson counter is given in the source [V.L. Awl. Popular digital microcircuits. Directory. Moscow. Metallurgy, 1988, p. 240, fig. 2.40]. The interval between pulses at each of the outputs of the distributor based on the Johnson counter corresponds to the boundaries of the BCH words or words formed at the junction of two BCH words, and the pulse itself serves as a label. Comparison of numbers of numbering sequences is carried out only within the list of one label corresponding to the boundaries of words whose numbers are being analyzed at the moment. Moreover, the comparison of the numbers of the input sequence and the values of the synchronized counters of the complete set of numbering sequences within each list is carried out in parallel using the hardware method. The operation of finding equal values of the synchronized counters to the corrected numbers of the numbering sequences is carried out and the values of their coincidence counters are increased by one. A variant of the full set of numbering sequences for one label can be represented as follows: the first synchronized counter has a value of 00000, the value of the second synchronized counter is one more than the value of the first synchronized counter, that is, 00001, the value of the third synchronized counter is one greater than the value of the second synchronized counter, that is 00010 and so on. Therefore, the value of the thirty-second synchronized counter for this mark will be 11111. After a time corresponding to the transmission of one codeword, the values of the synchronized counters are increased by one in parallel, and this mark serves as a clock. After a time corresponding to the duration of the transmission of thirty-one codewords, the values of these synchronizing counters will be:

11111, 11110, 11101, 11100, ..., 00010, 00001, 00000.

One synchronized counter can be used for a complete set of numbering sequences, and the values for the remaining thirty-one synchronized counter can be summed up. For example, the value of the second synchronized counter is obtained by summing one (00001) to the value of the first synchronized counter, the value of the third synchronized counter is obtained by summing two (00010) to the value of the first synchronized counter, and so on. The value of the thirty-second synchronized counter is obtained by summing thirty-one (11111) to the value of the first synchronized counter.

For a codeword with two or three errors in the input sequence, each of the five variants of the numbers of the numbering sequence within the list for this word is compared in parallel with the values of the synchronized counters of the complete set of numbering sequences and, if there are comparisons, then the values for all the corresponding hit counters in one clock cycle are increased by unit.

When the synchronized counter counts to the last codeword number in the block and the number written in its coincidence counter is equal to or exceeds the threshold value, then a decision is made on the correct code frame synchronization of the input sequence. In this case, all values of the coincidence counters of the comparison circuit are reset to their original state. When any synchronized counter counts down to the last codeword number in the block and the number written in its corresponding hit counter is less than the threshold, only that hit counter is reset. The rest of the hit counters continue to function.

The proposed method of code frame synchronization for a concatenated code when using hard solutions in comparison with the prototype has a simpler circuit design. In the proposed method for a complete set of numbering sequences requires only thirty-two counters. The prototype uses 32 × 31 = 992 synchronized counters for the numbering sequences. In the proposed method, in contrast to the prototype, there are no operations for determining the mismatched numbers of the numbering sequence for the input sequence with the numbers of the involved synchronized counters in the list and sequentially launching new, still unused synchronized counters corresponding to these mismatched numbers and writing the unit into their coincidence counters. Accordingly, circuitry solutions are not required for these operations. Therefore, the algorithm for processing the numbering sequences for each list in the proposed method is performed in parallel only in hardware, providing high performance for transmitting information in channels with a high level of interference.

The achieved technical result of the proposed method of code frame synchronization for a concatenated code when using hard solutions is a simple circuit implementation and an increase in the information transfer rate in channels with a high level of interference.

Claims (1)

The method of code frame synchronization for a concatenated code when applying hard decisions, which consists in the fact that the received input sequence, consisting of several consecutive words, each of which is a bitwise sum modulo two of an error-correcting cyclic code, a numbering sequence and a phasing sequence, first multiply by the check polynomial of the error-correcting cyclic code and, as a result of multiplication, obtain the sum of the syndromes of the error-correcting cyclic code, the numbering sequence and the phasing sequence, then the resulting sum is multiplied by the check polynomial of the numbering sequence and obtain the sum of the syndromes of the error-correcting cyclic code and the phasing sequence, from this sum the syndrome of the phasing sequence is subtracted and the syndrome of the error-correcting cyclic code is obtained, which can correspond to one numbering sequence or several numbering sequences sequences, each bit in a continuous sequence equal to the number of bits in the codeword of the cyclic error-correcting code is assigned its own label, which repeats constantly after a time interval corresponding to the transmission of one codeword, therefore, such labels determine the boundaries of the words of the cyclic error-correcting code and words formed at the junction of two adjacent words of a cyclic error-correcting code, a block of words of a cyclic error-correcting code and blocks of words formed at the junction of two adjacent words of a cyclic error-correcting code are assigned their synchronized counters of the numbering sequences and their coincidence counters, in case of exceeding or equal to the number written in the corresponding coincidence counter , the threshold value, at the end of this numbering sequence, a decision is made on the code frame synchronization of the input sequence, and the threshold value of the number of code words in the synchronization sequence is equal to the minimum the set of codewords required for decoding a block, and synchronization is carried out according to codewords with the number of errors in them not exceeding the correcting ability of codewords obtained after removing synchronizing symbols from the input sequence, characterized in that for each word of blocks corresponding to its label, synchronized counters in parallel form a complete set of numbering sequences, the values of these synchronized counters are increased in parallel by one after a time interval corresponding to the transmission of one code word, when the synchronized counters reach their maximum value, the next value of the counters corresponds to their initial value and the cycle time of the synchronized counter is equal to the duration of the numbering sequence , for each synchronized counter of one specific numbering sequence there is a set of hit counters for all different labels, the values of each are synchronized th counter from the complete set of numbering sequences for each label is hardware-matched in parallel with the numbers of the numbering sequences for the corresponding word of the input sequence, which is analyzed at the moment, when the word number of the input sequence coincides with the value of the synchronized counter of the numbering sequence, the value of their coincidence counter is increased by one, if the number written in the corresponding counter of hits exceeds or is equal to the threshold value at the end of this numbering sequence, a decision is made on the code frame synchronization of the input sequence, and all hit counters are reset to their initial state, if at the end of the synchronizing sequence in its counter of hits corresponding to label of certain words of the input sequence, the value has not reached the threshold value, then only this hit counter is reset to its original state ...