RU2613844C1 - Device for measuring characteristics of random processes - Google Patents

Abstract

FIELD: measuring equipment.

SUBSTANCE: first target sequence averager (16), the fourth detector (17), the second target sequence averager (18), a subtractor (19) and the fourth divider (20), the output of which is the fifth device output, are further introduced into the device for measuring the characteristics of random processes.

EFFECT: improved accuracy of determining the m parameter of the random process with the Nakagami distribution.

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Description

The invention relates to the field of radio measurements, in particular to devices for measuring the characteristics of random processes.

A device is known for determining the parameter m of a random process with a Nakagami distribution (SU 481907, G06G 7/00, 1975), comprising a non-linear block with a logarithmic characteristic connected via a dispersion determination block to a non-linear indicator device calibrated in units of the Riemann zeta function. The output of a random process source having a Nakagami density distribution is connected to the input of a nonlinear block with a logarithmic amplitude characteristic, the output of which is connected to the input of the dispersion determination block of the random process, the output of which is connected to the input of the indicator device.

A disadvantage of the known device is the relatively low accuracy of determining the parameter m of a random process with a Nakagami distribution due to visual determination based on the information displayed on the indicator device.

A device for determining the characteristics of random processes (SU 1273947 A1, 4 G06F 15/36, 1986), comprising an averager, a first element And, a comparison unit, a first divider, a first adder, a quadrator, a one-shot, the second element And, scale blocks, a logarithm, root extracting units, a second adder, a second divider, the input of the device is connected to the input of the quadrator and one-shot, the output of which is connected to the counting input of the counter, the output of which is connected to the first inputs of the first and second elements AND, the output of the quadrator is connected to the input of the first scale unit and to the input of the averager, the output of which is connected to the second input of the second element And, the output of which is connected to the input of the divisible first divider, the input of the divider of the first divider is connected to the output of the first root extraction unit, the input of which is combined with the first input of the comparison unit and connected to the output of the first element And, the second input of which is connected to the output of the first scale block, the output of the first divider is connected to the input of the logarithm, the output of which is connected to the inputs of the second and third scale blocks, the output of the second scale unit is connected to the input of the first adder, the output of which is connected to the input of the second root extraction unit, the output of which is connected to the input of the second adder, the output of which is connected to the input of the divisible second divider, the input of the divider of the second divider is connected to the output of the third scale unit, the output of the second the divider is the output of the first distribution parameter Nakagami device, the second input of the comparison unit is connected to the input zero of the device, the outputs of the comparison unit and the first divider respectively, the outputs "Stop" and the second parameter of the Nakagami distribution of the device.

A disadvantage of the known device is the relatively low accuracy of determining the parameter m of a random process with a Nakagami distribution. The low accuracy is due to the fact that the maximum likelihood method is implemented in the device for determining the parameter m of a random process with a Nakagami distribution.

The closest in technical essence and the functions performed to the claimed device is a device for measuring the characteristics of random processes (RF Patent No. 2336562, IPC 7 G06G 7/52, 05/19/2006).

The prototype device contains a first decoder, an indicator, a normalizing amplifier, the input of which is connected to the input bus, and the output through a series-connected double quadratic detector and the first integrator is connected to the first input of the first divider, while the output of the normalizing amplifier through a series-connected first detector, second integrator and the second detector is also connected to the second input of the first divider, while the output of the normalizing amplifier is connected in series with the first multiplier, the third integrat rum and a second divider, the output of which is connected simultaneously to the first inputs of the first and second comparators, the second inputs of which are connected respectively to the input buses, with the first input of the second multiplier directly and the second input through the first square root extraction unit connected to the output of the second integrator, output the second multiplier is connected to the second input of the second divider, with the first input of the first multiplier directly, and the second through the third detector connected to the output of the normalizing amplifier, when the output of the third divider is connected to the first input of the first key, the second input of which is connected to the second input of the second key, while the outputs of the first, second, third, fourth, fifth, sixth and seventh AND-NOT elements are respectively connected to the first, second, third, the fourth, fifth, sixth and seventh inputs of the indicator, the eighth, ninth, tenth and eleventh inputs of which are connected respectively to the first, second, third and fourth outputs of the switch, the fifth input of which is connected to the input bus, and the first, second , the third and fourth inputs are connected respectively to the first, second, third and fourth outputs of the second decoder, the first input of which is simultaneously connected to the input bus and the combined ninth inputs of the first and second multiplexers, while the second input of the second decoder is simultaneously connected to the input bus and the combined tenths the inputs of the first and second multiplexers, and the combined ninth and combined tenth inputs of the first and second registers are connected respectively to the input buses, the first, second, heels and the sixth inputs of the first multiplexer are connected respectively to the first, fifth, second and sixth outputs of the first register, the first, second, third, fourth, fifth, fifth, sixth, seventh and eighth inputs of which are connected respectively to the outputs of the fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth comparators, the first inputs of which are combined, while the third, seventh, fourth and eighth outputs of the first register are connected respectively to the first, second, fifth and sixth inputs of the second multiplexer, third the fourth, seventh and eighth inputs of which are connected respectively to the third, seventh, fourth and eighth outputs of the second register, the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of which are connected respectively with the outputs of the third, fourth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth comparators, the first inputs of which are combined, and the first, fifth, second and sixth outputs of the second register are connected respectively to the third, fourth, seventh and eighth the inputs of the first multiplexer, the first and second outputs of which are connected respectively to the first and second inputs of the first decoder, the third and fourth inputs of which are connected respectively with the first and second outputs of the second multiplexer, the second output of the first decoder is simultaneously connected to the first inputs of the first and second elements AND, the second the inputs of which are respectively connected to the fifth and eighth outputs of the first decoder, the tenth output of which is connected to the second input of the fourth element AND NOT, the first input of which at the same time connected to the first inputs of the third and second AND-NOT elements and the twelfth output of the first decoder, the eleventh output of which is simultaneously connected to the combined second input of the seventh AND-NOT element, the third input of the third AND-NOT element and the second input of the second AND-NOT element, wherein the first output of the first decoder is connected to the fourth input of the seventh NAND element, the third input of which is simultaneously connected to the third input of the first NAND element and the fifteenth output of the first decoder, the fourteenth output which is connected to the combined second inputs of the fourth AND element and the third AND element, the fourth input of which is simultaneously connected to the second input of the sixth AND element and the third output of the first decoder, the thirteenth output of which is simultaneously connected to the first inputs of the fourth element AND and the first element AND -NOT, the combined second and fourth inputs of which are simultaneously connected to the output of the first element And and the first input of the third element And, the output of which is simultaneously connected to the fourth input of the fourth the NAND element and the first input of the fifth NAND element, the second input of which is simultaneously connected to the first input of the sixth NAND element and the fourth output of the first decoder, the sixth output of which is simultaneously connected to the combined fourth inputs of the fifth and second NAND elements, the seventh output of the first decoder is connected to the third input of the second AND-NOT element, and the ninth output is connected to the third input of the fifth AND-NOT element, the output of the second AND element is simultaneously connected to the second input of the third AND element, the first input of the fourth AND-NOT element and to the combined fourth and third inputs of the sixth AND-NOT element, and the output of the fourth AND element is connected to the third input of the fourth AND-NOT element, while the input of the second square root extraction unit is connected to the output of the first divider, and the output is connected to the first input of the third divider, the second input of which is connected to the input bus, the first inputs of the first and second amplitude selectors are simultaneously connected to the output of the normalizing amplifier, and the second inputs are connected respectively to the first and second outputs and a step voltage generator, the input of which is connected to the input bus, while the outputs of the first and second amplitude selectors are connected respectively to the first and second inputs of the first subtractor, the output of which is connected to the input of the fourth integrator, the output of which is simultaneously connected to the input of the logarithmic amplifier and the second input the third multiplier, the first input of which is connected to the output of the logarithmic amplifier, and the output is connected to the input of the fifth integrator, the output of which is connected to the input of the unit for calculating the exponential function, the output of which is connected to the first input of the fourth divider, the second input of which is connected to the input bus, and the output is connected to the first input of the fifth divider, the second input of which is connected to the output of the first square root extraction unit, third, fourth, fifth, sixth , seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, twentieth, twenty first, twenty second, twenty third, two twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh, twenty-eighth, twenty-ninth, thirty, thirty-first, thirty-second, thirty-third and thirty-fourth switches, the second and third inputs of which are connected respectively to the input buses, and the combined first inputs are connected to the first input of the thirty-fifth switch, the second inputs of the first and second keys, the twenty-eighth indicator input and the output of the OR element, the first and second inputs of which are connected respectively to the outputs of the first and second comparators, the combined first inputs of which are connected to the first input of the second key and the second input of the thirty-fifth switch, the third input of which is connected to the output of the fifth divider, and the output is connected to the combined first inputs of the twenty-seventh, twenty-eighth, twenty-ninth, thirty, thirty-first, thirty the second, thirty-third and thirty-fourth comparators, the second inputs of which are connected respectively to the outputs of the twenty-seventh, twenty-eighth, twenty-ninth, thirty, thirty-first, the thirty-second, thirty-third and thirty-fourth switches, while the second inputs of the third, fourth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth comparators are connected respectively to the outputs of the third, fourth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth switches and the combined first inputs are connected by the third input of the thirty-fifth switch, while the second inputs of the fifth, sixth, seventh, eighth, ninth, tenth , eleventh, twelfth, nineteenth, twentieth, twenty first, twenty second, twenty third, twenty fourth, twenty fifth and twenty sixth comparators are connected respectively to the outputs of the fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, nineteenth, twentieth , twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-fifth and twenty-sixth switches, and the combined first inputs are connected to the output of the third divider, while the outputs to the eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth AND elements are NOT connected respectively to the sixteenth, seventeenth, eighteenth, nineteenth, twentieth, twenty first and twenty second inputs of the indicator, the twelfth, thirteenth, fourteenth and fifteenth inputs of which are connected respectively the first, second, third and fourth outputs of the second switch, the fifth input of which is connected to the fifth input of the first switch, and the first, second, third and fourth inputs are connected to respectively, with the first, second, third and fourth outputs of the third decoder, the first input of which is simultaneously connected to the combined ninth inputs of the first, second, third and fourth multiplexers, while the second input of the third decoder is simultaneously connected to the combined tenth inputs of the first, second, third and fourth multiplexers, and the combined ninth and combined tenth inputs of the third and fourth registers are connected respectively to the combined ninth and combined tenth inputs the first and second registers, the first, second, fifth and sixth inputs of the third multiplexer are connected respectively to the first, fifth, second and sixth outputs of the third register, the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of which are connected respectively with the outputs nineteenth, twentieth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-fifth and twenty-sixth comparators, while the third, seventh, fourth and eighth outputs of the third register are connected respectively but to the first, second, fifth and sixth inputs of the fourth multiplexer, the third, fourth, seventh and eighth inputs of which are connected respectively to the third, seventh, fourth and eighth outputs of the fourth register, the first, second, third, fourth, fifth, sixth, seventh and the eighth inputs of which are connected respectively with the outputs of the twenty-seventh, twenty-eighth, twenty-ninth, thirty, thirty first, thirty second, thirty third and thirty fourth comparators, and the first, fifth, second and sixth outputs are four of that register are connected respectively to the third, fourth, seventh and eighth inputs of the third multiplexer, the first and second outputs of which are connected respectively to the first and second inputs of the fourth decoder, the third and fourth inputs of which are connected respectively with the first and second outputs of the fourth multiplexer, the second output of the fourth decoder simultaneously connected to the first inputs of the fifth and sixth elements And, the second inputs of which are respectively connected to the fifth and eighth outputs of the fourth decrypto RA, the tenth output of which is connected to the second input of the eleventh AND-NOT element, the first input of which is simultaneously connected to the first inputs of the tenth and ninth AND-elements and the twelfth output of the fourth decoder, the eleventh output of which is simultaneously connected to the combined second input of the fourteenth AND-NOT element , the third input of the tenth AND-NOT element and the second input of the ninth AND-NOT element, while the first output of the fourth decoder is connected to the fourth input of the fourteenth AND-NOT element, the third input of which is simultaneously connected to the third input of the eighth AND-NOT element and the fifteenth output of the fourth decoder, the fourteenth output of which is connected to the combined second inputs of the eighth AND element and the tenth AND-element, the fourth input of which is simultaneously connected to the second input of the thirteenth AND-NOT element and the third output the fourth decoder, the thirteenth output of which is simultaneously connected to the first inputs of the eighth AND element and the eighth AND-NOT element, the combined second and fourth inputs of which are simultaneously connected to the course of the fifth AND element and the first input of the seventh AND element, the output of which is simultaneously connected to the fourth input of the eleventh AND element and the first input of the twelfth AND element, the second input of which is simultaneously connected to the first input of the thirteenth AND element and the fourth output of the fourth decoder the sixth output of which is simultaneously connected to the combined fourth inputs of the twelfth and ninth AND-NOT elements, while the seventh output of the fourth decoder is connected to the third input of the ninth AND-NOT element, and nine the fifth output is connected to the third input of the twelfth AND-NOT element, the output of the sixth AND element is simultaneously connected to the second input of the seventh AND element, the first input of the fourteenth AND element and the combined fourth and third inputs of the thirteenth AND element, and the output of the eighth AND element is connected to the third input of the eleventh AND-NOT element, while the output of the second key is connected to the combined first inputs of the fourth and fifth multipliers, the second inputs of which are connected respectively to the input buses, and the outputs are connected respectively To the input of the second exponential function calculation unit and the first input of the second subtractor, the second input of which is connected to the input bus, and the output is connected to the twenty-fifth input of the indicator, the twenty-third and twenty-fourth inputs of which are connected respectively to the outputs of the sixth and seventh multipliers, the second inputs which are connected respectively to the input buses, and the first inputs are connected respectively to the outputs of the second unit for calculating the exponential function and the sixth divider, the first input to The second input is connected to the input bus, and the second input is connected to the output of the second exponential function calculation unit, while the twenty-sixth and twenty-seventh indicator inputs are connected respectively to the outputs of the adder and the fourth subtractor, the first input of which is connected to the input bus, and the second input is connected to the output of the ninth multiplier, the second input of which is connected to the input bus, and the first input is connected to the combined output of the first key, the input of the fourth detector and the first input of the eighth multiplier, second whose first input is connected to the input bus, and the output is connected to the second input of the third subtractor, the first input of which is connected to the input bus, and the output is connected to the first input of the adder, the second input of which is connected to the output of the tenth multiplier, the first input of which is connected to the input bus , and the second input is connected to the output of the fourth detector.

The disadvantage of the prototype device is the relatively low accuracy of determining the parameter m of a random process with a Nakagami distribution. The relatively low accuracy is due to the fact that the expression for determining the parameter m of a random process with a Nakagami distribution implemented in the prototype device is not true for all values of the asymmetry coefficient of the random distribution law [1].

The purpose of the proposed technical solution is to develop a device for determining the parameters of random processes, providing increased accuracy in determining the parameter m of a random process with a Nakagami distribution.

The goal is achieved by using a random process with the Nakagami distribution of the method of amplitude moments to determine the parameter m.

The invention is illustrated in figure 1, which presents a structural electrical diagram of the device.

The specified technical result is achieved by the fact that in the known device for measuring the characteristics of random processes, containing a normalizing amplifier (1), the input of which is the "input of the investigated sequence" of the device, and the output is connected to the inputs of a double quadratic detector (2), the first detector (7) , the third detector (12) and to the first input of the second multiplier (13). The output of the double quadratic detector (2) is connected to the input of the first integrator (3), the output of which is connected to the first input of the first divider (4), the second input of which is connected to the output of the second detector (9). The output of the first divider (4) is connected to the input of the first square root extraction unit (5), the output of which is connected to the first input of the second divider (6), the second input of which is the "control input" of the device. The output of the first detector (7) is connected to the input of the second integrator (8), the output of which is connected to the inputs of the second detector (9), the second square root extraction unit (11) and to the first input of the first multiplier (10). The output of the third detector (12) is connected to the second input of the second multiplier (13), the output of which is connected to the input of the third integrator (14), the output of which is connected to the first input of the third divider (15), the second input of which is connected to the output of the first multiplier (10) , the second input of which is connected to the output of the second square root extraction unit (11). In addition, the first averager of the studied sequence (16), the fourth detector (17), the second averager of the studied sequence (18), the subtracting device (19) and the fourth divider (20), the output of which is the fifth output of the device, are introduced. The input of the first averager of the test sequence (16) is connected to the output of the first detector (7), and the output is connected to the input of the fourth detector (17). The input of the second averager of the test sequence (18) is connected to the output of the double quadratic detector (2), and the output is connected to the first input of the subtractor (19), the second input of which is connected to the input of the fourth divider (20) and the output of the fourth detector (17). the output of the subtractor (19) is connected to the second input of the fourth divider (20), and the outputs of the second divider (6), the second integrator (8), the second square root extraction unit (11) and the third divider (15) are respectively the first, second, third and fourth outputs of the device.

Thanks to this new set of essential features in the device, the initial moments of the second and fourth order are determined, which indicates the possibility of achieving a technical result.

The claimed device, the structural diagram of which is shown in the figure, consists of a normalizing amplifier 1, a double quadratic detector 2, a first integrator 3, a first divider 4, a first square root extraction unit 5, a second divider 6, a first detector 7, a second integrator 8, and a second detector 9 , the first multiplier 10, the second square root block 11, the third detector 12, the second multiplier 13, the third integrator 14, the third divider 15, the first averager of the sequence 16, the fourth detector and 17, the second averager of the test sequence 18, the subtracting device 19, the fourth divider 20.

The normalizing amplifier 1 is designed to amplify and limit the test sequence. The normalizing amplifier 1 is known and described in [2].

Double quadratic detector 2 is designed to generate a signal proportional to the fourth degree of the investigated sequence. A double quadratic detector 2 is known and described in SU patent No. 744655, G06J 3/00, 06/30/1980

The first and third detectors 7, 12 are designed to generate signals proportional to the square of the investigated sequence. The first and third detectors 7, 12 are known and are described in patent SU No. 460548, G06G 7/20, 02.15.1975.

The first integrator 3 is designed to generate signals proportional to the central moment of a fourth-order random variable. The first integrator 3 is known and described in patent SU No. 1195362, G06G 7 / 186,30.11.1983

The first divider 4 is designed to generate a signal proportional to the kurtosis. The first divider 4 is known and described in patent SU No. 1064279, G06F 7/52, 12/30/1983

The first square root extraction unit 5 is for generating a signal proportional to the square root of excess. The first square root extraction unit 5 is known and described in SU patent No. 1005083, G06G 7/20, 03/19/1983

The second divider 6 is designed to generate a signal proportional to the counterexcess. The second divider 6 is known and described in patent SU No. 1064279, G06F 7/52, 12/30/1983

The second integrator 8 is designed to generate a signal proportional to the variance of a random variable. The second integrator 8 is known and described in patent SU No. 1195362, G06G 7/186, 11/30/1983

The second detector 9 is designed to generate a signal proportional to the square of the variance of a random variable. The second detector 9 is known and described in patent SU No. 460548, G06G 7/20, 02.15.1975.

The first multiplier 10 is designed to generate a signal proportional to the cube of the mean square deviation of a random variable. The first multiplier 10 is known and described in patent SU No. 918953, G06G 7/16, 04/07/1982

The second square root extraction unit 11 is designed to generate a signal proportional to the mean square deviation of the random variable. The second square root extraction unit 11 is known and described in SU patent No. 1005083, G06G 7/20, 03/19/1983

The second multiplier 13 is designed to generate a signal proportional to the cube of the sequence being studied. The second multiplier 13 is known and described in patent SU No. 918953, G06G 7/16, 04/07/1982

The third integrator 14 is designed to generate a signal proportional to the central moment of a random variable of the third order. The third integrator 14 is known and described in patent SU No. 1195362, G06G 7 / 186,30.11.1983

The third divider 15 is designed to generate a signal proportional to the coefficient of asymmetry. The third divider 15 is known and described in patent SU No. 1064279, G06F 7/52, 12/30/1983

The first averager of the studied sequence 16 is designed to generate a signal proportional to the initial moment of a random variable of the second order. The first averager of the studied sequence 16 is known and described in patent SU 1322313 A1, 4 G06F 15/36 07/07/1987, Bull. Number 25.

The fourth detector 17 is designed to generate a signal proportional to the square of the initial moment of a random variable of the second order. The fourth detector 17 is known and described in patent SU No. 460548, G06G 7/20, 02.15.1975.

The second averager of the test sequence 18 is designed to generate a signal proportional to the initial moment of a fourth-order random variable. The first averager of the test sequence 18 is known and described in patent SU 1322313 A1, 4 G06F 15/36 07/07/1987, Bull. Number 25.

The subtractor 19 is designed to generate a signal proportional to the difference between the initial moment of a random variable of fourth order and the square of the initial moment of a random variable of second order. The subtractor 19 can be performed according to the scheme proposed in patent SU 1070568 A, G06G 7/14 01/30/1984, Bull. Number 4.

The fourth divider 20 is designed to generate a signal proportional to the parameter m of the random process with the distribution of Nakagami. The fourth divider 20 is known and described in patent SU No. 1064279, G06F 7 / 52,30.12.1983

The inventive device for measuring random processes operates as follows.

At the "input of the test sequence" of the device, which is the input of the normalizing amplifier 1, the random random sequence X is studied, which characterizes the random process, where it is amplified, limited, and from the output goes to the inputs of the double quadratic detector 2, the first detector 7, the third detector 12, and the first input of the second multiplier 13. The output of the dual detector 2 quadratic signal describing the studied sequence of the fourth power X ⁴ is input to the first integrator 3 and the second yc ednitelya target sequence 18. At the output of the first integrator 3, a signal is generated proportional to the central point of the random variable fourfold

,

,

where ω (x) is the probability density of the process under study. A signal proportional to the central moment of a fourth-order random variable is fed to the first input of the first divider 4. From the output of the first detector 7, a signal describing the sequence to be studied in the second power X ² is fed to the inputs of the second integrator 8 and the first averager of the studied sequence 16. At the output of the second integrators 8 a signal is generated proportional to the variance of a random variable

,

,

which is fed to the input of the second detector 9, the first input of the first multiplier 10, the input of the second square root extraction unit 11 and to the second output of the device. At the output of the second detector 9, a signal is generated proportional to the square of the dispersion of the random variable, and fed to the second input of the first divider 4, at the output of which a signal proportional to the excess

,

,

which goes to the input of the first square root extraction unit 5. From the output of the square root extraction unit 5, a signal proportional to the kurtosis is fed to the first input of the second divider 6. A signal proportional to the second input of the second divider 6 is received unit. At the output of the second divider 6, a signal is generated proportional to the counterexcess,

,

,

which goes to the first output of the device. From the output of the second square root extraction unit 11, a signal proportional to the mean square deviation of a random variable

,

,

enters the second input of the first multiplier 10 and the third output of the device. From the output of the first multiplier 10, a signal proportional to the cube of the mean square deviation of a random variable is fed to the second input of the third divider 15. From the output of the third detector 12, a signal describing the sequence to be studied in the second power X ² is fed to the second input of the second multiplier 13, from the output of which a signal describing the studied sequence in the third power X ³ is fed to the input of the third integrator 14, the output of which forms a signal proportional to the central moment of random variables s third order

,

,

which is fed to the first input of the third divider 15. At the output of the third divider 15, a signal is generated proportional to the asymmetry coefficient,

,

,

which is fed to the fourth output of the device. At the output of the first averager of the studied sequence 16, a signal is generated proportional to the initial moment of a random variable of the second order, which is fed to the input of the fourth detector 17. From the output of the fourth detector 17, a signal proportional to the square of the initial moment of a random variable of second order is fed to the second input of the subtractor 19 and to the first input of the fourth divider 20. At the output of the second averager of the studied sequence 18, a signal is generated proportional to the initial moment s a fourth-order radial quantity that is fed to the first input of the subtractor 19. A signal is generated at the output of the subtractor 19, which is proportional to the difference between the initial moment of the fourth-order random variable and the square of the initial moment of the second-order random variable, which is fed to the second input of the fourth divider 20, at the output which forms a signal proportional to the parameter m of a random process with a Nakagami distribution,

,

,

where X _i is the i-th member of the studied sequence, N is the volume of the studied sequence. A signal proportional to the parameter m of the random process with the distribution of Nakagami arrives at the fifth output of the device.

The proposed device allows to increase the accuracy of determining the parameter m of a random process with a Nakagami distribution due to the implementation of the method of amplitude moments. As an indicator describing the accuracy of determining the parameter m of a random process with a Nakagami distribution, the true relative error of the estimated parameter m [3] is used, which is calculated in accordance with the expression

,

,

- истинное значение параметра m случайного процесса с распределением Накагами, N - количество измерений, m_i - оценочное значение параметра m случайного процесса с распределением Накагами, i=[1, 2, 3, …, N].Where

is the true value of the parameter m of the random process with the Nakagami distribution, N is the number of measurements, m _i is the estimated value of the parameter m of the random process with the Nakagami distribution, i = [1, 2, 3, ..., N].

The values of the true relative error were obtained by analyzing samples from the values of parameter m of a random process with a Nakagami distribution (sample size N = 50, true value of parameter m = 1.5) using the MathCAD 15 computing environment.

Information sources

1. I.I. Sytko. Characterization of random processes distributed by the Nakagami law // Components and Technologies. - 2014. - No. 1. - S. 172-173.

2. A.G. Aleksenko. E.A. Colombet. G.I. Starodub. The use of precision analog microcircuits. - M .: Radio and communication. 1985

3. Handbook of mathematics for engineers and students of technical colleges. Bronstein I.N., Semendyaev K.A. - M: Science. The main edition of the physical and mathematical literature. 1981

Claims (1)

A device for measuring the characteristics of random processes, containing a normalizing amplifier, the input of which is the "input of the sequence under investigation" of the device, and the output is connected to the inputs of the double quadratic detector, the first detector, the third detector and the first input of the second multiplier, the output of the double quadratic detector is connected to the input of the first an integrator whose output is connected to the first input of the first divider, the second input of which is connected to the output of the second detector, the output of the first divider is connected to the first square root extraction unit, the output of which is connected to the first input of the second divider, the second input of which is the "control input" of the device, the output of the first detector is connected to the input of the second integrator, the output of which is connected to the inputs of the second detector, the second square root extraction unit and the first input of the first multiplier, the output of the third detector is connected to the second input of the second multiplier, the output of which is connected to the input of the third integrator, the output of which is connected to the first input of the a third divider, the second input of which is connected to the output of the first multiplier, the second input of which is connected to the output of the second square root extraction unit, characterized in that the first averager of the test sequence, the fourth detector, the second averager of the test sequence, the subtractor, and the fourth divider are added which is the fifth output of the device, the input of the first averager of the test sequence is connected to the output of the first detector, and the output is connected to ode of the fourth detector, the input of the second averager of the test sequence is connected to the output of the double quadratic detector, and the output is connected to the first input of the subtractor, the second input of which is connected to the input of the fourth divider and the output of the fourth detector, the output of the subtractor is connected to the second input of the fourth divider, and the outputs the second divider, the second integrator, the second square root extractor and the third divider are respectively the first, second, third and fourth device outputs.

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