RU2485668C1 - Octave microconsuming high-frequency cmos generator controlled by voltage - Google Patents

Abstract

FIELD: radio engineering, communications.

SUBSTANCE: octave microconsuming high-frequency voltage-controlled generator comprises four P-channel transistors, four N - channel transistors. Links between transistors provide for a self-excitation mode, and non-linearity of feedback depending on control voltages provides for expansion of generated frequencies range to one octave.

EFFECT: maintenance of a permanent output signal amplitude, close to symmetrical one, increased noise immunity.

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Description

The present invention relates to integrated electronic equipment and can be used as part of complex functional blocks (SF blocks) of high-frequency synthesizers of the frequency network (MSC) of the clock synchronization CMOS VLSI.

The modern VLSI design methodology involves the wide use of the library of previously developed and verified SF blocks. VLSI chip manufacturing technology implies technological and structural compatibility of the SF blocks included in it. It is necessary to solve the following problems:

- Minimizing the area occupied by SF blocks on a VLSI chip.

- Minimization of power consumption and the level of interference in power circuits.

- Improving the noise immunity of the SF blocks.

As SF blocks of the VLSI clock frequency synchronization system, the most widely used are solutions based on the use of a voltage-controlled oscillator (VCO), the frequency and phase of the output signal of which is stabilized using a pulse phase-locked loop. A high-frequency VCO is a source of interference in the power supply circuits for neighboring SF units, and is also subject to the influence of interference disrupting its operation. In addition, in many VLSIs, dynamic clock adjustment modes are used to reduce power consumption according to the requests of the executable application. At the same time, the adjustment range of the VCO of the SF block of the SSH should be at least one octave.

When implementing the VF SF unit, the following conditions must be met:

- Production of VCOs using the same technology as the VLSI core.

- The VCO should have low power consumption, and the supply voltage should be equal to the supply voltage of the VLSI core.

- The amplitude of the VCO oscillation signal should be close to the value of the supply voltage in the entire frequency range. The durations of the rising and falling edges of the oscillation signal should be approximately equal.

As a VCO for the SF blocks of the MSS clock synchronization of VLSI, the most widely used are the integrated ring VCOs. A typical block diagram of the ring CMOS VCO is presented in figure 1. The generator includes a unit 11 for generating control voltages Pent and Ncnt, set by the voltage Vent, and a generating ring 12. A typical generating ring consists of series-connected inverters with adjustable voltage Pent and Ncnt for the duration of the propagation of the switching signal. Due to the general negative feedback in the generating ring, a forced oscillation occurs, the frequency of which is determined by the number of inverters in the ring and the total delay of their switching. The output signal OUT from the generating ring is fed to elements designed to increase the steepness of the front and the fall and the load capacity of the VCO output.

To expand the frequency range of a typical generating ring, a corresponding change in the duration of the edge and decay of the oscillation signal over a wide range is required. In this case, more gentle front and decay of the oscillations will be more sensitive to interference along the power supply circuits and on the VLSI chip substrate. As a result, the switching moments of the elements of the generating ring will move from their ideal location in time, thereby increasing the value of the phase noise in the generated signal.

The closest technical solution to the claimed invention is a circuit inverter ring CMOS VCO described in the patent of the Russian Federation No. 2397603 (C1) "Wide-range ring generator controlled by voltage", IPC Н03В 5/08, Н03В 29/00 [1]. This scheme is selected as a prototype of the claimed invention and is shown in figure 2.

A common feature of the invention [1] with the claimed invention is that in addition to changing the duration of the front and the decay of the oscillation signal, at the same time, the values of the input switching voltage of the circuit are changed. The result of such a combined interaction of durations and switching levels is the extension of the operating frequency range of the generating ring, and with smaller changes in the control current and the duration of the edge and decay of the oscillation signal.

However, as shown in the invention [1], to create a generating ring having a frequency range of two octaves, it is necessary to use the series connection of three such circuits. In this case, the total number of transistors is 18, which, despite the two-octave frequency range, is a drawback of this circuit.

A generating ring implemented using one scheme of the invention [1] is presented in article [2]: “Development of circuitry of a high-frequency CMOS controlled oscillator for a microcircuit of the class“ System on a chip ”” / A. Zaitsev // Information technology in electrical engineering and electric power industry: materials of the 7th All-Russian. scientific and technical conf. Cheboksary: Publishing house of the Chuvash University, 2010. - S.178-182. The generating ring of article [2] is shown in FIG. 3 and is formed by sequentially switching on the circuit 21 of the invention [1] and a buffer element 31 with an adjustable switching signal propagation duration. With a range of generated frequencies equal to one octave, the total number of transistors is 12, which is a drawback of this circuit.

The technical result of the claimed invention is the creation of a micro-consuming high-frequency VCO, consisting of eight transistors manufactured in a standard digital CMOS manufacturing process, which determines its compactness and structural compatibility with other CMOS VLSI units. The generator provides a frequency range of one octave, in which it maintains a constant, close to symmetrical, signal amplitude equal to the supply voltage, which increases its noise immunity. Moreover, the generator has a small constant value and small ripples of the current consumption and does not interfere with other VLSI blocks.

The specified result is achieved due to the fact that in the scheme of the invention [1] with current-controlled levels and durations of the front and the fall of the switching signal, comprising: first, second, third, fourth and fifth conclusions; first, second and third P-channel transistors; first, second and third N-channel transistors; the first terminal of the first P-channel transistor and the first terminal of the first N-channel transistor are interconnected; the second terminal of the first, the third terminal of the second and second terminal of the third P-channel transistors are interconnected; the second terminal of the first, the third terminal of the second and second terminal of the third N-channel transistors are interconnected; the first terminal of the second P-channel transistor is connected to the first terminal of the device; the first terminal of the second N-channel transistor is connected to the second terminal of the device; the second terminal of the second P-channel transistor and the third terminal of the third N-channel transistor are connected to the third terminal of the device; the second terminal of the second N-channel transistor and the third terminal of the third P-channel transistor are connected to the fourth terminal of the device; the third terminal of the first and first terminal of the third P-channel transistor, the third terminal of the first and first terminal of the third N-channel transistor connected to the fifth terminal of the device, it is proposed to introduce a fourth P-channel transistor and a fourth N-channel transistor; to connect the first output of the fourth and the first output of the second P-channel transistors; to connect the second terminal of the fourth and second terminal of the first P-channel transistors; to connect the third terminal of the fourth and the first terminal of the first P-channel transistors; connect the first terminal of the fourth and the first terminal of the second N-channel transistor; to connect the second output of the fourth and second output of the first N-channel transistors; connect the third output of the fourth and the first output of the first N-channel transistors.

In the claimed invention, as well as in the invention [1], with a decrease in the control voltage at the first and second terminals of the device and a corresponding decrease in the value of the switching current, there is not only an increase in the front and fall of the oscillation signal, but also at the same time the voltage potentials of the switching circuit diverge, leading to an increase in the propagation delay of the oscillation signal. And vice versa, with an increase in the control voltage and a corresponding increase in the value of the switching current, not only the edge and decay of the oscillation signal become sharper, but also the potentials of the switching voltage of the circuit approach closer, which leads to a decrease in the propagation delay of the oscillation signal.

An innovation in the CMOS VCO circuit of the claimed invention is that the introduced fourth P-channel transistor and the fourth N-channel transistor create an internal non-linear negative feedback, depending on the magnitude of the control voltages on the first and second terminals of the device. Through this connection, the first terminals of the first P- and N-channel transistors connected together are alternately connected to the output potentials of the controlled current sources formed by the second P- and N-channel transistors. Depending on the state of the output of the generator, the connection occurs either through the fourth P- or fourth N-channel transistors, causing self-excitation of the VCO. The non-linearity of the feedback provides an extension of the range of generated frequencies to one octave, while the amplitude of the oscillation signal at the generator output approaches the value of the supply voltage.

The invention is illustrated by the following drawings:

Figure 1. Typical block diagram of the ring CMOS VCO.

Figure 2. The circuit of the inverter ring CMOS VCO presented in the invention [1] and selected as a prototype of the claimed invention.

Figure 3. The scheme of the generating ring presented in the article [2].

Figure 4. The CMOS VCO diagram of the invention.

Figure 5. The signal diagrams of the inventive CMOS VCO scheme when generating an output signal with a frequency of 0.5 GHz.

6. The signal diagrams of the inventive CMOS VCO scheme when generating an output signal with a frequency of 1.0 GHz.

The inventive CMOS VCO scheme is shown in FIG. 4. The generator has: the first (Pent) and second (Ncnt) terminals for connecting control signals, the third (VDD) and fourth (GND) terminals for connecting voltage and power supply, and the fifth (OUT) terminal of the output signal. The composition of the generator includes: the first (P1), second (P2), third (P3) and fourth (P4) P-channel transistors and the first (N1), second (N2), third (N3) and fourth (N4) N- channel transistors. The first terminal of transistor P1, the third terminal of transistor P4, the first terminal of transistor N1 and the third terminal of transistor N4 are interconnected. The second terminal of transistor P1, the third terminal of transistor P2, the second terminal of transistor PZ and the second terminal of transistor P4 are interconnected. The second terminal of transistor N1, the third terminal of transistor N2, the second terminal of transistor N3 and the second terminal of transistor N4 are interconnected. The first terminal of transistor P2 and the first terminal of transistor P4 are connected to the first terminal Pent of the device. The first terminal of transistor N2 and the first terminal of transistor N4 are connected to the second terminal Ncnt of the device. The second terminal of the transistor P2 and the third terminal of the transistor N3 are connected to the third terminal of the VDD device. The second terminal of the transistor N2 and the third terminal of the transistor P3 are connected to the fourth terminal of the GND device. The third terminal of transistor P1, the first terminal of transistor RZ, the third terminal of transistor N1 and the first terminal of transistor N3 are connected to the fifth terminal OUT of the device.

The claimed invention works as follows. Let the supply voltage be applied to the VDD pin relative to the GND pin, and the corresponding control voltages to the Pent and Ncnt pins. Let the voltage potential at the OUT terminal of the device be in a low voltage state at which the channels of transistors P1 and N3 are closed, and the channels of transistors P3 and N1 are open. Then, through the transistors Р2 and РЗ from the VDD pin to the GND pin, a current flows, limited by the control voltage at the Pent pin. In this case, the voltage level at terminal 3 of transistor P2 depends on the magnitude of the current flowing through it and the resistance value of the open channel of transistor P3. The lower the value of the flowing current, the higher the voltage drop between the terminals 2 and 3 of the transistor P2 and, accordingly, the lower the voltage potential between the terminals 1 and 2 of the transistor P4, as a result of which the transistor P4 goes into a closed state. At the same time, through the open channel of transistor N2, the voltage potential at its terminal 3 tends to the output level GND, increasing the voltage potential between terminals 1 and 2 of transistor N4. As a result, the channel of transistor N4 opens and the voltage potential at the first terminals of transistors P1 and N1 tends to the GND level. Moreover, the magnitude of the current recharging the parasitic capacitance of this node depends on the value of the control voltage Ncnt. When the voltage potential at the first terminals of transistors P1 and N1 reaches the corresponding voltage level between the second terminals of transistors P1 and N1, the channel of transistor P1 opens, and the channel of transistor N1 closes and the OUT terminal of the device switches to a high-level voltage state. In this case, the switching current depends on the value of the control voltage Pent.

The presence of a high level voltage potential at the OUT terminal closes the channel of the transistor RE and opens the channel of the transistor N3. Through the transistors N3 and N2 from the VDD terminal to the GND terminal, current flows limited by the voltage of the control signal at the Ncnt terminal. In this case, the voltage level at terminal 3 of transistor N2 depends on the current flowing through it and the resistance value of the open channel of transistor N3. The lower the value of the flowing current, the higher the voltage drop between the terminals 2 and 3 of the transistor N2 and, accordingly, the lower the voltage potential between the terminals 1 and 2 of the transistor N4, as a result of which the transistor N4 goes into a closed state. At the same time, through the open channel of transistor P2, the voltage potential at its terminal 3 tends to the output level VDD, increasing the voltage potential between terminals 1 and 2 of transistor P4. As a result, the channel of transistor P4 opens and the voltage potential at the first terminals of transistors P1 and N1 approaches the level of VDD. Moreover, the magnitude of the current recharging the stray capacitance of this node depends on the value of the control voltage Pent. When the voltage potential at the first terminals of transistors P1 and N1 reaches the corresponding voltage level between the second terminals of transistors P1 and N1, the channel of transistor P1 closes, and the channel of transistor N1 opens and the output OUT of the device switches to a low voltage state. In this case, the switching current depends on the value of the control voltage Ncnt.

Thus, in the inventive CMOS VCO circuit, self-excitation occurs with a frequency depending on the magnitude of the switching currents of the circuit, controlled by the voltage potentials at the Pent and Ncnt pins. When a low-frequency signal is generated with a decrease in the switching current, not only the edge and decay of the oscillation signal are obstructed, but also the voltage potential levels diverge at the first terminals of transistors P1 and N1, which are required for switching the third terminals of transistors P1 and N1 in the direction of VDD and in the direction GND This leads to an increase in the switching delay of the signal, and hence to a decrease in the oscillation frequency. When a high-frequency signal is generated with an increase in the switching current, not only the edge and decay of the oscillation signal become sharper, but also the required voltage potential levels come closer to switch the transistors P1 and N1, which leads to a decrease in the signal switching delay, and therefore to an increase in the oscillation frequency . The result of the interaction of these factors is the expansion of the range of generated frequencies, in which the amplitude of the generated signal is kept constant and close to the value of the supply voltage.

To protect the VCO of the VHF SF-block from interference on power circuits, on the substrate and by means of electromagnetic waves, guard rings and electrostatic shielding are used in its design. Electrostatic shielding is carried out by metallization layers having contacts with the substrate along the entire perimeter of the SF block. Additional screens located above the P-channel transistors are connected to the potential of VDD, and located above the N-channel transistors are connected to the potential of GND.

In Fig.5 and Fig.6. The signal diagrams of the claimed VCO scheme implemented by the CMOS 180 nm process are presented. The diagrams in FIG. 5 correspond to an output signal frequency of 0.5 GHz. 6, the output frequency is 1.0 GHz. Current diagrams are shown in the upper part of the drawings, and voltage diagrams in the lower part of the drawings.

The legend on the diagrams corresponds to:

IVDD - current consumed by the circuit along the line of the supply voltage VDD;

IP2 - current flowing through the transistor P2;

IN2 - current flowing through the transistor N2;

IP4 - current flowing through the transistor P4;

IN4 - current flowing through the transistor N4;

VPN1 — voltage of nonlinear feedback at the first terminals of transistors P1 and N1;

VP2 - voltage at terminal 3 of transistor P2;

VN2 - voltage at terminal 3 of transistor N2;

VOUT - voltage at the OUT terminal.

In both cases, almost symmetric oscillation signals are observed that occur relative to the level of half the supply voltage with a fill factor of 0.5 ± 5%. At the same time, the amplitude of the VPN1 non-linear feedback signal exceeds half the value of the supply voltage, and the amplitude of the OUT signal is maintained close to the circuit voltage of 1.8 V. When generating a signal with a frequency of 0.5 GHz, the average current consumption is 16 μA (30 μW) , the magnitude of the ripple current is + 7 / -6 μA. When generating a signal with a frequency of 1.0 GHz, the average current consumption is 27 μA (50 μW), the ripple value is + 6 / -7 μA.

The range of generated frequencies in the inventive CMOS VCO circuit can be changed by connecting a capacitor of the corresponding capacity: between the OUT terminal and the VDD or GND terminals; between the first terminals of transistors P1 and N1 and the terminals of VDD or GND; between the first terminals of the transistors P1 and N1 and the terminal OUT; combination of data connections. The required capacitor can be formed by metallization layers, transistor structures, or in another way convenient for integral implementation.

The inventive CMOS VCO circuit consists of eight transistors manufactured in a standard digital CMOS manufacturing process, which determines its compactness and structural compatibility with other CMOS VLSI units. Due to the generated internal nonlinear negative feedback, the generator generates a signal with a frequency range equal to one octave, in which it maintains a constant, close to the symmetrical amplitude of the output oscillation signal, equal to the supply voltage, which increases its noise immunity. Moreover, the generator has a small constant value and small ripple of the current consumption and does not interfere with other VLSI units.

The combination of these qualities makes it possible to use the claimed CMOS VCO scheme when developing micropowerful SF-blocks of MSS clock synchronization intended for use as a part of VLSI of the broadest purpose from ADC to microprocessors.

Claims (1)

An octave micropower consuming high frequency controlled voltage generator, comprising: first, second, third, fourth and fifth pins; first, second and third P-channel transistors; first, second and third N-channel transistors; the first terminal of the first P-channel transistor and the first terminal of the first N-channel transistor are interconnected; the second terminal of the first, the third terminal of the second and second terminal of the third P-channel transistors are interconnected; the second terminal of the first, the third terminal of the second and second terminal of the third N-channel transistors are interconnected; the first terminal of the second P-channel transistor is connected to the first terminal of the device; the first terminal of the second N-channel transistor is connected to the second terminal of the device; the second terminal of the second P-channel transistor and the third terminal of the third N-channel transistor are connected to the third terminal of the device; the second terminal of the second N-channel transistor and the third terminal of the third P-channel transistor are connected to the fourth terminal of the device; the third terminal of the first and first terminal of the third P-channel transistors, the third terminal of the first and first terminal of the third N-channel transistors are connected to the fifth terminal of the device, characterized in that the fourth P-channel transistor and the fourth N-channel transistor are introduced; the first terminal of the fourth and the first terminal of the second P-channel transistors are interconnected; the second terminal of the fourth and second terminal of the first P-channel transistors are interconnected; the third terminal of the fourth and the first terminal of the first P-channel transistors are interconnected; the first terminal of the fourth and the first terminal of the second N-channel transistors are interconnected; the second terminal of the fourth and second terminal of the first N-channel transistors are interconnected; the third terminal of the fourth and the first terminal of the first N-channel transistors are interconnected.

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