RU2460169C1 - Integral test structure to assess reliability and metallisation - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: test structure comprises a metal conductor with two outputs to connect a source of currents and two potential outputs to measure voltage drops as current flows through the conductor. An additional metal conductor is connected at the side to the metal conductor, besides, this conductor has current and potential outputs at the free end and a potential output in area of its connection to the conductor. Metal conductors are tested on this test structure for reliability.

EFFECT: higher information value regarding permissible metallisation current density with account of metal layout features in an integral microcircuit chip.

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Description

This invention relates to the field of microelectronics and can be used to control the reliability of metallization, namely metal wiring, in the production of integrated circuits (ICs).

It is known that as a result of the flow of electric current through a conductor in the metal wiring of the integrated circuit under the influence of an electric current, metal atoms diffuse with the formation of defects near the cathode in the form of voids (absence of atoms) and near the anode in the form of hillocks (atom accumulation).

To assess the reliability of metal wiring in integrated circuits, test structures are used taking into account its specific wiring design.

Known test structure (US 6897476 B1, H01L 23/58, 2004), containing two adjacent linear conductors with current leads to the contact pads for each conductor. Two linear conductors are used for testing the reliability of metallization and assessing the quality of the dielectric between the conductors before and after the tests. The disadvantages of this structure is the low accuracy of the measurements during reliability tests due to the lack of potential conclusions and not taking into account the branching of conductors in the IC.

A known test method and apparatus for testing the reliability of metallization (US 6825671 B1, G01R 31/08, 2004), which includes a test structure containing a large number of linear conductors with different lengths to determine at a given current density the critical length of the conductor below which is not the conductor breaks during testing. The disadvantage of the test structure in the invention is the high complexity during testing and the large area of the test structure.

Closest to the claimed invention is a single conductor of a certain length of 800 μm with potential and current leads at both ends (Harry A. Schafft, 1998). The test results determine the permissible current density flowing through the conductor, at which the conductor's failure-free operation is predicted for 10 years. The resulting current density is used in the further development of microcircuits to ensure the failure-free operation of conductors of any length.

The disadvantage of this test structure is the lack of information for real metal wiring in integrated circuits, since in integrated circuits the wiring is made in the form of branching conductors in the power and earth circuits, where the highest currents flow. In these conductors, the permissible current densities differ from the current density in a single conductor. It is the assessment of the permissible current density in the IC that this test structure provides.

Figure 1 shows the design of the proposed test structure; Fig. 2 is a detailed description of the topology of the test structure; Fig. 3 is a diagram of the connection of devices to the test structure, ensuring reliability tests; in Fig. 4 - electrical diagram of the test structure with measured voltages and currents during testing, in Fig. 5 - the results of tests for the reliability of test structures A, B and C.

The design of the test structure is shown in Fig. 1. Two wide conductors 2a and 3a of width W ₂ ≥3 · W _{1 are} attached to the test conductor 1 with a length L = 800 μm and a width W ₁ at both ends. Conductors 2a and 3a are current through which the supplied current flows. To wide conductors 2a and 3a, conductors 2b and 3b are connected at right angles, which are leads for measuring potentials on conductors 2a and 3a. Further, on the side (from either side) to the conductor 1 at a distance L ₁ from the wide conductor 2a is connected a conductor 4 of width W ₁ and length L ₂ with a wide conductor 4a of width W ₃ at its free end. A potential lead 4b of width W _{1 is} connected to conductor 4a. A potential terminal 4i of width W _{1 is} connected to the side of conductor 1 (opposite to conductor 4). In the general case, the distances L ₁ and L _{2 are} determined from the wiring topology of a real microcircuit; in this example, two test structures were taken: the first - L ₁ = 40 μm and L ₂ = 40 μm (near the cathode), the second - L ₁ = 760 μm and L ₂ = 40 μm (near the anode).

Figure 2 shows a detailed design of the test structure. Shown are the contact pads (KP1, KP2, ..., KP8) and their switching either with current 2a, 3a and 4a or with potential 2b, 3b, 4b and 4i conductors. Next to the test conductors 1 and 4, adjacent conductors 1a and 1b are located to monitor short circuits with the neighboring test conductors (extrusion control). Conductors 1a and 1b are connected to the contact pads KP1 and KP8, respectively. Contact pads provide the connection of external power and measurement devices to the test structure through contact devices.

Figure 3 shows a diagram of the measurement of the test structure during testing. The current generator is connected to the conductor 2a (cathode) and all other current conductors 3a, 4a are connected to zero potentials (ground), and a current meter is connected in series to the current conductor 4a. Voltages V ₂ , V ₃ , V ₄ and V _4i are measured at potential terminals 2b, 3b, 4b and 4i, respectively.

Figure 4 shows the electrical circuit of the test structure with the measured voltages V ₂ , V ₃ , V _4i , V ₄ and current I ₃ . Resistance R ₄ is the resistance of conductor 4 connected to conductor 1 on the side. The measured voltage at the intersection of conductors 1 and 4 is indicated as V _4i . In accordance with Fig. 4, resistances R _1a and R _1b are parts of the resistance of conductor 1. Resistances r ₂ , r ₃ , r ₄ are parasitic resistances, namely the resistances of the cables of the measuring equipment and the lead conductors to the test structure on the chip.

The resistance of the tested parts of the conductor R _1a , R _1b and side conductor R _{4 are} easily calculated based on Ohm's law:

The criterion for the presence of a metallization gap at time t _f , here ('f'-failure), is the maximum of three relative changes Δ _1a , Δ _1b and Δ _{4 of the} resistances R _1a , R _1b and R _4, respectively, when tested more than 20%:

where Δ _1a = (R _1a (t) -R _1a (0)) / R _1a (0) 100%, Δ _1b = (R _1b (t) -R _1b (0)) / R _1b (0) 100%, Δ ₄ = (R ₄ (t) -R ₄ (0)) / R ₄ (0) · 100%. R _1a (0), R _1b (0) and R ₄ (0) are the initial resistances at the beginning of the test, R _1a (t), R _1b (t) and R ₄ (t) are the resistances at time t during the test.

The accelerated tests used here are carried out at elevated direct current and elevated temperature, which provides an acceptable test time of up to several hours per test structure. According to the test results of the array of test structures, statistical processing of the obtained t _{f is} performed based on the log-normal distribution. As a result, the median MTBF t ₅₀ and the variance of the distribution S are determined.

The actual MTBF of t _0.1 under normal operating conditions Jex, Tex and the failure rate of 0.1% of the test structures is calculated by the formula:

where t _{50_hour} is the median failure time at the failure rate of 50% (MTTF), hour;

S is the variance of the distribution of failure times;

E _a is the activation energy, eV;

N is the coefficient in the Blake expression;

Test - test temperature in units of K;

Jack and Tex - current and operating temperature of the integrated circuit;

k is the Boltzmann constant.

The values of the activation energy Ea and the coefficient N are determined by additional tests based on the well-known Blake expression:

where t ₅₀ is the median failure time at the 50% level (MTTF);

E _a is the activation energy;

A, N - Blake distribution coefficients.

Expression (3) is derived from expression (4).

This test structure can be used to assess the reliability of metal wiring from both Al and its compounds, and from Cu.

Example:

Reliability tests (electromigration tests) were carried out on test structures. We tested AlCuSi / TiN metal conductors with a width of W = 0.8 μm and a thickness of 0.4 μm (h) AlSi / 0.03 μm TiN with a passivating SiO ₂ / SiN layer 1.0 μm thick. Samples (test structures with boiled contact pads in a ceramic case) were subjected to accelerated tests: at an increased direct current J = 2 MA / cm ² and an elevated temperature of 385 ° C in the furnace. During the tests, a measuring stand was used based on the Agilent 4156C precision semiconductor parameter analyzer. The set generator current was calculated by the formula J · (h · W).

Figure 5 shows the reliability test data for three types of test structures: structure A is a linear conductor without a side conductor, structure B is a linear conductor with a side conductor L ₁ = 40 μm and L ₂ = 40 μm, structure C is a linear conductor with a side conductor a conductor L ₁ = 760 μm and L ₂ = 40 μm.

Shown are the measured failure times of test structures during accelerated testing (45 data for each type of test structure) and a linear extrapolation of the results by the least squares method was performed. The horizontal axis X shows the failure times of structures on a logarithmic scale (in hours), the vertical axis Y represents the value Z satisfying the equation F ₀ (Z) = p, where F ₀ is the standard normalized normal distribution function and p is the fraction of the number of failures. The extrapolation line has the expression Z = (lnt-ln t ₅₀ )) / S. For practical calculations, MS Excel has a built-in function NORMSINV that calculates the value Z in the equation F ₀ (Z) = p from the value p.

It should be noted that at p = 0.5 (the number of failures is 50%), the function F ₀ (Z = 0) is 0.5. Also, the intersection of the extrapolation line with the horizontal axis X is the median failure time t ₅₀ .

The control of extrusion (short circuit of the tested conductor 1 with adjacent conductors 1a and 1b, Fig. 2) showed that there are no short circuits. The circuit was evaluated at a voltage of 1 V according to the criterion of the measured current <10 nA.

Table 1 summarizes the test results for these three types of test structures. Here, the activation energy E _a = 0.74 eV and the coefficient of the Blake expression N = 1.76; experiments on their determination are given in the appendix. The metallization operation parameters in the IC are Jex = 0.55 MA / cm ² and Tex = 85 ° C.

Table 1 Test Results for Test Structures A, B, and C Type of test structure Structure A (without side conductor) Structure B (side conductor L ₁ = 760 μm and L ₂ = 40 μm) Structure C (side conductor L ₁ = 40 μm and L ₂ = 40 μm) t ₅₀ / S, ln (hour) 0.56 / 0.31 0.58 / 0.30 0.73 / 0.29 t ₀₁ , year.

As a result, the test structure with a side conductor near the cathode (structure C) has been reliable (electromigration resistance) for 18.7 years, which is more than the electromigration resistance of 13.6 years of a single test structure A (without a side conductor).

проводника С (с боковым проводником L₁=40 мкм и L₂=40 мкм) при условии медианы времени наработки на отказ 13,6 года, что присуще тестовой структуре A без бокового проводника с током эксплуатации Jэкс=0.55 МА/см² Based on formula (4), the maximum working current density can be recalculated

conductor C (with a side conductor L ₁ = 40 μm and L ₂ = 40 μm) under the condition of a median MTBF of 13.6 years, which is inherent in test structure A without a side conductor with an operating current of Jex = 0.55 MA / cm ²

As a result, on the basis of this test structure, the information content about the permissible current density is increased, taking into account the peculiarities of the metal wiring in the integrated circuit.

Application:

The activation energy E _a and the coefficient N of the Blake expression were determined on a test structure A (without a side conductor).

The table shows the experimental values of the failure times of test structures for determining the activation energy E _a by constructing a linear approximation of the dependence of the failure time (ln (t ₅₀ )) on temperature (1 / (kT) and calculating E _a as the slope of the linear approximation. Here, the activation energy is equal to 0.74 eV.

table 2 The test results of 5 test structures A to determine the activation energy. Test current density Jtest = 2 MA / cm ² , test temperatures - 300 ° C, 350 ° C, 400 ° C. The calculated value of E _a is equal to 0.74 eV. Test temperature at Jtest = 2 MA / cm ² 300 ° C 350 ° C 400 ° C Nn failure Failure time ln (t), hour one 3.40 2.39 1.23 2 3.55 2.21 1.37 3 3.61 2.42 1.39 four 3.93 2.75 1.40 5 4.21 2.96 1.55 Median (ln (t ₅₀ )) 3.61 2.42 1.39 1 / (kT) 20.25 18.62 17.24

Table 3 shows the experimental values of the failure times of test structures for determining the coefficient N by constructing a linear approximation of the dependence of the failure time (ln (t ₅₀ )) on the current load Ln (J test) and calculating the coefficient 'N' as the slope of the linear approximation. Here, the coefficient N of the Blake expression is 1.76.

Table 3 The test results of 5 test structures A to determine the coefficient N of the Blake expression. Test temperature 350 ° C, test current density Jtest = 1 MA / cm ² , 2 MA / cm ² , 3 MA / cm ² . Current density Jtest at Ttest = 350 ° C 1 MA / cm ² 2 MA / cm ² 3 MA / cm ² Nn failure Failure time ln (t), hour one 2.27 1.63 1.43 2 3.44 2.25 1.67 3 3.62 2.39 1.70 four 4.54 2.58 1.74 5 5.41 3.46 1.83 Median (ln (t ₅₀ )) 3.62 2.39 1.70 Ln (J test) 0.00 0.69 1.10

The temperature coefficient of resistance of the TCS of the metal conductor was also determined, which is equal to 0.00287 ° C ^-1 . The TCS coefficient is calculated based on the linear dependence of the resistance of a metal conductor on R (T) of temperature T in the range of 25 ° C, 50 ° C, 75 ° C, 100 ° C, 150 ° C:

where R ₀ is the resistance of the conductor at room temperature T ₀ = 25 ° C. The supplied current for measuring the resistance was small (20 μA) to prevent thermal self-heating due to the flow of current.

Additionally, self-heating of the test structure was taken into account when a current of 2 MA / cm ² used in the tests and a furnace temperature of 385 ° C flowed. The temperature T of the test structure was monitored by the formula

and amounted to 380 ° C, i.e. the difference with the oven temperature was 5 ° C. With this in mind, the temperature of the furnace was set at 380 ° C.

Literature for an application for an invention:

Standards:

Standard Method for Calculating the Electromigration Model Parameters for Current Density and Temperature, JEDEC Standard JESD63, 1998.

Standard Test Structures for Reliability Assessment of AlCu Metallizations with Barrier Materials, JEDEC Standard JESD87, 2001.

Articles:

F. Giroux, C. Gounelle, P. Mortid and G. Ghibaudo Wafer-level electromigration tests on NIST and SWEAT structures. Proc. IEEE 1995 Int. Conference on Microelectronic Test Structures, Vol8, March, p.229-232, 1995.

Harry A. Schafft. Interconnect reliability test chip NIST 36 for development of measurement tools and standards. Integrated Reliability Workshop Final Report, 1998 IEEE International, p.109.

Patents:

US Pat. No. 5,264,377, class H01L 21/66, Integrated Circuit Electromigration Monitor, 1993.

U.S. Patent 6,825,671, Class G01R 31/08, Integrated Electromigration Length Effect Testing Method and Apparatus, 2004.

US Pat. No. 6,897,476 B1, Class H01L 23/58, Test Structure For Determining Electromigration and Interlayer Dielectric Failure, 2005.

US Patent 7693651 B2, class G01R 31/26, Test Structure For Electromigration Analysis And Related Method, 2010.

US Patent 6822437 B1, Class H01L 23/48, Interconnect Test Structure With Slotted Feeder To Prevent Stress-Induced Voids, 2004.

Patent WO 2004/001432 A1, class G01R 31/316, Electromigration Test Device and Electromigration Test Method, 2004.

Patent WO 2002/067318 A2, class H01L 21/66, Electromigration Test Structure For Determining The Reliability of Wiring, 2002.

US Pat. No. 6,995,392 B2, class H01L 23/58, Test Structure For Locating Electromigration Voids In Dual Damascene Interconnects, 2006.

Claims (1)

An integrated test structure for assessing the reliability of metallization in an integrated circuit, consisting of a metal conductor with two leads for connecting a current source and two potential leads for measuring voltage drops when current flows through a conductor, characterized in that, in order to increase information content, they are connected to the metal conductor on the side there is an additional metal conductor, while this conductor has current and potential terminals at the free end and a potential terminal in the area of its connection .

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