RU2310212C1 - Digital correlator of receiver of satellite radio-navigation system signals - Google Patents

Abstract

FIELD: radio navigation aids, applicable in digital correlators of receivers of satellite radio navigation system (SPNS) signals, in particular, in digital correlators of receivers of the SPNS GLONASS (Russia) and GPS (USA) signals.

SUBSTANCE: the legitimate signal in the digital correlator is detected by the hardware, which makes it possible to relieve the load of the processor and use its released resources for solution of additional problems. The digital correlator has a commutator of the SPNS signals, processor, digital mixers, digital controllable carrier-frequency oscillator, units of digital demodulators, accumulating units, programmed delay line, control register, digital controllable code generator, reference code generator and a signal detector. The signal detector is made in the form of a square-law detector realizing the algorithm of computation of five points of the Fourier sixteen point discrete transformation with additional zeroes in the interval of one period of the, c/a code with a subsequent computation of the modules of the transformation results and their incoherent summation and comparison with a variable threshold, whose value is set up depending on the noise power and the number of the incoherent readout. The signal detector has a controller, multiplexer, complex mixer, coherent summation unit, module computation unit, incoherent summation unit, noise power estimation unit, signal presence estimation unit and a unit for determination of the frequency-time coordinates of the global maximum.

EFFECT: provided acceleration of the search and detection of signals.

2 cl, 6 dwg

Description

The invention relates to the field of radio navigation aids and can be used in digital correlators of signal receivers of satellite radio navigation systems (SRNS), in particular in digital correlators of signal receivers of SRNS GLONASS (Russia) and GPS (USA).

There are well-known SRNS signal receivers operating simultaneously on GLONASS and GPS SRNS signals described in [1] - Riley S., Howard N., Aardoom E., Daly P., Silvestrin P. "A Combined GPS / GLONASS High Precision Receiver for Spase Applications "/ Pros. Jf ION GPS-95, Palm Springs, CA, US, Sept. 12-15, 1995, p.835-844, as well as in the patents: [2] - RU No. 2146378 (C1), G01S 5/14, 03.10.2000; [3] - RU No. 2164431 (C2), G01S 5/14, 01/27/2001; [4] - RU No. 2178894 (C1), G01S 5/14, 01/27/2002; [5] - EP No. 1052786 (A1), G01S 1/00, G01S 5/14, HB04 7/185, 11/15/2000.

The generalized block diagram of these receivers consists of a radio frequency conversion unit, a multi-channel correlation processing unit, and a processor (computer). The radio frequency conversion unit amplifies the received signals to the desired level, filters the signals from interference, converts the carrier frequency of the signals with decreasing frequency, and then converts the signals into digital form. To perform these functions, the RF conversion unit contains analog filters, amplifiers, frequency converters (analog mixers), analog-to-digital converters (samplers), as well as clock and heterodyne signal conditioners. The operations of frequency conversion of signals and their sampling are carried out in the radio frequency conversion unit in separate GLONASS and GPS channels, which is due to differences between the signals of these systems, namely, their location in different, albeit close, frequency ranges, using different pseudorandom modulating codes and using different methods of individualization (separation) of signals. Thus, GPS SRNS satellites emit signals modulated by individual pseudo-random codes on one carrier frequency, and GLONASS SRNS satellites emit signals modulated by the same pseudo-random code on individual carrier (letter) frequencies lying in the adjacent frequency domain. The outputs of these channels form the outputs of the block of the radio frequency Converter. Signals from these outputs, i.e. the converted GLONASS and GPS signals are fed to the corresponding inputs of the multichannel correlation processing unit. The multichannel correlation processing unit, together with the processor, searches for and monitors the SRNS signals, measures the radio navigation parameters — the pseudorange and pseudo-velocities of the object relative to the satellites emitting the SRNS signals, and converts the radio navigation parameters into navigation data. Each of the channels of the multichannel correlation processing unit is a digital correlator connected via a data exchange bus with a processor common to all channels, see [2, FIG. 1, 2, block 2, elements 3 ₁ ÷ 3 _N ], [3, FIG. .1, 2, block 2, elements 3 ₁ ÷ 3 _N ; [4, FIG. 1, block 2, elements 3 ₁ ÷ 3 _N ], [5, FIG. 4, block 3, elements 4 ₁ ÷ 4 _N ]. The implementation of digital correlators used in SRNS signal receivers is the subject of consideration in this application.

The digital correlators used in the SRNS signal receivers [1] - [5] are made according to the standard scheme presented in [2, FIG. 4], [3, FIG. 3], [4, FIG. 3], [5, 6]. A similar scheme of the digital correlator, which differs in details of the implementation of a digital controlled carrier generator, is also considered in [6] - EP No. 1067395 (A1), G01S 1/00, G01S 5/02, Н04В 7/185, 01/10/2001.

The typical circuit of the digital correlator of the SRNS signal receiver includes a SRNS signal switch (GLONASS or GPS), a control register, a digital controlled carrier oscillator, digital mixers of in-phase and quadrature processing channels, series-connected blocks of digital demodulators and storage blocks in-phase and quadrature processing channels, and digitally controlled code generator, reference code generator and programmable delay line are also connected in series; kov, control register, digital controlled carrier generator, digital controlled code generator and reference code generator are connected via a data bus with the processor. The signal inputs of the SRNS signal switch form the signal input of the digital correlator. The clock inputs of the drives of the storage units, the digital controlled code generator, the digital controlled carrier generator and the programmable delay line form the clock input of the digital correlator. The signal inputs of the digital mixers are connected to the output of the SRNS signal switch, the outputs of the digital mixers are connected to the signal inputs of the blocks of digital demodulators, and the reference inputs of the digital mixers are connected to the outputs of the digital controlled carrier generator. The control inputs of the programmable delay line, the reference code generator and the SRNS signal switch are connected to the corresponding outputs of the control register. The reference inputs of the blocks of digital demodulators are connected to the corresponding outputs of the programmable delay line.

The main procedures performed by the digital correlators of SRNS signal receivers, presented in [1] - [6], consist in correlating the signal coming from the output of the SRNS signal switch with a copy of the desired signal and accumulating the correlation results in the storage units of the storage units over a certain time interval. Usually this interval is one millisecond, which corresponds to the length of the code pseudo-random sequence (PSP) of the reference C / A code of the SRNS GPS and GLONASS. The indicated correlation is carried out by multiplying the digital samples of the input signal by the local copy of the desired signal generated inside the digital correlator, i.e. a copy of the signal of the selected SRNS satellite. The loop closure of tracking the delay of the reference code and the frequency of the signal is carried out using the processor. The processor reads the information from the drives, processes it using the appropriate programs, and generates feedback control signals for the digital carrier and code generators, thereby closing the tracking loops.

The tracking procedure is preceded at the initial stage by the signal search and detection procedure. The signal search is carried out according to two parameters - the frequency and symbols of the reference code bandwidth. The combination of all search positions by frequency and symbols of the reference code bandwidth determines the search area. Frequency search positions are changed by discrete changes in the frequency of the output signals of a digital controlled carrier generator. Changing the search positions by the symbols of the reference code bandwidth is carried out by discrete changing the delay of the reference code in a programmable delay line. The signal search procedure consists in sequentially sorting all the time-frequency positions of the search area and comparing the accumulated results of correlation processing with a given detection threshold.

In digital correlators of SRNS signal receivers presented in [1] - [6], this threshold is set based on the given probabilities of skipping and false alarm for the lowest signal level. Based on the results of studies of a specific time-frequency position, a decision is made about the absence or presence of a signal at this position.

A feature of the digital correlators of SRNS signal receivers presented in [1] - [6] is that the procedures for comparing the accumulated results of correlation processing with a given detection threshold and deciding on the presence or absence of a signal are performed by the processor, i.e. exclusively using software tools. This requires certain computing resources, increases the load on the processor and narrows the possibility of its use for solving additional tasks not related to signal detection.

The known digital correlator of the SRNS signal receiver described in [7] is EP No. 1063536 (A1), G01S 5/14, H04B 7/185, 12/27/2000 ("Digital correlator for a receptor of signals from satellite radio-navigation systems") , in which an attempt was made to reduce the load on the processor by using a two-stage signal search procedure, the essence of which is that at the first stage, a strong signal is searched using a signal detector, implemented by hardware, and at the second stage (in the case of a negative result, first stage) standard software search. This digital correlator receiver signals SRNS adopted as a prototype.

The digital correlator of the SRNS signal receiver, adopted as a prototype, contains (see Fig. 1) a SRNS signal switch 1, a processor 2, a first 3 and a second 4 digital mixers, respectively, related to the in-phase and quadrature processing channels, a digital controlled generator 5 carrier, the first 6 and second 7 blocks of digital demodulators related, respectively, to the in-phase and quadrature processing channels, the first 8 and second 9 storage blocks, respectively, to the in-phase and quadrature processing channels, programs adjustable delay line 10, control register 11, digital controlled code generator 12, reference code generator 13 and signal detector 14.

Block 6 of digital demodulators contains a group of two digital demodulators 6 ₁ and 6 ₂ , block 7 of digital demodulators contains a group of two digital demodulators 7 ₁ and 7 ₂ , storage block 8 contains a group of two drives 8 ₁ and 8 ₂ , and storage block 9 contains a group of two drives 9 ₁ and 9 ₂ . The signal inputs of digital demodulators 6 ₁ and 6 ₂ are interconnected and form the signal input of block 6, the outputs of digital demodulators 6 ₁ and 6 ₂ form a group of outputs of block 6, and the reference inputs of digital demodulators 6 ₁ and 6 ₂ form a group of reference inputs of block 6. The signal inputs of digital demodulators 7 ₁ and 7 ₂ are interconnected and form the signal input of block 7, the outputs of digital demodulators 7 ₁ and 7 ₂ form a group of outputs of block 7, and the reference inputs of digital demodulators 7 ₁ and 7 ₂ . form a group of reference inputs of block 7.

The outputs of drives 8 ₁ and 8 ₂ form a group of outputs of block 8, the signal inputs of drives 8 ₁ and 8 ₂ form a group of signal inputs of block 8, and the interconnected clock inputs of drives 8 ₁ and 8 ₂ form a clock input of block 8. Outputs of drives 9 ₁ and 9 ₂ form a group of outputs of block 9, the signal inputs of drives 9 ₁ and 9 ₂ form a group of signal inputs of block 9, and interconnected clock inputs of drives 9 ₁ and 9 ₂ form a clock input of block 9.

The signal inputs of the switch 1 signals SRNS form the signal input of a digital correlator.

The signal inputs of the digital mixers 3 and 4 are connected to the output of the SRNS signal switch 1, and their reference inputs are connected, respectively, to the first and second outputs of the digital controlled carrier generator 5.

The signal inputs of digital demodulators 6 and 7 are connected to the outputs of the respective digital mixers 3 and 4, and the groups of their outputs are connected to the groups of inputs of the corresponding storage units 8 and 9.

The output groups of the storage units 8 and 9 are connected with the first and second groups of signal inputs of the signal detector 14, and also, through the data exchange bus, with the processor 2.

The output of the digital controlled code generator 12 is connected to the signal input of the reference code generator 13, the output of which is connected to the signal input of the programmed delay line 10.

A group of two outputs of the controlled delay line 10 is connected to the groups of reference inputs of blocks 6 and 7 of digital demodulators. In this case, the first output in this group, on which an “exact” (“p”) copy of the reference code is generated, is connected to the reference inputs of digital demodulators 6 ₁ and 7 ₁ , and the second output in this group, on which the “biased” one is formed (" d ") a copy of the reference code associated with the reference inputs of the digital demodulators 6 ₂ and 7 ₂ . The control input of the programmable delay line 10 is connected to the first output of the control register 11, the second output of which is connected to the control inputs of the switch 1 of the SRNS signals and the reference code generator 13.

A digital controlled carrier generator 5, a control register 11, a digital controlled code generator 12, a reference code generator 13 and a signal detector 14 are connected via a data bus with the processor 2.

The clock inputs of the digital controlled generator 5 of the carrier, the storage units 8 and 9, the programmable delay line 10, the digital controlled generator 12 of the code are connected to the clock input of the digital correlator.

The signal detector 14 implements in the prototype the function of a simple modular detector that compares individually the modules of the results of correlation processing in in-phase and quadrature channels with a first threshold and their sums with a second threshold.

In a generalized form, the work of the correlator prototype is as follows. At the inputs of the switch 1 of the SRNS signals, samples of the SRNS GLONASS and GPS signals are generated, formed by analog-to-digital converters of the radio frequency conversion unit of the SRNS signal receiver. In accordance with the command of processor 2, issued to the control register 11, the switch 1 of the SRNS signals connects to its output the signals of one of the SRNS - GLONASS or GPS. The signals of the selected SRNS are fed to the signal inputs of digital mixers 3 and 4, the reference inputs of which receive quadrature signals ("SIN" and "COS") of the reference frequency from the corresponding outputs of the digital controlled generator 5 of the carrier. A digitally controlled carrier generator 5 provides the generation of quadrature signals of the intermediate frequency of the given SRNS GLONASS letter, the binary code of which is issued by the processor 2, or the intermediate frequency of the SRNS GPS signals. Digital mixers 3 and 4 provide the selection of the signals of a given SRNS GLONASS letter or the signals of the SRNS GPS satellites and the transfer of the spectra of these signals to the main frequency band (to zero frequency). From the outputs of digital mixers 3 and 4, the signals are fed to the signal inputs of blocks 6 and 7 of digital demodulators. The reference inputs of blocks 6 and 7 of digital demodulators from the first and second outputs of the programmed delay line 10 receive, respectively, the “exact” (“p”) and “shifted” (“d”) copies of the reference C / A code of the SRNS GLONASS or GPS. Blocks 6 and 7 of digital demodulators using the digital demodulators 6 ₁ , 6 ₂ and 7 ₁ , 7 ₂ that are part of them carry out the correlation of the received signals with the “exact” (“p”) and “offset” (“d”) copies of the reference C / A code SRNS GLONASS or GPS. Programmable delay line 10 operates on the signals from the output of the generator 13 of the reference code, which forms the reference pseudorandom C / A codes of the SRNS GLONASS or GPS satellites. The clock signal of 1.023 MHz for GPS or 0.511 MHz for GLONASS, necessary for the operation of generator 13, is supplied to its signal input from the output of a digital controlled code generator 12. The type of the generated pseudo-random code sequence and the clock frequency of the reference code are selected according to the instructions of the processor 2 received via the data bus to the generators 12 and 13. The correlation results are accumulated in the storage units 8 and 9 in the corresponding drives 8 ₁ , 8 ₂ and 9 ₁ , February _9, namely, the accumulator accumulates August _1-phase component of the correlation replica signal (Ip), ₈ February drive accumulates an in-phase component shifted copies of the signal (Id) correlation accumulator accumulates the quadrature January ₉ to mponentu replica correlation signal (Qp), and drive February ₉ accumulates the shifted quadrature component of the correlation signal copies (Qd). The accumulation period is equal to the period of the reference C / A code, i.e. 1 ms

The data (Ip, Qp, Id, Qd) accumulated in the drives 8 ₁ , 8 ₂ , 9 ₁ , 9 ₂ are periodically read by the processor 2, in which the necessary signal processing algorithms are implemented and the necessary control commands and data are generated to search and track signal.

At the beginning of the search process, the processor 2, based on a priori uncertainty of the temporal position of the desired signal, sets the initial position of the search, i.e. sets the carrier frequency for the digital controlled generator 5 of the carrier, the code frequency for the digital controlled generator 12 of the code and the position of the "exact" ("p") and "shifted" ("d") copies of the reference C / A code of the SRNS GLONASS or GPS using the register 10 control, and also sets the threshold value for the signal detector 14.

The results of correlation processing Ip, Qp, Id, Qd accumulated in the drives 8 ₁ , 8 ₂ , 9 ₁ , 9 ₂ over the interval of 1 ms are fed to the signal inputs of the signal detector 14, which detects a strong signal at the first stage of the search using its hardware . This is done by comparing the modules / Ip /, / Qp /, Ad /, / Qd / and the sums of the modules / Ip / + / Qp / and / Id / + / Qd / with the given thresholds. If, as a result of comparisons, a threshold is exceeded, a decision is made to detect a signal at a given search position. Next, a confirmation procedure is carried out, at the end of which a decision is made to end or continue the search procedure. If after processing all the search positions the signal is not detected, the search process proceeds to the second stage - the signal search stage, implemented by the software of the processor 2 without the participation of the hardware of the signal detector 14.

The signal search in the second stage is carried out at the same positions as in the first stage. The processor 2 provides the starting position of the search, i.e. sets the carrier frequency for the digital controlled generator 5 of the carrier, the code frequency for the digital controlled generator 12 of the code and the position of the "exact" ("p") and "shifted" ("d") copies of the reference C / A code of the SRNS GLONASS or GPS using the register 10 controls. Then, after 1 ms from the beginning of accumulation, the processor 2 reads information from all the drives of the storage units 8 and 9. Then, the transition to the second and subsequent search positions is carried out. After passing through all the search positions, the processor 2 processes the accumulation results using the embedded algorithm and makes a decision on the presence or absence of a signal at these positions.

Thus, the digital prototype correlator implements a two-stage signal search procedure - at the first stage, a strong signal is searched using the hardware of signal detector 14, which implements the function of a simple modular detector, and in the second stage (in the case of a negative result in the first stage), a standard search signal software processor 2.

Under ideal conditions, when working with strong signals, the use of such a digital correlator gives a gain in the SRNS signal receiver compared to the analogs [1] - [6] in terms of reducing the signal detection time and reducing the load on the processor. In real conditions, when working with ordinary (rather weak) signals, the use of such a digital correlator leads to an increase in the time required to search for a signal due to unproductive losses of time spent on the useless first stage in this case, without any decrease in processor load .

The task to which the claimed invention is directed is to create a digital correlator of the SRNS signal receiver, in which the task of detecting a signal, regardless of its level, is performed by hardware, which allows you to really unload the processor and use its freed up resources to solve additional problems.

The invention consists in the following. The digital correlator of the SRNS signal receiver contains a SRNS signal switch, the signal inputs of which form the signal input of the digital correlator, the first and second blocks of digital demodulators, each of which contains a group of digital demodulators, the outputs of which form a group of outputs of the corresponding block of digital demodulators, the reference inputs form a group of reference inputs the corresponding block of the digital demodulator, and the interconnected signal inputs are the signal input of the corresponding block of the digital demodulator first and second digital mixers, the signal inputs of which are connected to the output of the SRNS signal switch, and the outputs are connected to the signal inputs of the corresponding blocks of digital demodulators, the first and second memory blocks, each of which contains a group of drives, the clock inputs of which form the clock input of the corresponding memory unit, the outputs form the group of outputs of the corresponding storage unit, and the signal inputs - the group of signal inputs of the corresponding storage unit, associated with the outputs of the corresponding block of digital demodulators, a signal detector, the first and second groups of signal inputs of which are connected to the groups of outputs, respectively, of the first and second storage units, a digitally controlled carrier generator, the first and second outputs of which are connected to the reference inputs, respectively, of the first and second digital mixers, a programmable delay line, the outputs of which are connected to groups of reference inputs of the first and second blocks of digital demodulators, a reference code generator, the output of which is connected to the signal input of the programmable delay line, a digital controlled code generator, the output of which is connected to the signal input of the reference code generator, a control register, the outputs of which are connected to the control inputs of the programmable delay line, the SRNS signal switch and the reference code generator, as well as a processor connected via data bus with a digital controlled code generator, a reference code generator, a control register, a digital controlled carrier generator, storage units and will detect signal tree. In this case, the clock inputs of the storage units, the programmable delay line, the digital controlled carrier oscillator and the digital controlled code generator are connected to the clock input of the digital correlator. Unlike the prototype, the signal detector is made in the form of a quadrature detector that implements an algorithm for calculating five points of a sixteen-point discrete Fourier transform with additional zeros in the interval of one era of C / A code, followed by calculation of the modules of the conversion results and their incoherent summation and comparison with a variable threshold, value which is set depending on the noise power and incoherent reference number, and contains connected to the processor via the data exchange bus to an ontroller whose clock input is connected to the clock input of the digital correlator, and the command output is connected to the command input of the reference code generator, a multiplexer, the control input of which is connected to the corresponding control output of the controller, and the first and second groups of signal inputs forming the first and second group of signal inputs a signal detector connected to the output groups of the respective storage units, a complex mixer, the first and second signal inputs of which are connected to the corresponding outputs of the multip an exponent, and the reference inputs - with the corresponding reference outputs of the controller, a coherent summing unit, the first and second signal inputs of which are connected to the corresponding outputs of the complex mixer, and the control input - with the corresponding control output of the controller, the module calculation unit, the first and second signal inputs of which are connected with the corresponding outputs of the coherent summation block, and the control input - with the corresponding control output of the controller, the incoherent summation block, signal input for which it is connected to the output of the module calculation unit, and the control input to the corresponding control output of the controller, the noise power estimation unit, the signal input of which is connected to the output of the module calculation unit, the information input is connected to the first output of the incoherent summing unit, the control input is connected to the corresponding control the controller’s output, and the output is connected via a data bus with the processor, a signal availability estimator, the signal input of which is connected to the second output of the incoherent summation I, the output is connected to the signal input of the controller, the control input is connected to the corresponding control output of the controller, and the information inputs are connected via the data bus with the processor, as well as the unit for determining the time-frequency coordinates of the global maximum, the first information input of which is connected to the first output of the incoherent block summation, the second information input is connected to the output of the signal presence assessment unit, the control input is connected to the corresponding control output of the controller, and the output is connected via data exchange bus with the processor.

In an embodiment of practical importance, the groups of drives and digital demodulators in each of the storage units and blocks of digital demodulators consist, respectively, of K drives and K digital demodulators, where K = 16.

The invention and the possibility of its industrial use are illustrated by drawings and explanatory materials presented in figures 1-6, where

figure 1 presents a generalized structural diagram of a digital correlator of a receiver of signals of the SRNS, adopted as a prototype;

figure 2 is a generalized structural diagram of the inventive digital correlator of the receiver of the SRNS signals;

figure 3 is a generalized block diagram of a unit for estimating noise power;

figure 4 is a generalized block diagram of a block for assessing the presence of a signal;

5 is a graphical depiction of a set of coefficients used in the discrete Fourier transform;

6 is a matrix of coefficients used in the discrete Fourier transform.

The inventive digital correlator of the SRNS signal receiver (hereinafter referred to as the digital correlator) contains, see FIG. 2, a SRNS signal switch 1, a processor 2, a first 3 and a second 4 digital mixers related, respectively, to in-phase and quadrature processing channels, a digital controlled generator 5 carrier, the first 6 and second 7 blocks of digital demodulators related, respectively, to the in-phase and quadrature processing channels, the first 8 and second 9 storage blocks, respectively, to the in-phase and quadrature processing channels, p a programmable delay line 10, a control register 11, a digitally controlled code generator 12, a reference code generator 13, and a signal detector 14.

Block 6 of digital demodulators contains a group of K digital demodulators 6 ₁ ÷ 6 _K , block 7 of digital demodulators contains a group of K digital demodulators 7 ₁ ÷ 7 _K , memory block 8 contains a group of K drives 8 ₁ ÷ 8 _K , and memory block 9 contains a group of K drives 9 ₁ ÷ 9 _K , where K = 16.

The signal inputs of digital demodulators 6 ₁ ÷ 6 _K are interconnected and form the signal input of block 6 of digital demodulators, the outputs of digital demodulators 6 ₁ ÷ 6 _K form a group of outputs of block 6 of digital demodulators, and the reference inputs of digital demodulators 6 ₁ ÷ 6 _K form a group of reference inputs of block 6 digital demodulators. The signal inputs of digital demodulators 7 ₁ ÷ 7 _K are interconnected and form the signal input of block 7 of digital demodulators, the outputs of digital demodulators 7 ₁ ÷ 7 _K form a group of outputs of block 7 of digital demodulators, and the reference inputs of digital demodulators 7 ₁ ÷ 7 _K form a group of reference inputs of block 7 of digital demodulators.

The outputs of the drives 8 ₁ ÷ 8 _K form the group of outputs of the storage unit 8, the signal inputs of the drives 8 ₁ ÷ 8 _K form the group of signal inputs of the storage unit 8, and the interconnected clock inputs of the drives 8 ₁ ÷ 8 _K form the clock input of the storage unit 8. Outputs drives 9 ₁ ÷ 9 _K form a group of outputs of the storage unit 9, the signal inputs of drives 9 ₁ ÷ 9 _K form a group of signal inputs of the storage unit 9, and interconnected clock inputs of drives 9 ₁ ÷ 9 _K form the reference input of the storage unit 9.

The signal inputs of the switch 1 signals SRNS form the signal input of a digital correlator.

The signal inputs of the digital mixers 3 and 4 are connected to the output of the SRNS signal switch 1, and their reference inputs are connected, respectively, to the first and second outputs of the digital controlled carrier generator 5.

The signal inputs of the digital demodulators 6 and 7 are connected, respectively, with the outputs of the digital mixers 3 and 4, and the groups of their outputs are connected, respectively, with the groups of inputs of the storage units 8 and 9.

The output groups of the storage units 8 and 9 are connected with the first and second groups of signal inputs of the signal detector 14, and also, through the data exchange bus, with the processor 2.

The output of the digital controlled code generator 12 is connected to the signal input of the reference code generator 13, the output of which is connected to the signal input of the programmed delay line 10.

The outputs of the controlled delay line 10 are associated with groups of reference inputs of blocks 6 and 7 of digital demodulators. The control input of the programmable delay line 10 is connected to the first output of the control register 11, the second output of which is connected to the control inputs of the switch 1 of the SRNS signals and the reference code generator 13.

A digital controlled carrier generator 5, a control register 11, a digital controlled code generator 12, a reference code generator 13 and a signal detector 14 are connected via a data bus with the processor 2.

The clock inputs of the digital controlled generator 5 of the carrier, the storage units 8 and 9, the programmable delay line 10, the digital controlled generator 12 of the code and the signal detector 14 are connected to the clock input of the digital correlator.

The signal detector 14 is made in the form of a quadrature detector that implements an algorithm for calculating five points of a sixteen-point discrete Fourier transform with additional zeros in the interval of one epoch of C / A code, followed by calculation of the modules of the conversion results and their incoherent summation and comparison with a variable threshold, the value of which is set depending from noise power and incoherent readout numbers.

The signal detector 14 comprises a controller 15, a multiplexer 16, an integrated mixer 17, a coherent summing unit 18, a module calculating unit 19, an incoherent summing unit 20, a noise power estimating unit 21, a signal presence estimating unit 22, and a global maximum frequency-time coordinate determination unit 23 .

The controller 15 is connected via a data bus with the processor 2; the clock input of the controller 15, forming the clock input of the signal detector 14, is connected with the clock input of the digital correlator; the command output of the controller 15 is connected to the command input of the reference code generator 13.

The first and second groups of signal inputs of the multiplexer 16, forming the first and second group of signal inputs of the signal detector, are connected to the output groups of the storage units 8 and 9. The control input of the multiplexer 16 is connected with the corresponding control output of the controller 15.

The first and second signal inputs of the complex mixer 17 are connected to the corresponding outputs of the multiplexer 16, and the reference inputs to the corresponding reference outputs of the controller 15.

The first and second signal inputs of the coherent summation unit 18 are connected to the corresponding outputs of the complex mixer 17, and the control input to the corresponding control output of the controller 15.

The first and second signal inputs of the module calculation unit 19 are connected to the corresponding outputs of the coherent summation unit 18, and the control input is connected to the corresponding control output of the controller 15.

The signal input of the incoherent summing unit 20 is connected to the output of the module calculation unit 19, and the control input is connected to the corresponding control output of the controller 15.

The signal input of the noise power estimation unit 21 is connected to the output of the module calculation unit 19, the information input is connected to the first output of the incoherent summing unit 20, the control input is connected to the corresponding control output of the controller 15, and the output is connected via the data bus with the processor 2.

The signal input of the signal availability estimation unit 22 is connected to the second output of the incoherent summing unit 20, the output is connected to the signal input of the controller 15, the control input is connected to the corresponding control output of the controller 15, and the information inputs are connected via the data exchange bus with processor 2.

The first information input of the global-maximum frequency-time coordinates determination unit 23 is connected to the first output of the incoherent summing unit 20, the second information input is connected to the output of the signal presence estimation unit 22, the control input is connected to the corresponding control output of the controller 15, and the output is connected via the data exchange bus with processor 2.

In this example, the noise power estimation block 21 contains (Fig. 3) a register block 24 consisting of registers 24 ₁ ÷ 24 _J (J = 5), the combined signal inputs of which are connected to the output of the adder 25, and the outputs are connected to the corresponding signal inputs of the multiplexer 26, as well as with the corresponding summing inputs of the subtraction unit 27, the subtracting inputs of which are connected to the outputs of the adders 28 ₁ ÷ 28 _J. The inputs of the adders 28 ₁ ÷ 28 _J form the information input of the block 21 estimates the noise power associated with the first output of the block 20 incoherent summation. The first input of the adder 25 forms the signal input of the noise power estimation unit 21 associated with the output of the module calculation unit 19. The second input of the adder 25 is connected to the output of the multiplexer 26. The control inputs of the multiplexer 26 and the registers 24 ₁ ÷ 24 _J form the control input of the noise power estimating unit 21 associated with the corresponding control output of the controller 15. The outputs of the subtracting unit 27 form the output of the noise power estimating unit 21, connected through the data bus with the processor 2.

In the example under consideration, the signal presence estimation unit 22 comprises (Fig. 4) a comparison unit 29, an output register 30, a threshold generation unit 31, a threshold initial value unit 32 and a threshold increment unit 33. The input of the output register 30 is connected to the output of the comparison unit 29. The output of the output register 30 forms the output of the signal availability estimator 22 associated with the signal input of the controller 15 and the second information input of the frequency-time coordinates of the global maximum. The signal input of the comparison unit 29 forms the signal input of the signal availability estimator 22, associated with the second output of the incoherent summing unit 20. The reference input of the comparison unit 29 is connected to the output of the threshold generation unit 31, the first information input of which is connected to the output of the initial threshold value block 32, and the second information input is connected to the output of the threshold increment unit 33. The threshold forming unit 31 consists of registers 34 ₁ ÷ 34 _j (J = 5), the combined signal inputs of which are connected to the output of the adder 35, and the outputs are connected to the corresponding signal inputs of the multiplexer 36, the output of which, forming the output of the threshold forming unit 31, is connected with the first input of the adder 35 and the reference input of the comparison unit 29. The inputs of the installation of the initial value of the registers 34 ₁ ÷ 34 _J form the first information input of the block 31 of the formation of the threshold associated with the output of the block 32 of the initial value of the threshold. The second input of the adder 35 forms a second information input of the threshold forming unit 31 associated with the output of the threshold incrementing unit 33. Block 32 of the initial threshold value consists of registers 37 ₁ ÷ 37 _J , the combined signal inputs of which form the information input of block 32 of the initial threshold value, and the outputs are connected to the corresponding signal inputs of multiplexer 38, the output of which is connected to the first information input of block 31 of the threshold formation. The threshold increment block 33 consists of registers 39 ₁ ÷ 39 _J , the combined signal inputs of which form the information input of the threshold increment block 33, and the outputs are connected to the corresponding signal inputs of the multiplexer 40, the output of which is connected to the second information input of the threshold formation block 31. The information inputs of block 32 of the initial threshold value and block 33 of the increment of the threshold form the information inputs of block 22 for evaluating the presence of a signal connected via a data bus with processor 2. Control inputs of registers 34 ₁ ÷ 34 _J , 37 ₁ ÷ 37 _J , 39 ₁ ÷ 39 _J and multiplexers 36, 38, 40 form the control input of the signal availability estimator 22 associated with the corresponding control output of the controller 15.

The digital correlator has two main modes of operation - the signal search mode and the signal tracking mode. The signal search mode is characterized by two stages, in the first of which the noise power is estimated, and in the second, the signal is actually searched using a variable threshold, the value of which is set depending on the result of the noise power estimation and incoherent reference number (number n of the millisecond C / A era code). The main features of the implementation of both stages of the signal search mode are discussed below in the description of the operation of the noise power estimation blocks 21 and the signal presence assessment 22.

In a generalized form, the work of the digital correlator is described as follows. At the inputs of the switch 1 of the SRNS signals, the samples of the actual SRNS GLONASS and GPS signals are generated, formed by analog-to-digital converters of the radio-frequency conversion unit of the SRNS signal receiver (not shown in the figures). In accordance with the command of processor 2, issued to the control register 11, the switch 1 of the SRNS signals connects to its output the signals of one of the SRNS - GLONASS or GPS. The signals of the selected SRNS are fed to the signal inputs of digital mixers 3 and 4, the reference inputs of which receive quadrature signals ("SIN" and "COS") of the reference frequency from the corresponding outputs of the digital controlled generator 5 of the carrier. A digitally controlled carrier generator 5 provides the generation of quadrature signals of the intermediate frequency of the given SRNS GLONASS letter, the binary code of which is issued by the processor 2, or the intermediate frequency of the SRNS GPS signals. Digital mixers 3 and 4 provide the selection of the signals of a given SRNS GLONASS letter or the signals of the SRNS GPS satellites and the transfer of the spectra of these signals to the main frequency band (to zero frequency). From the outputs of digital mixers 3 and 4, the signals are fed to the signal inputs of blocks 6 and 7 of digital demodulators, i.e. to the signal inputs of digital demodulators 6 ₁ ÷ 6 _K and 7 ₁ ÷ 7 _K. To the groups of reference inputs of blocks 6 and 7 of digital demodulators formed by the reference inputs of digital demodulators 6 ₁ ÷ 6 _K and 7 ₁ ÷ 7 _K , from the group of outputs of the programmed delay line 10, K copies of the reference code (C / A of the SRNS GLONASS or GPS code) are received offset from each other by a predetermined delay time, usually equal to half the duration of the C / A code symbol. Blocks 6 and 7 of digital demodulators using the digital demodulators 6 ₁ ÷ 6 _K and 7 ₁ ÷ 7 _K included in their composition correlate the in-phase and quadrature components of the processed signals with the indicated K copies of the reference code. Copies of the reference code are generated based on the signals from the output of the reference code generator 13, which generates reference pseudorandom C / A codes of the SRNS GLONASS or GPS satellites. The clock signal of 1.023 MHz for GPS or 0.511 MHz for GLONASS, necessary for the operation of generator 13, is supplied to its signal input from the output of a digital controlled code generator 12. The type of the generated pseudo-random code sequence and the clock frequency of the reference code are selected according to the instructions of processor 2 received through the data bus to the generators 12 and 13. The correlation results are accumulated in storage units 8 and 9 in the corresponding drives 8 ₁ ÷ 8 _K and 9 ₁ ÷ 9 _K at accumulation intervals equal in the search mode for a signal of 1/8 of the C / A code era (i.e., 1/8 ms), and in the signal tracking mode, the durations of the C / A code era (i.e. 1 ms )

The data (K in-phase and K quadrature correlation components) accumulated in the drives 8 ₁ ÷ 8 _K and 9 ₁ ÷ 9 _K are supplied to the first and second groups of signal inputs of the signal detector 14, and also through the data exchange bus to processor 2, in which the necessary signal processing algorithms are implemented and the necessary control commands and data are generated that are used in the search (detection) of the signal and subsequent tracking of the signal.

In the process of searching for the signal, the processor 2, based on the a priori uncertainty of the time-frequency position of the desired signal, sequentially sets the necessary search positions by the carrier frequency and by the code delay and gives the controller 15 a delay search range (the number of temporary positions at which to search for the signal) and the duration of the incoherent processing interval determined by a predetermined number N of millisecond epochs. The search position is set by setting the current frequency for the digital controlled generator 5 of the carrier, the code frequency for the digital controlled generator 12 of the code and the temporary position of the copies of the reference C / A code of the SRNS GLONASS or GPS using the control register 11, the reference code generator 13 and a programmable delay line 10. At the established search positions, the correlation processing described above is carried out with the formation of pairs of quadrature signals I (i, k) and Q (i, k) at the outputs of the storage units 8 and 9 K, where i is the number of int tearing within the epoch C / A code (i = 1 ... 8); k is the channel number of the correlation processing, determined by the number of the digital demodulator in groups 6 ₁ ÷ 6 _K and 7 ₁ ÷ 7 _K (k = 1 ... 16).

With a frequency of 0.125 ms (8 kHz), the quadrature signals I (i, k) and Q (i, k) are supplied, respectively, to the first and second groups of signal inputs of the signal detector 14, i.e. to the first and second group of signal inputs of the multiplexer 16. Under the action of the control signal from the controller 15, the multiplexer 16 alternately passes to its outputs pairs of quadrature signals related to one channel number "k" sequentially passing from the first channel number (k = 1) to the last (k = 16). Based on the total number of channels K = 16, the frequency of the output signals of the multiplexer 16 is 128 kHz.

From the outputs of the multiplexer 16, these pairs of quadrature signals are fed to the first and second signal inputs of the complex mixer 17, the reference inputs of which receive the signals Re (V (j, i)) and Im (V (j, i)) defined by the matrix [V] discrete Fourier transform coefficients. The complex mixer 17 converts quadrature signals by multiplying their values by the values of the Fourier coefficients. Each pair of quadrature samples of each of the K channels of correlation processing on the ith interval is multiplied by the column vector of the matrix [V] corresponding to this interval. The results of this multiplication are then summed up in block 18 of coherent summation, which generates the resulting signals of the implemented discrete Fourier transform for five frequency bins j (from the English "bin" is a sampling element) in the interval of one (n-th) epoch of C / A code (1 ms ) The operation of the block 18 coherent summation occurs under the influence of control signals received from the controller 15.

In order to reduce hardware costs and reduce energy losses, it is proposed to use the discrete Fourier transform option, which is a truncation of the standard 16-point discrete Fourier transform algorithm with additional zeros (see [8] - L. Rabiner, B. Gould. Theory and application of digital signal processing M., Mir, 1978, p. 395, 426), which makes it possible to obtain results for five frequency bins from the initial signals I (i, k) and Q (i, k) based on a 2-bit set of Fourier coefficients. This algorithm differs from the standard 16-point algorithm with additional zeros only in the used set of Fourier coefficients [V ₀ ÷ V ₇ ], shown in Fig.5, and the matrix of Fourier coefficients [V], shown in Fig.6.

The results of the discrete Fourier transform — the output signals of block 18 of coherent summation I (k, j, n) and Q (k, j, n), where n is the number of the millisecond era of the C / A code (n = 1 ... 255) —are received to the inputs of the module calculation unit 19, which performs the function of determining the module ρ (k, j, n) of the quadrature signals I (k, j, n) and Q (k, j, n).

Unit 19 for calculating the module generates at its output signals ρ (k, j, n) that determine the current values of the modules for each n-th millisecond era of C / A code for each j-th frequency bin and each k-th channel. In order to reduce hardware costs, the module calculation unit 19 is proposed to be implemented as a block that implements an approximate algorithm for determining the modules ρ (k, j, n) of quadrature signals I (k, j, n) and Q (k, j, n), which do not require operations to extract the square root of the sum of the squares of the terms and providing a calculation error of not more than 4%: ρ = II / 16 + I / 64 + I / 128 + Q / 4 + Q / 8 + Q / 64 + Q / 128 (for I > Q) (Poncelet algorithm).

From the output of the module calculation unit 19, the signals ρ (k, j, n) are fed to the signal inputs of the incoherent summing unit 20 and the noise power estimation unit 21.

The operation of the incoherent summing unit 20 and the type of signals generated at its first and second outputs depend on the stage being carried out — the stage of estimating the noise power or the stage of signal search.

At the stage of estimating the noise power, preceding the stage of signal search, at each new frequency position specified by writing a new value of the carrier frequency to a digitally controlled carrier generator 5, the incoherent summing unit 20 generates at its first output signals E _{k, j, N} , which are the maximum module values for each k-th channel and each j-th frequency bin in the time interval determined by a given number N millisecond epochs. These signals during the noise power estimation procedures are received at the end of the last (Nth) incoherent accumulation cycle at the information input of the noise power estimation block 21, the signal input of which receives signals ρ (k, j, n) from the output of the module definition block 19.

представляющие собой нарастающий итог суммирования модулей ρ(k, j, n) по n-м миллисекундным циклам за время некогерентного накопления, определяемое заданным числом N миллисекундных эпох. Эти сигналы при осуществлении процедур поиска и обнаружения полезного сигнала поступают на сигнальный вход блока 22 оценки наличия сигнала, на информационные входы которого поступают вычисленные процессором 2 по результатам оценки мощности шума начальные значения порогов П₀(j) и значения их приращений ΔП(j).At the next step after estimating the noise power, the signal search stage 20, the incoherent summing unit 20 generates signals at its second output

representing the cumulative summation of the modules ρ (k, j, n) over the nth millisecond cycles during the incoherent accumulation time, determined by a given number N of millisecond eras. These signals during the search and detection of the useful signal are fed to the signal input of the signal availability estimator 22, to the information inputs of which the initial threshold values П ₀ (j) and the values of their increments ΔП (j) calculated by the processor 2 are received from the noise power estimates

The main features of the noise power estimation stage are determined by the operation of the noise power estimation block 21 (Fig. 3) and are as follows.

поступают на вычитающие входы блока 27 вычитания.The information input of the noise power estimation block 21 at the stage of noise power estimation from the first output of the incoherent summing block 20 at the end of the last (Nth) incoherent accumulation cycle receives signals E _{k, j, N} representing, as indicated above, the maximum values of the modules for each k-th channel and each j-th frequency bin in the time interval determined by a given number N of millisecond epochs. These signals are summed up in block 21 for estimating the noise power in adders 28 ₁ ÷ 28 _J over all k channels for each j-th frequency bin. Summarization Results

arrive at the subtracting inputs of the subtraction unit 27.

т.e. общие суммы значений модулей ρ(k, j, n) для данного j-го частотного бина, для всех k=16 каналов и всех n=N миллисекундных эпох, в конце последнего (N-го) цикла некогерентного накопления поступают на суммирующие входы блока 27 вычитания, на вычитающие входы которого с выходов сумматоров 28₁÷28_J поступают результаты рассмотренного выше суммирования максимальных значений модулей для всех k=16 каналов

The signal input of block 21 estimates the noise power, i.e. to the first input of adder 25, signals ρ (k, j, n) are received, which are, as indicated above, the current values of the modules for each n-th millisecond era of C / A code for each j-th frequency bin and k-th channel . These signals are summed and accumulated in registers 24 ₁ ÷ 24 _J in accordance with their frequency bins in the interval determined by a given number N of millisecond epochs. Summation is carried out by periodically connecting the outputs of the corresponding registers 24 ₁ ÷ 24 _J through the multiplexer 26 to the second input of the adder 25. The accumulated summation results

i.e. the total sums of the modulus values ρ (k, j, n) for a given j-th frequency bin, for all k = 16 channels and all n = N millisecond eras, at the end of the last (N-th) cycle of incoherent accumulation go to the summing inputs of the block 27 subtractions, the subtracting inputs of which from the outputs of the adders 28 ₁ ÷ 28 _J receive the results of the summation of the maximum values of the modules considered above for all k = 16 channels

The subtraction unit 27 generates, for each frequency bin, the results of estimating the noise power P _j in the form of differences P _j = S (j) -Z (j). The signals that determine the results of evaluating the noise power from the output of the block 21 estimating the noise power through the data exchange bus are sent to the processor 2.

Based on the results of evaluating the noise power, the processor 2 calculates the initial values of the detection thresholds and their increments. This data in the form of information signals P ₀ (j) and ΔP (j) at the beginning of the signal search stage is sent to the signal presence estimation unit 22.

представляющие собой, как указано выше, нарастающий итог суммирования модулей ρ(k, j, n) по n-м миллисекундным циклам за время некогерентного накопления, определяемое заданным числом N, при каждом значении n сравниваются с нарастающим порогом

формируемым в блоке 22 на основе входных данных П₀(j) и ΔП(j), и по результатам сравнения вырабатывается выходной сигнал, свидетельствующий об обнаружении или отсутствии полезного сигнала. При этом, если при каком-то значении n величины E(k, j, n) для всех каналов k и частотных бинов j оказываются ниже порога, то принимается решение об отсутствии полезного сигнала на данной частотно-временной позиции. Если же хотя бы в одном частотном бине j одного из каналов k величина E(k, j, n) оказывается выше порога, то процесс некогерентного накопления продолжается до момента n=N, при этом фиксируется наличие сигнала в том частотном бине того канала, в котором значение E(k, j, n)≥П(j, N). Указанное сравнение осуществляется с помощью блока 29 сравнения, а хранение сигнала, несущего информацию об обнаружении или отсутствии полезного сигнала в каждом частотном бине каждого канала, осуществляется с помощью выходного регистра 30.The main features of the search stage and the detection of the useful signal are determined by the operation of the block 22 assess the presence of the signal (figure 4). Block 22 implements a truncated sequential single-threshold signal detection procedure. This procedure consists in the fact that the signals received at the signal input of block 22

which, as indicated above, are the cumulative summation of the moduli ρ (k, j, n) over the nth millisecond cycles during the incoherent accumulation time determined by the given number N, for each value of n they are compared with the increasing threshold

generated in block 22 on the basis of the input data P ₀ (j) and ΔP (j), and according to the results of the comparison, an output signal is generated that indicates the detection or absence of a useful signal. Moreover, if for some value of n the values of E (k, j, n) for all channels k and frequency bins j are below the threshold, then a decision is made about the absence of a useful signal at a given time-frequency position. If, at least in one frequency bin j of one of the channels k, the value E (k, j, n) is higher than the threshold, then the process of incoherent accumulation continues until n = N, and the presence of a signal in that frequency bin of that channel whose value is E (k, j, n) ≥P (j, N). The specified comparison is carried out using the comparison unit 29, and the storage of the signal carrying information about the detection or absence of a useful signal in each frequency bin of each channel is carried out using the output register 30.

осуществляется следующим образом. Начальные значения порогов П₀(j) для каждого j-го частотного бина записываются в соответствующие регистры 37₁÷37_J блока 32 начального значения порога, а значения приращения порогов ΔП₀(j) - в соответствующие регистры 39₁÷39_J блока 33 приращения порога. Начальные значения порога, выбираемые мультиплексором 38 для каждого j-го частотного бина, поочередно подаются на первый информационный вход блока 31 формирования порога, где они записываются в соответствующие регистры 34₁÷34_J. Значения приращения порогов, выбираемые мультиплексором 40 для каждого j-го частотного бина, поочередно подаются на второй информационный вход блока 31 формирования порога, т.е. на второй вход сумматора 35. На первый вход сумматора 35 с выхода мультиплексора 36 поочередно поступают текущие значения порогов, хранящиеся в регистрах 34₁÷34_J. В сумматоре 35 осуществляется прибавка приращения к текущему значению порога, после чего новое значение порога записывается в соответствующий регистр 34₁÷34_J. Текущие значения нарастающего порога, определяемые как

подаются на опорный вход блока 29 суммирования, на сигнальный вход которого поступают, как указано выше, сигналы

Согласованная работа блоков 31, 32 и 33 по формированию нарастающих порогов обеспечивается управляющими сигналами, поступающими с контроллера 15 на управляющий вход блока 22, т.е. на управляющие входы регистров 34₁÷34_J, 37₁÷37_J, 39₁÷39_J и мультиплексоров 36, 38, 40.Formation of the indicated rising threshold

carried out as follows. The initial threshold values П ₀ (j) for each j-th frequency bin are recorded in the corresponding registers 37 ₁ ÷ 37 _{J of the} block 32 of the initial threshold value, and the threshold increments ΔП ₀ (j) are written in the corresponding registers 39 ₁ ÷ 39 _{J of the} block 33 increment threshold. The initial threshold values selected by the multiplexer 38 for each j-th frequency bin are alternately fed to the first information input of the threshold generation unit 31, where they are recorded in the corresponding registers 34 ₁ ÷ 34 _J. The threshold increment values selected by the multiplexer 40 for each j-th frequency bin are alternately supplied to the second information input of the threshold generating unit 31, i.e. the second input of the adder 35. The first input of the adder 35 from the output of the multiplexer 36 alternately receives the current threshold values stored in the registers 34 ₁ ÷ 34 _J. In the adder 35, the increment is increased to the current threshold value, after which the new threshold value is recorded in the corresponding register 34 ₁ ÷ 34 _J. The current values of the rising threshold, defined as

are fed to the reference input of the summing unit 29, the signal input of which, as indicated above, receives signals

The coordinated work of blocks 31, 32 and 33 on the formation of increasing thresholds is provided by control signals from the controller 15 to the control input of block 22, i.e. to the control inputs of the registers 34 ₁ ÷ 34 _J , 37 ₁ ÷ 37 _J , 39 ₁ ÷ 39 _J and multiplexers 36, 38, 40.

If the search result is positive, the detection signal generated at the output of block 22 is transmitted to the signal input of the controller 15, which stops the search process. At the same time, the numbers of the frequency and time positions at which the useful signal is detected are recorded in the output register 30, and the last results of the incoherent summation of the modules are stored in the incoherent summing unit 20 for each channel and each frequency position. These data go to the information inputs of the block 23 for determining the time-frequency coordinates of the global maximum, which generates information signals about the time-frequency position of this maximum. This is accomplished by pairwise comparing the results of incoherent accumulation for those frequency bins (j) and channels (k) on which a signal is detected, and information about which is transmitted to the second information input of the frequency-time coordinates of the global maximum 23 from the output of the availability estimation unit 22 signal (i.e., from output register 30). Information signals generated by the block 23 determine the frequency-time coordinates of the global maximum, together with the message about the detection of the signal generated by the controller 15, are transmitted to the processor 2 to put the digital correlator in tracking mode for the detected signal.

If a useful signal is not detected, then the signal presence estimation unit 22 transmits to the controller 15 a signal absence signal at the given k × j time-frequency positions. In this case, the controller 15 issues a command to the reference code generator 13 to delay the reference code at K temporary positions, decreases the delay range specified at the beginning of the search mode by one, restores all blocks of the signal detector 14 to the initial state, and starts searching for the signal on the same the most frequency position set in the digital controlled oscillator 5 carrier (on the same five frequency bins), but at the new K temporary positions. If the signal is not detected in the entire specified search range for the delay, then the controller 15 gives the processor 2 a sign of the absence of a signal and stops the operation of the signal detector 14 until a new task is received from the processor 2.

Thus, it follows from the foregoing that the claimed invention is technically feasible and solves the task of creating a digital correlator of the SRNS signal receiver, in which the task of detecting the signal (regardless of its level) is performed by hardware, which allows you to really unload the processor and use its freed up resources for solving additional problems. Moreover, due to the use of a large number of time-frequency positions, which are searched, determined by the product J × K, where J = 5, K = 16, and also due to the possibility of estimating the noise level, which provides data for calculating thresholds in the processor, accelerated search and detection of signals in comparison with the prototype and analogues.

Claims (2)

1. A digital correlator of a signal receiver of satellite radio navigation systems (SRNS), comprising a signal changer SRNS, the signal inputs of which form the signal input of a digital correlator, the first and second blocks of digital demodulators, each of which contains a group of digital demodulators, the outputs of which form a group of outputs of the corresponding block of digital demodulators, the reference inputs form a group of reference inputs of the corresponding block of the digital demodulator, and the interconnected signal inputs - the signal the first input of the corresponding block of digital demodulators, the first and second digital mixers, the signal inputs of which are connected to the output of the SRNS signal switch, and the outputs are connected to the signal inputs of the corresponding blocks of digital demodulators, the first and second storage blocks, each of which contains a group of drives, whose clock inputs form the clock input of the corresponding memory block, the outputs form the group of outputs of the corresponding memory block, and the signal inputs - the group of signal inputs respectively a storage block associated with the group of outputs of the corresponding block of digital demodulators, a signal detector, the first and second groups of signal inputs of which are connected to the groups of outputs of the first and second storage blocks, a digital controlled carrier generator, the first and second outputs of which are connected to the reference inputs, respectively, of the first and a second digital mixer, a programmable delay line, the outputs of which are connected to groups of reference inputs of the first and second blocks of digital demodulator s, a reference code generator, the output of which is connected to the signal input of the programmable delay line, a digital controlled code generator, the output of which is connected to the signal input of the reference code generator, a control register, the outputs of which are connected to the control inputs of the programmable delay line, SRNS signal switch and reference generator code, as well as a processor connected via a data bus with a digital controlled code generator, a reference code generator, a control register, a digital controlled generator carrier, memory blocks and a signal detector, while the clock inputs of the memory blocks, programmable delay lines, digital controlled carrier generator and digital controlled code generator are connected to the digital input of the correlator, characterized in that the signal detector is made in the form of a quadrature detector that implements the calculation algorithm of five points of a sixteen-point discrete Fourier transform with additional zeros on the interval of one era of the C / A code, with the subsequent calculation it contains modules of conversion results and their incoherent summation and comparison with a variable threshold, the value of which is set depending on the noise power and incoherent reference number, and contains a controller connected to the processor via the data bus, the clock input of which is connected to the clock input of the digital correlator, and the command output - with the command input of the reference code generator, a multiplexer, the control input of which is connected with the corresponding control output of the controller, and the first and second groups with the needle inputs forming the first and second group of signal inputs of the signal detector are connected to the output groups of the corresponding storage units, a complex mixer, the first and second signal inputs of which are connected to the corresponding outputs of the multiplexer, and the reference inputs to the corresponding reference outputs of the controller, the coherent summation unit, the first and second signal inputs of which are connected to the corresponding outputs of the complex mixer, and the control input to the corresponding control output to the controller, the module calculation unit, the first and second signal inputs of which are connected to the corresponding outputs of the coherent summation unit, and the control input - with the corresponding control output of the controller, the incoherent summation block, the signal input of which is connected to the output of the module calculation unit, and the control input - with the corresponding the control output of the controller, the noise power estimation unit, the signal input of which is connected to the output of the module calculation unit, the information input is connected to the first output of the unit of a continuous summation, the control input is connected to the corresponding control output of the controller, and the output is connected via a data exchange bus with the processor, a signal presence assessment unit, the signal input of which is connected to the second output of the incoherent summation block, the output is connected to the signal input of the controller, the control input is connected to the corresponding control output of the controller, and the information inputs are connected via the data exchange bus with the processor, as well as the unit for determining the time-frequency coordinates of the global maxim ma, the first information input of which is connected to the first output of the incoherent summation block, the second information input is connected to the output of the signal presence estimation block, the control input is connected to the corresponding control output of the controller, and the output is connected via the data exchange bus with the processor. 2. The digital correlator according to claim 1, characterized in that the groups of drives and digital demodulators in each of the storage units and blocks of digital demodulators consist respectively of K drives and K digital demodulators, where K = 16.

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