RU2304359C2 - Mode of time-and-frequency synchronization of the liason system and arrangement for its execution - Google Patents

Abstract

FIELD: the inventions refer to the field of radio technique particularly to the mode and the arrangement of time-and-frequency synchronization of the liaison system.

SUBSTANCE: the evaluation of the temporary provision of the signal is executed in two stages. On the first stage a decisive function with a wide useful response is formed and that increases possibility of regular detection of the signal. On the second stage a decisive function with a narrow useful response is formed and that allows receive an exact evaluation of the temporary provision of the signal. The evaluation of the frequency shift is also formed in two stages. At that the quality of this evaluation is high because it is based on qualitative evaluation of the temporary provision of the signal. The other distinctive peculiarity of the invention is possibility of synchronization at relatively significant initial values of the frequency shift and that is unattainable to many known modes and arrangements of time-and-frequency synchronization.

EFFECT: increases noise immunity of time-and -frequency synchronization of the liaison system.

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Description

The invention relates to the field of radio engineering, in particular to a method and apparatus for time-frequency synchronization of a communication system.

In communication systems, the signal propagation channels between the receiver and the data transmitter are multipath and non-stationary. The effectiveness of communication systems is largely determined by the ability of time-frequency synchronization algorithms to provide in multipath non-stationary channels the necessary accuracy in estimating the temporal position of a signal and the frequency mismatch between the frequency of the input signal and the frequency of the reference oscillator.

Recently, communication systems with OFDM (Orthogonal Frequency Division Division Multiplexing) have been greatly developed. An OFDM signal is a sequence of OFDM symbols. Each such symbol consists of two parts - a prefix and a multi-frequency information symbol. A multi-frequency information symbol is the sum of modulated harmonics. The prefix means a certain sequence of samples of the signal, which immediately precedes each multi-frequency information symbol and is a part of this symbol. As a rule, the prefix duration is less than the duration of the information symbol. The presence of a prefix during signal processing can reduce or completely eliminate intersymbol interference (IEEE Std 802.11a - 1999, Prokis J., Digital Communications. Translation from English. M., Radio and Communications, 2000, p. 593) [1].

For the initial time-frequency synchronization, a special signal is usually used - the preamble that precedes the information message. In the IEEE 802.11a communication system (see Supplement to IEEE Standard for Information technology. Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in. The 5 GHZ Band) [2 ] the preamble and the information message are OFDM (Orthogonal Frequency Division Multiplexing) signals. The structure of the preamble is shown in FIG.

The preamble consists of two parts.

The first part of the preamble includes ten short training multi-frequency symbols and serves as a preliminary (“rough”) estimate of the temporal position and frequency detuning of the input signal. The second part of the preamble includes two long training multi-frequency symbols and a guard interval (prefix). The second part of the preamble serves for an accurate final assessment of the temporal position and frequency detuning of the input signal during initial synchronization.

There is a method of frequency and time synchronization described by Tufvesson F., Faulkne M., Hoeher P., Edfors O., OFDM Time and Frequency Synchronization by Spread Spectrum Pilot Technique // 8th IEEE Communication Theory Mini Conference in conjunction to ICC'99 ,. - June 1999. - P.115-119 [3]. This article proposes a method of frequency and time synchronization for OFDM systems, which is based on the use of a continuous code sequence. The code sequence is added to the OFDM information signal or used separately as a preamble signal. This method of time and frequency synchronization is as follows.

The input signal is processed in several filters, consistent with various parts of the known code sequence. The output signals of matched filters are used to form an integrated decision function. Each term of the decisive function is the sum of the pairwise products of the responses of the matched filters to the corresponding adjacent complex conjugate responses of the matched filters.

The estimate of the time delay (position) of the input signal is determined by the position of the maximum squared module of the decisive function. An estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined by the value of the argument of the decision function at the point corresponding to the estimate of the time delay.

The described method involves a one-stage procedure of time-frequency synchronization. As a result, with large values of the possible frequency shift between the carrier frequency of the input signal and the frequency of the reference signal, when implementing the method, it is necessary to use filters that are consistent with shorter parts of the known code sequence. This leads to a deterioration in the accuracy of estimating the time delay and frequency detuning and is the main disadvantage of this synchronization method.

A known method of time-frequency synchronization described in the article Schmidl T.M., Sox D. C., Robust Frequency and Timing

In [4], a method was proposed for synchronizing signal parameters in OFDM (Orthogonal Frequency Division Multiplexing) systems, which is based on the reception of a preamble consisting of two OFDM symbols. In the synchronization process at the first stage, the temporal position of the signal is determined from the first symbol, and a preliminary estimation of the partial mismatch is carried out with an accuracy of n · π · T, n = 1, 2 ..., T is the duration of the OFDM symbol. The final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is carried out in a second step using a second OFDM symbol.

The first OFDM symbol consists of two identical parts, which differ in phase shift reception. First, the complex decisive function of the first stage is formed as the product of the samples of the first part of the symbol and the corresponding complex conjugate samples of the second part of the symbol. The estimate of the time delay of the input signal is determined by the position of the maximum squared module of the decisive function of the first stage. A preliminary estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal is calculated by the value of the argument of the decision function of the first stage at the point corresponding to the estimate of the time delay.

To determine the final estimate of the frequency mismatch, a decisive function of the second stage is formed for all possible values of n using both OFDM symbols. The estimate of the parameter n is determined by the position of the maximum of the decisive function of the second stage.

The disadvantage of the described method is the low accuracy of estimating the temporal position of the signal due to the very wide flat top of the decision function of the first stage, the width of which is equal to the duration of the OFDM symbol prefix. In addition, the disadvantage is the incomplete use of the preamble resource, namely the rejection of the use of the second OFDM symbol in estimating the temporal position of the signal. These disadvantages lead to low noise immunity of the time-frequency synchronization of the communication system.

In an article by Chia-Sheng Peng, Chian-Himg Cho and K.A. Wen, Frame Synchronization and Digital AGC for OFDM Based WLAN Proceedings Vol. 2 of European Wireless 2002, pp. 835-839, Feb. 2002 [5] a time synchronization algorithm and AGC (Automatic Gain Control) are proposed in the IEEE 802.11a communication system. In accordance with the algorithm proposed in [5], the beginning of the frame and the end of the first part of the preamble are determined by the threshold crossing the following value

where s (n) are the samples of the received OFDM signal,

N _g = 16.

The threshold is determined based on the average signal power calculated in a sliding window. After determining the start of the frame, AGC is performed using the magnitude module (1). After determining the start of the frame, symbol synchronization is also performed using a filter consistent with the short OFDM symbol. The output samples of the matched filter are compared with a threshold. At the end of the first part of the preamble and the threshold is exceeded, the output samples of the matched filter decide on time synchronization.

The disadvantage of the described synchronization method is the rejection of incoherent processing in symbolic (temporary) synchronization, which leads to low noise immunity of the time synchronization of the communication system. In addition, the article does not describe the frequency synchronization procedure.

In the article by N. Kobayashi, K. Mori, T. Nagaosa. Proposal of Symbol Timing and Carrier Frequency Synchronization Method for Burst Mode OFDM Signal // IEICE Trans. Commun., Vol. E86-B, No.1, January 2003 [6] describes a time-frequency synchronization algorithm in an OFDM communication system using a preamble signal (similar to that shown in FIG. 1).

In accordance with the described algorithm for the implementation of time synchronization, first form the products of complex conjugate samples of the input signal to complex samples of the input signal delayed by one sample. The resulting products are fed to the correlator, the reference signal of which is the product of the known time samples of the preamble to the complex conjugate samples of the preamble, delayed by one sample. From the output of the correlator, the signal is fed to the input of the peak detector, which determines the temporary position of the preamble signal from the position of the maximum output signal of the correlator. Frequency mismatch estimation is proposed to be carried out in two stages. At the first stage, a preliminary estimate of the frequency mismatch is formed, and at the second, an accurate estimate of the frequency mismatch is formed. At the first stage, using the estimation of the temporal position of the preamble signal, the products of the samples of the input signal and the complex conjugate samples of the known preamble signal are first formed. A preliminary estimate of the frequency mismatch is obtained by the Fourier transform of the resulting product. Next, the input signal is adjusted in accordance with the obtained estimate. In a second step, the Fourier transform OFDM symbols of the corrected input signal are first performed. Then, the products of the complex conjugate results of the conversion of the first symbol to the corresponding conversion results of the second OFDM symbol of the input signal are found. An accurate estimate of the frequency mismatch is obtained by correlating the resulting product with a reference signal.

The disadvantages of the described method of time-frequency synchronization include the rejection of coherent processing during time synchronization, the lack of accounting for changes in the level of the input signal (as a result of the functioning of the AGC system). These disadvantages lead to low noise immunity of the time-frequency synchronization of the communication system. The disadvantages also include a large decision delay time, which requires hardware complexity (there is a need for delay lines with a large amount of memory).

Closest to the claimed solution is a method of time-frequency synchronization of a communication system and an algorithm for its implementation, described in the book Nee R. Prasad R., OFDM for Wireless Multimedia Communication, London: “Artech House”, 2000, Chapter 4. Synchronization. 4.6. Synchronization using Special Training Symbols, pp. 86-88; Chapter 10. Applications of OFDM. 10.5.4 Training, pp. 246-247 [7].

This method of time-frequency synchronization of a communication system is as follows:

the input signal is filtered, amplified, automatic gain control is performed, calculating the gain of the input signal depending on the power level of the input signal, transfer to the video frequency, carry out its analog-to-digital conversion and decimation, forming the input digital complex signal at the video frequency;

time-frequency synchronization is carried out in two stages:

at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined, for which:

filtering the input digital complex signal, consistent with one short multi-frequency symbol, forming complex responses of the first stage;

calculate the squares of the modules of the complex responses of the first stage, forming the decisive function of the first stage;

determine the temporary position of the local maxima of the decisive function of the first stage, exceeding a predetermined threshold of the first stage H1;

remember the complex responses of the first stage, corresponding to the local maxima of the decisive function of the first stage;

form a preliminary estimate of the frequency shift by the averaged phase difference of the complex responses of the first stage, corresponding to the local maxima of the decisive function of the first stage;

at the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal is performed, for which:

correcting the phase of the input digital complex signal in the interval of operation of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal;

filtering the corrected input digital complex signal, consistent with one long multi-frequency symbol, forming complex responses of the second stage;

calculate the squares of the modules of the complex responses of the second stage, forming the decisive function of the second stage;

comparing the values of the decisive function of the second stage with a predetermined threshold of the second stage H2, if the threshold is not exceeded, the preamble is assumed to be undetected;

when the threshold of the second stage H2 is exceeded, the preamble is considered to be detected, then:

determining an estimate of the temporary position of the preamble by the temporary position of the first exceeding the threshold of the second stage H2;

determine the temporary position of the local maxima of the decisive function of the second stage, exceeding a predetermined threshold of the second stage H2;

determining an additional estimate of the frequency shift by the phase difference of the two complex responses of the second stage, corresponding to the local maxima of the decisive function of the second stage;

determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift.

Automatic gain control is performed by changing the gain of the analog amplifier. The gain is formed by assessing the level (power) of the received signal (prototype description p. 10.4 p. 235).

The assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined to be equal to the difference in the temporary position of the first exceeding the threshold of the second stage H2 and the sum of the durations of the first part of the preamble and the prefix.

An additional estimate of the frequency shift is determined, for example, as the ratio of the phase difference of the adjacent complex responses of the second stage to the duration of a long multi-frequency symbol.

Note that in the above-mentioned information source, the structural diagram of the time-frequency synchronization device of the communication system is not shown. However, from the description of the algorithm, you can imagine a device that implements the prototype method. The prototype device is shown in Fig.2.

The prototype device (Figure 2) contains a receiving path 1, the first 2 and second 3 matched filters, performing in the first stage matched with one short multi-frequency symbol filtering the generated input digital complex signal and forming complex responses of the first stage, the first 4 and second 5 multipliers , the first adder 6, a complex multiplier 7, a harmonic generation unit 8, a frequency shift calculation unit 9, a first threshold comparison unit 10, a control unit 11, a clock 12, a third 13 and a fourth 14 Glazed filters, performing the second stage filtering of the corrected digital input complex signal, consistent with one long multi-frequency symbol, and generating complex responses of the second stage, the third 15 and fourth 16 multipliers, the second adder 17, the second threshold comparison unit 18, the additional frequency shift calculation unit 19 , the third adder 20, while the input of the receiving path 1 is the input of the device, the first output of the receiving path 1 is connected to the input of the first matched filter 2 and the first input the complex multiplier 7, the second output of the receiving path 1 is connected to the input of the second matched filter 3 and the second input of the complex multiplier 7, the output of the first matched filter 2 is connected to the first and second inputs of the first multiplier 4 and the second input of the frequency shift calculation unit 9, the output of the second matched filter 3 is connected to the first and second inputs of the second multiplier 5 and the third input of the frequency shift calculation unit 9, the outputs of the first 4 and second 5 multipliers are connected respectively to the first and second the first inputs of the first adder 6, the output of which is connected to the first input of the first comparison unit 10 with a threshold, the second input of which is combined with the fourth input 9 of the frequency shift calculation unit and connected to the first output of the control unit 11, the output of the first comparison unit 10 with the threshold is connected to the first the input of the frequency shift calculation unit 9 and the first input of the control unit 11, the second output of which is the first output of the device, the fourth output of the control unit 11 is connected to the fifth input of the frequency shift calculation unit 9, and the third output with the first input of the additional frequency shift calculation unit 19, the second input of the control unit 11 is combined with the second input of the harmonic generation unit 8 and connected to the output of the clock generator 12, the first input of the harmonic generation unit 8 is combined with the first input of the third adder 20 and connected to the output of block 9 of calculating the frequency shift, the first and second outputs of the harmonics forming unit 8 are connected respectively to the third and fourth inputs of the complex multiplier 7, the first and second outputs of which are connected respectively with the inputs of the third 13 and fourth 14 matched filters, the output of the third matched filter 13 is connected to the first and second inputs of the third multiplier 15 and the second input of the additional frequency shift calculation unit 19, the output of the fourth matched filter 14 is connected to the first and second inputs of the fourth multiplier 16 and the third the input of block 19 for calculating the additional frequency shift, the outputs of the third 15 and fourth 16 multipliers are connected respectively to the first and second inputs of the second adder 17, the output of which is is dined with the first input of the second comparison unit 18 with a threshold, the second input of which is combined with the fourth input of the additional frequency shift calculation unit 19 and connected to the fifth output of the control unit 11, the output of the second comparison unit 18 with the threshold is connected with the third input of the control unit 11 and the fifth input block 19 calculating the additional frequency shift, the output of block 19 calculating the additional frequency shift is connected to the second input of the third adder 20, the output of which is the second output of the device.

Device frequency-time synchronization of a communication system (Figure 2) works as follows.

On the receiving side in the receiving path 1, the input signal is pre-filtered, amplified, transferred to the video frequency, its analog-to-digital conversion, decimation, etc. As a result, an input digital complex signal is generated at the video frequency. For time-frequency synchronization, which consists of two stages, a preamble signal is used. In this case, at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined. At the second stage, the temporal position of the preamble is estimated and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is performed.

At the first stage, the in-phase and quadrature components of the input digital complex signal from the first and second outputs of the receiving path 1 are fed respectively to the inputs of the first 2 and second 3 matched filters and to the first and second inputs of the complex multiplier 7.

In matched filters 2 and 3, at the first stage, filtering, respectively, in-phase and quadrature components of the input digital complex signal, consistent with one short multi-frequency symbol, is carried out and responses are generated for the in-phase and quadrature components of the input digital complex signal, which are received respectively at the first and second inputs of multipliers 4 and 5 and to the second and third inputs of the frequency shift calculation unit 9. In multipliers 4 and 5, the squares of the responses for the in-phase and quadrature components of the input digital complex signal of the first stage are calculated, which are supplied to the first and second inputs of the first adder 6. In the first adder 6, by summing the corresponding squares of the responses of the in-phase and quadrature components of the input digital complex signal, the squares are calculated modules of complex responses of the first stage, forming the decisive function of the first stage. The responses of the first stage come from the output of the first adder 6 to the first input of the first block 10 comparison with the threshold.

In the first block 10 comparison with the threshold sequentially compare the results of the summation of the output of the first adder 6 with the threshold of the first stage H1. The comparison results from the output of the first comparison unit 10 with a threshold are supplied to the first input of the frequency shift calculation unit 9 and to the first input of the control unit 11.

At the second input of the first block 10 comparison with the threshold and at the fourth input of the block 9 for calculating the frequency shift from the first output of the control unit 11, a control signal corresponding to the end of the time domain of exceeding the decision function values of the first stage of the threshold H1 is exceeded. This signal sets the initial (initial) threshold value of the first stage in the first block 10 for comparison with the threshold, and the in-phase and quadrature components of the complex responses of the first stage corresponding to the local maximum of the decision function of the first stage (received in the second and third the inputs of block 9 with matched filters 2 and 3).

In the block 9 for calculating the frequency shift by the signal of exceeding the threshold of the first stage and by the control signal of the end of the time domain of exceeding by the values of the decisive function of the first stage of the threshold H1, temporary positions corresponding to local maxima of the decisive function of the first stage are determined.

Based on the signal that the first part of the preamble is received from the fourth output of the control unit 11 to the fifth input of the frequency shift calculation unit 9, in block 9, a preliminary estimate of the frequency is determined from the in-phase and quadrature components of the complex responses of the first stage, corresponding to the local maxima of the decisive function of the first stage shear. A preliminary estimate of the frequency shift is formed, for example, as the ratio of the averaged phase difference of the complex responses of the first stage corresponding to local maxima to the duration of a short multi-frequency symbol. The averaged phase difference is formed, for example, as follows. For temporary positions of local maxima of the decisive function of the first stage, the sum of the products of pairs of current complex responses and previous complex conjugate responses is formed. The value of the argument of the obtained complex number is equal to the averaged phase difference. Moreover, the ratio of the averaged phase difference to the duration of a short multi-frequency symbol is equal to a preliminary estimate of the frequency shift.

An estimate of the preliminary frequency shift is supplied from the output of the frequency shift calculation unit 9 to the first input of the harmonic generation unit 8 and to the first input of the third adder 20, and it corresponds to the preliminary estimate of the frequency detuning. At the second input of the harmonics forming unit 8 and at the second input of the control unit 11, a clock signal is supplied from the output of the clock generator 12.

In block 8, the harmonics are generated from the preliminary estimate of the frequency shift and the signal from the clock generator 12 to form a complex multiplier of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the temporary position of the current samples, which corresponds to the standard exponential representation of the complex factor. Alternatively, the complex factor may be equivalently formed as an in-phase and quadrature component. In this case, the in-phase part of the complex factor is equal to the cosine, and the imaginary part is the sine of the argument, which is equal to the product of the preliminary estimate of the frequency shift by the temporary position of the current samples. This representation of the complex factor is easily implemented in a functional converter based on a memory device in which the values of the corresponding samples of the sine and cosine functions are recorded.

The generated quadrature components of the complex factor from the first and second outputs of the harmonics forming unit 8 are supplied to the third and fourth inputs of the complex multiplier 7, respectively.

In the complex multiplier 7, the phase of the input digital complex signal is corrected for the second synchronization stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal obtained in the first stage. To do this, in the complex multiplier 7 carry out the well-known operation of multiplying the samples of the input digital complex signal by a complex factor.

The in-phase and quadrature components of the adjusted input digital complex signal from the first and second outputs of the complex multiplier 7 are fed to the inputs of the third 13 and fourth 14 matched filters, respectively.

In the matched filters 13 and 14, for the in-phase and quadrature components of the input corrected digital complex signal, filtering is performed, consistent with one long multi-frequency symbol, and the second-phase and common-mode and quadrature responses are generated respectively. The generated in-phase and quadrature components of the responses of the second stage from the outputs of the matched filters 13 and 14 are supplied respectively to the first and second inputs of the third 15 (in-phase) and fourth 16 (quadrature) multipliers and to the second and third inputs of the additional frequency shift calculation unit 19. In the multipliers 15 and 16, respectively, the squares of the in-phase and quadrature components of the responses of the second stage are formed, which are fed to the first and second input of the second adder 17, where by summing them the squares of the modules of the complex responses of the second stage are calculated, obtaining the decisive function of the second stage. The calculated squares of the second-stage complex response modules from the output of the second adder 17 are supplied to the first input of the second comparison unit 18 with a threshold.

In the second block 18 comparison with the threshold compares the squares of the modules of the complex responses of the second stage with the threshold of the second stage H2. The result of the comparison from the output of the second comparison unit 18 with a threshold is supplied to the third input of the control unit 11 and to the fifth input of the additional frequency shift calculation unit 19.

If the threshold H2 is not exceeded, the preamble is assumed to be undetected and the frequency-time synchronization procedure is continued.

If the threshold is exceeded, H2 is assumed to be detected. In this case, the signals for exceeding the threshold in the control unit 11 determine the assessment of the temporary position of the preamble as the temporary position of the first exceeding the threshold of the second stage H2. The resulting estimate from the second output of the control unit 11 is fed to the first output of the device.

The final assessment of the temporary position of the preamble is determined to be equal to the difference in the temporary position of the first exceeding the threshold of the second stage H2 and the sum of the durations of the first part of the preamble and the prefix.

From the fifth output of the control unit 11, to the second input of the second threshold comparison unit 18 and to the fourth input of the additional frequency shift calculation unit 19, a signal is received for receiving the second part of the preamble equal to, for example, a logical unit.

In block 19 for calculating the additional frequency shift by the signal of exceeding the threshold and by the control signal of the end of the time domain of exceeding by the values of the decisive function of the threshold of the second stage, temporary positions corresponding to local maxima of the decisive function of the second stage are determined.

In block 19 for calculating the additional frequency shift by the signal of the end of the reception of the second part of the preamble, the in-phase and quadrature components of the complex responses of the second stage, corresponding to the local maxima of the decisive function of the second stage, are used to determine the additional frequency shift.

Evaluation is performed, for example, as follows. The phase difference of two complex responses of the second stage, corresponding to local maxima, is formed as the product of the complex conjugate response to the subsequent complex response. As a result, the argument of the obtained complex number corresponds to an estimate of the additional phase shift. An additional estimate of the frequency shift is determined, for example, as the ratio of the estimate of the additional phase shift to the duration of the long multi-frequency symbol. An additional estimate of the frequency shift from the output of block 19 is supplied to the second input of the third adder 20. In the third adder 20, the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined as the sum of the preliminary and additional estimates of the frequency shift. The resulting final estimate from the output of the third adder 20 is fed to the second output of the device.

The disadvantages of the prototype method and device include the rejection of a preliminary assessment of the temporary position of the signal and, as a result, from the use of incoherent processing at the first stage. This drawback leads to insufficiently high noise immunity of the estimation of the temporary position and frequency mismatch, especially in conditions of multipath signal propagation. The presence of a prefix in the second part of the preamble may lead to an abnormal error in assessing the temporary position in the second stage.

The problem that the proposed invention solves is to increase the noise immunity of the time-frequency synchronization of the communication system.

This problem is solved in that in the method of time-frequency synchronization of a communication system, namely, that

the input signal is filtered, amplified, automatic gain control is performed, calculating the gain of the input signal depending on the power level of the input signal, transfer to the video frequency, carry out its analog-to-digital conversion and decimation, forming the input digital complex signal at the video frequency,

time-frequency synchronization is performed in two stages:

at the first stage, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined, for which:

- carry out the filtering of the input digital complex signal, consistent with one short multi-frequency symbol, forming complex responses of the first stage,

- calculate the squares of the modules of the complex responses of the first stage,

- carry out a comparison with a given threshold of the first stage,

- determine a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal,

at the second stage, the temporal position of the preamble is estimated and the frequency offset is finally estimated between the carrier frequency of the input signal and the frequency of the reference signal, for which:

- adjust the phase of the input digital complex signal on the interval of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal,

- carry out the filtering of the phase-corrected input digital complex signal, consistent with one long multi-frequency symbol, forming complex responses of the second stage,

- calculate the squares of the modules of the complex responses of the second stage,

- carry out a comparison with a given threshold of the second stage, if the threshold is not exceeded, the preamble is assumed to be undetected,

- when the threshold of the second stage is exceeded, the preamble is considered to be detected, then the final estimate of the temporary position of the preamble is determined by the temporary position of the first excess of the threshold of the second stage,

- determine the assessment of the temporary position of the preamble by the temporary position of the first excess of the threshold of the second stage,

- determine an additional estimate of the frequency shift by the phase difference of the complex responses of the second stage,

determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift,

according to the invention:

when performing the first stage of the time-frequency synchronization, a preliminary estimate of the temporary position of the second part of the preamble is determined, for which:

calculate the correction coefficient of the power level of the generated input signal,

correcting the generated input digital complex signal using the calculated correction coefficient of the power level of the generated input signal,

forming the complex responses of the first stage, filter the corrected input digital complex signal,

remember the complex responses of the first stage,

calculate the sum of N squares of the modules of the complex responses of the first stage, taken with an interval equal to the duration of the short multi-frequency symbol,

compare the received amount with a given threshold of the first stage, if the threshold is exceeded:

the temporary position of the beginning of the preamble corresponding to the amount received is considered the current temporary position of the preamble,

,form the current estimate of the frequency shift by the averaged phase difference of adjacent complex responses of the first stage from the n-th to the (N-n + 1) -th corresponding to the summation terms, where n is an integer,

,

the threshold of the first stage is set equal to the received amount,

if at least one threshold is exceeded for the first stage, and then the threshold for the first stage is not exceeded from the time the last threshold was exceeded for an interval equal to the duration of the short multi-frequency symbol, then

determine a preliminary assessment of the temporary position of the second part of the preamble for the current temporary position of the preamble,

a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal is determined as the current estimate of the frequency shift,

the threshold of the first stage is assumed to be equal to the initial value, and the current temporary position of the preamble is considered undefined;

at the second stage, a final assessment of the temporary position of the preamble is carried out, for which:

determine the a priori interval of the temporary position of the second part of the preamble by preliminary estimation of the temporary position of the second part of the preamble,

the squares of the modules of the complex responses of the second stage are compared with a predetermined threshold of the second stage on an a priori interval of the time position of the second part of the preamble,

according to the temporary position of the first excess of the threshold of the second stage, the assessment of the temporary position of the preamble is determined as final,

find complex spectra of long multi-frequency symbols of the phase-corrected input digital complex signal, the temporary positions of which are determined by the temporary position of the first threshold exceeding the second stage,

an additional estimate of the frequency shift is determined by the average phase difference of the corresponding elements of the complex spectra of long multi-frequency symbols.

The generated input digital complex signal is corrected, for example, by multiplying by the ratio of the gain of the receive path, at which the first threshold of the first stage is exceeded, by the current gain of the receive path; if not a single excess of the threshold of the first stage has occurred, then the generated input digital complex signal is multiplied by a factor equal to unity.

A current estimate of the frequency shift is formed, for example, as the ratio of the averaged phase difference of the complex responses of the first stage to the duration of a short multi-frequency symbol.

The beginning of the a priori time interval of the second part of the preamble is determined, for example, by the sum of the preliminary estimate of the temporary position of the second part of the preamble, the duration of the (N-2) x short multi-frequency symbol and the duration of the prefix, where N is the number of short multi-frequency symbols in the preamble.

The end of the a priori time interval of the temporal position of the second part of the preamble is determined, for example, by the sum of the preliminary estimate of the temporal position of the second part of the preamble, the duration of (N + 2) -x short multi-frequency symbols and the duration of the prefix, where N is the number of short multi-frequency symbols in the preamble.

The phase of the input digital complex signal in the interval of operation of the second stage is adjusted by multiplying the samples of the input digital complex signal by a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the time positions of the samples.

An additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of the corresponding elements of the complex spectra of long multi-frequency symbols to the duration of a long multi-frequency symbol.

The final assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined equal to the difference in the temporary position of the first threshold exceeding the second stage and the sum of the durations of the first part of the preamble and the prefix.

The problem is also solved by the fact that in the device of the time-frequency synchronization of a communication system containing

the receiving path, which generates an input digital complex signal at the video frequency at the outputs, the first and second matched filters, filtering the common-phase and quadrature components of the generated input complex digital signal matched with one short multi-frequency symbol, forming complex responses of the first stage, the first and second multipliers, the first adder, complex multiplier, harmonic generation unit, frequency shift calculation unit, threshold comparison unit, control unit phenomena, a clock generator that generates a clock signal at the output, the third and fourth matched filters, filtering the phase-corrected input digital complex signal matched with one long multi-frequency symbol, forming complex responses of the second stage, third and fourth multipliers, second adder, calculation unit additional frequency shift and the third adder, while the input of the receiving path is the input of the device, the first and second outputs of the receiving path are connected respectively, with the first and second inputs of the complex multiplier, the outputs of the first and second multipliers are connected respectively to the first and second inputs of the first adder, the output of which is connected to the first input of the comparison unit with a threshold, the second input of which is connected to the first output of the control unit, the output of the comparison unit with a threshold connected to the first input of the frequency shift calculation unit, the output of which is connected to the first input of the harmonic generation unit and the first input of the third adder, the second input of the formation unit r rmonics is connected to the output of the clock generator, the first and second outputs of the harmonic generation unit are connected respectively to the third and fourth inputs of the complex multiplier, the first and second outputs of which are connected respectively to the inputs of the third and fourth matched filters, the output of the third matched filter is connected to the first and second inputs of the third multiplier, the output of the fourth matched filter is connected to the first and second inputs of the fourth multiplier, the outputs of the third and fourth multiply of the units is connected respectively to the first and second inputs of the second adder, the second output of the control unit is the first output of the device that generates an estimate signal for the temporal position of the preamble at this output, the third output of the control unit is connected to the first input of the additional frequency shift calculation unit, the output of which is connected to the second input the third adder, forming the output signal of the final assessment of the frequency shift, the output of the third adder is the second output of the device,

according to the invention additionally introduced:

fifth and sixth multipliers for correcting the power level of the generated input signal,

a unit for calculating the coefficient of correction of the power level of the generated input signal,

first and second delay lines,

(N-1) first and (N-1) second multipliers,

a block for determining the boundaries of the a priori interval, which generates at the first output a signal of not exceeding the threshold of the first stage from the time of the last threshold exceeding for an interval equal to the duration of the short multi-frequency symbol, at the second output, the signal at the beginning of the a priori interval of the time position of the second part of the preamble, at the third output, a signal the end of the a priori time interval of the second part of the preamble,

key,

comparator

wherein the first output of the receiving path is connected to the first input of the fifth multiplier, the second output of the receiving path is connected to the first input of the sixth multiplier, the third output of the receiving path is connected to the first input of the block for calculating the power level correction coefficient of the generated input signal, the second input of which is combined with the first input of the block determining the boundaries of the a priori interval and is connected to the output of the comparison unit with a threshold,

the output of the block for calculating the coefficient of correction of the power level of the generated input signal is connected to the second inputs of the fifth and sixth multipliers,

the output of the fifth multiplier is connected to the input of the first matched filter, filtering the adjusted input digital complex signal, the output of the first matched filter is connected to the input of the first delay line,

the output of the sixth multiplier is connected to the input of the second matched filter, the output of which is connected to the input of the second delay line,

N outputs of the first delay line are connected to their respective N first and N second inputs of their respective N first multipliers and N second inputs of the frequency shift calculator, the outputs (N-1) of the first multipliers are connected to (N-1) additional first inputs of the first adder,

N outputs of the second delay line are connected to their respective N first and N second inputs of their respective N second multipliers and N by the third inputs of the frequency shift calculator, the outputs (N-1) of the second multipliers are connected to (N-1) additional second inputs of the first adder, forming at the output the sum of N squares of the modules of the complex responses of the first stage,

the second and third inputs of the block for calculating the additional frequency shift are connected respectively to the first and second outputs of the complex multiplier,

the second input of the block determining the boundaries of the a priori interval and the fourth input of the block for calculating the additional frequency shift are combined and connected to the output of the clock generator,

the first input of the control unit and the third input of the comparison unit with a threshold are combined and connected to the first output of the unit for determining the boundaries of the a priori interval, the second and third outputs of which are connected respectively to the second and third inputs of the control unit, which generates a control signal at the first output that determines the moment of completion or repeated start the execution of the first stage, at the third - a signal of the presence of at least one exceeding the threshold of the second stage, at the fourth output - a control signal that determines the time interval and the current time is within a delay interval priori temporal position of the second part of the preamble, the fourth output of the control unit is connected to the first input key,

the second key input is connected to the output of the second adder, and the output to the comparator input, the output of which is connected to the fourth input of the control unit, the second output of which is connected to the fifth input of the additional frequency shift calculation unit.

The inventive method of time-frequency synchronization of a communication system and a device for its implementation have significant differences from the closest analogues found when searching from the prior art.

These differences are as follows: the temporal position of the preamble signal is evaluated in two stages, and at the first stage, they form a decisive function with a wide useful response, which increases the likelihood of capturing a successful preliminary estimate of the temporal position, and at the second stage, they form a decisive function with a narrow useful response, which provides an accurate estimate of the temporal position of the preamble signal. The frequency shift estimate is also formed in two stages, and the quality of this estimate is high, because it is based on a qualitative assessment of the temporary position.

The invention is illustrated by examples and drawings:

Figure 1 shows the structure of the preamble of the OFDM (Orthogonal Frequency Division Division Multiplexing) signal.

Figure 2 shows the structural diagram of the device of the prototype.

Figure 3 shows the structural diagram of the inventive device.

Figure 4 shows the structural diagram of block 23 for calculating the coefficient of correction of the power level of the generated input signal.

Figure 5 shows the structural diagram of the block 25 for determining the boundaries of the a priori interval,

Figure 6 shows the structural diagram of the block 10 comparison with the threshold.

Figure 7 shows the structural diagram of block 19 for calculating the additional frequency shift.

Fig. 8 shows a block diagram of a control unit 11.

The inventive device of the time-frequency synchronization (Figure 3) contains a receiving path 1, the first 2 and second 3 matched filters, the first 4 ₁ and second 5 ₁ multipliers, the first adder 6, a complex multiplier 7, a harmonics generation unit 8, a frequency calculation unit 9 a shift, a threshold comparison unit 10, a control unit 11, a clock 12, a third 13 and a fourth 14 matched filters, a third 15 and a fourth 16 multipliers, a second adder 17, an additional frequency shift calculator 19 and a third adder 20, while the input of the receiving truck This 1 is the input of the device, the first and second outputs of the receiving path 1 are connected respectively to the first and second inputs of the complex multiplier 7, the outputs of the first 4 ₁ and second 5 ₁ multipliers are connected respectively to the first and second inputs of the first adder 6, the output of which is connected to the first input a comparison unit 10 with a threshold, the second input of which is connected to the first output of the control unit 11, the output of the comparison unit 10 with a threshold is connected to the first input of the frequency shift calculation unit 9, the output of which is connected to the first input ka 8 harmonic generation and the first input of the third adder 20, the second input of the harmonic generation unit 8 is connected to the output of the clock generator 12, the first and second outputs of the harmonic generation unit 8 are connected respectively to the third and fourth inputs of the complex multiplier 7, the first and second outputs of which are connected respectively with the inputs of the third 13 and fourth 14 matched filters, the output of the third matched filter 13 is connected to the first and second inputs of the third multiplier 15, the output of the fourth matched the filter 14 is connected to the first and second inputs of the fourth multiplier 16, the outputs of the third 15 and fourth 16 multipliers are connected respectively to the first and second inputs of the second adder 17, the second output of the control unit 11 is the first output of the device, the third output of the control unit 11 is connected to the first input of the unit 19 calculating an additional frequency shift, the output of which is connected to the second input of the third adder 20, the output of the third adder 20 is the second output of the device, according to the invention further comprises : fifth 21 and sixth 22 multipliers, block 23 for calculating the power factor correction coefficient of the generated input signal, the first 24 and second 25 delay lines, (N-1) first 4 _i -4 _N and (N-1) second 5 _i -5 _N multipliers, a priori interval boundary determination unit 25, a key 27 and a comparator 28, wherein the first output of the receive path 1 is connected to the first input of the fifth multiplier 21, the second output of the receive path 1 is connected to the first input of the sixth multiplier 22, the third output of the receive path 1 is connected to the first input of block 23 for calculating the correction coefficient the power level of the generated input signal, the second input of which is combined with the first input of the block for determining the boundaries of the a priori interval and connected to the output of the comparison unit 10 with a threshold, the output of the block 23 for calculating the correction factor of the power level of the generated input signal is connected to the combined second inputs of the fifth 21 and sixth multipliers, the output of the fifth multiplier 22 is connected to the input of the first matched filter 2, the output of which is connected to the input of the first delay line 24, the output of the sixth multiplier 22 s connected to the input of the second matched filter 3, the output of which is connected to the input of the second delay line 25, N outputs of the first delay line 24 are connected to their respective N first and N second inputs of their respective N first multipliers 4 ₁ -4 _N and N by the second inputs of block 9 for calculating the frequency shift, the outputs (N-1) of the first multipliers are connected to (N-1) additional first inputs of the first adder 6, N outputs of the second delay line 25 are connected to their corresponding N first and N second inputs of the corresponding N second multipliers th May ₁ -5 _N and N third inputs of the frequency offset calculating unit 9 outputs (N-1) second multipliers are connected to the (N-1) additional second inputs of the first adder 6, the second and third inputs additional frequency offset calculation unit 19 are respectively connected to with the first and second outputs of the complex multiplier 7, the second input of the block for determining the boundaries of the a priori interval and the fourth input of the additional frequency shift calculation unit 19 are combined and connected to the output of the clock generator 12, the first input of the control unit 11 and the third the input of the comparison unit 10 with the threshold is combined and connected to the first output of the unit for determining the boundaries of the a priori interval 25, the second and third outputs of which are connected respectively to the second and third inputs of the control unit 11, the fourth output of which is connected to the first input of the key 27, the second input of the key 27 is connected with the output of the second adder 17, and the output with the input of the comparator 28, the output of which is connected to the fourth input of the control unit 11, the second output of which is connected to the fifth input of the additional frequency shift calculation unit 19.

Block 23 calculating the correction coefficient of the power level of the generated input signal (Figure 4) contains the first 29 and second 30 registers, a key 31, a node for calculating the ratio of the gain of the input signal corresponding to the first exceeding the threshold of the first stage to the current value of the gain of the receiving path 32, the pulse shaper 33 and the NOT circuit 34, wherein the first inputs of the first register 29, the key 31, and the input of the node 32 are combined to form the first input of the block 23, the second input of the first register 29 is connected to the output of the pulse shaper 33, the input of which is combined with the input of the “NOT” circuit 34 and connected to the output of the second register 30, the first and second inputs of which are combined to form the second input of the block 23, the output of the “NOT” circuit 34 is connected to the second input of the key 31, the outputs of the key 31 and the first register 29 are connected to the second input of the node 32 for calculating the ratio of the gain of the input signal corresponding to the first excess of the threshold of the first stage to the current value of the gain of the receive path, the output of which is the output of the block 23 for calculating the level correction coefficient ti generated input signal.

Block 25 for determining the boundaries of the a priori interval (Fig. 5) contains series-connected first register 35, first key 36 and first counter 37, series-connected second register 38, second key 39 and second counter 40, series-connected third register 41, third key 42 and the third counter 43, while the first and second inputs of the first 35, second 38 and third 41 registers, the second inputs of the first 37, second 40 and third 43 counters are combined to form the first input of block 25, the second inputs of the first key 36, second key 39 and third key 42 combined Now, forming the second input of block 25, the output of the first counter 37 is the second output of block 25 and connected to the third input of the first register 35, the output of the second counter 40 is the second output of block 25 and connected to the third input of the second register 38, the output of the third counter 43 is the first the output of block 25 and is connected to the third input of the third register 41.

Block 10 comparison with the threshold (Fig.6) contains a series-connected register 44, the comparator 45 and the first key 46, the second key 47 and the third key 48, while the second input of the comparator 45 and the first input of the second key 47 are combined to form the first input of block 10 comparison with the threshold, the second input of the first key 46 forms the second input of block 10, the input of the third key 48 is the third input of block 10, the output of the first key 46 is the output of the comparison block 10 with a threshold and connected to the second input of the second key 47, the outputs of the keys 47 and 48 connected to the input of the register 44.

Unit 19 for calculating the additional frequency shift (Fig. 7) contains the first 49, second 50, third 51 and fourth 52 registers, node 53 for calculating the complex spectrum of the signal, node 54 for calculating the frequency shift, circuit 55 "OR", counter 56 and key 57, the inputs of the registers 49 and 50 respectively form the second and third inputs of the additional frequency shift calculation unit 19, the outputs of the registers 49 and 50 are connected respectively to the first and second inputs of the complex spectrum signal calculation unit 53, the third input of which is connected to the output of the OR circuit 55 first exit at la 53 is connected to the first inputs of the third register 51 and the frequency shift calculation unit 54, the second output of the node 53 is connected to the first input of the fourth register 52 and the second input of the frequency shift calculation unit 54, the third and fourth inputs of which are connected respectively to the outputs of the registers 51 and 52, the output of the frequency shift calculation unit 54 is the output of the additional frequency shift calculation unit 19, the fifth input of the frequency shift calculation unit 54 and the second input of the OR circuit 55 are combined and connected to the output of the counter 56, the input of which is connected to the output th key 57, the first and second inputs of which respectively form the first and fourth inputs of the additional frequency offset calculation unit 19, the input circuit 55 "OR" is the fifth input of block 19.

The control unit 11 (Fig. 8) contains the first 58 and second 59 of the "AND" circuit, the first 60 and second 61 of the "NOT" circuit, the OR circuit 62, the register 63 and the pulse shaper 64, while the first inputs of the first circuit 58 " AND ”and the second“ 59 ”circuits 59 are respectively the second and first inputs of the control unit 11, the input of the first“ NOT ”circuit 60 is the third input of the control unit 11, the second inputs of the first 58 and second 59“ I ”circuits are combined and connected to the output of the first circuit 60 "NOT", the output of the first circuit 58 "AND" is the fourth output of the control unit 11, the output of the second circuit 59 "AND" is connected to the first input of the OR circuit 62, the output of which is connected to the input of the second NOT circuit 61, the output of which forms the first output of the control unit 11, the first and second inputs of the register 63 form the fourth input of the control unit 11, the output of the register 63 is the third output of the block 11 control and connected to the combined second input of the OR circuit 62 and the input of the pulse shaper 64, the output of which forms the second output of the control unit 11 and, accordingly, the first output of the device.

Carry out the inventive method of time-frequency synchronization of a communication system as follows:

the input signal is filtered, amplified, automatic gain control is performed, calculating the gain of the input signal depending on the power level of the input signal, transfer to the video frequency, carry out its analog-to-digital conversion and decimation, forming the input digital complex signal at the video frequency;

- time-frequency synchronization is performed in two stages, while at the first stage, a preliminary estimate of the temporary position of the second part of the preamble and a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are determined, for which:

calculate the correction coefficient of the power level of the generated input signal,

correcting the generated input digital complex signal using the calculated correction coefficient of the power level of the generated input signal,

filtering the corrected input digital complex signal, consistent with one short multi-frequency symbol, forming complex responses of the first stage,

remember the complex responses of the first stage,

calculate the squares of the modules of the complex responses of the first stage,

calculate the sum of N squares of the modules of the complex responses of the first stage, taken with an interval equal to the duration of the short multi-frequency symbol,

compare the received amount with a given threshold of the first stage, if the threshold is exceeded:

the temporary position of the beginning of the preamble corresponding to the amount received is considered the current temporary position of the preamble,

,form the current estimate of the frequency shift by the averaged phase difference of adjacent complex responses of the first stage from the n-th to the (N-n + 1) -th corresponding to the summation terms, where n is an integer,

,

the threshold of the first stage is set equal to the received amount,

if at least one threshold is exceeded for the first stage, and then the threshold for the first stage is not exceeded from the time the last threshold was exceeded for an interval equal to the duration of the short multi-frequency symbol, then

determine a preliminary assessment of the temporary position of the second part of the preamble for the current temporary position of the preamble,

determining a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the current estimate of the frequency shift,

the threshold of the first stage is assumed to be equal to the initial value, and the current temporary position of the preamble is considered undefined;

go to the second stage,

- at the second stage, a final assessment of the temporal position of the preamble and a final assessment of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are carried out, for which:

determine the a priori interval of the temporary position of the second part of the preamble by preliminary estimation of the temporary position of the second part of the preamble,

adjust the phase of the input digital complex signal in the interval of operation of the second stage, taking into account a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal,

filtering the phase-corrected input digital complex signal, consistent with one long multi-frequency symbol, provides complex responses of the second stage,

calculate the squares of the modules of the complex responses of the second stage,

comparing the squares of the modules of the complex responses of the second stage with a given threshold of the second stage on an a priori interval of the time position of the second part of the preamble, if the threshold is not exceeded, the preamble is considered undetected,

when the threshold of the second stage is exceeded, the preamble is considered to be detected, then

determine the final assessment of the temporary position of the preamble by the temporary position of the first excess of the threshold of the second stage,

find complex spectra of long multi-frequency symbols of the phase-corrected input digital complex signal, the temporary positions of which are determined by the temporary position of the first threshold exceeding the second stage,

determining an additional estimate of the frequency shift from the average phase difference of the corresponding elements of the complex spectra of long multi-frequency symbols,

determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal as the sum of the preliminary and additional estimates of the frequency shift.

The generated input digital complex signal is corrected, for example, by multiplying by the ratio of the gain of the receive path, at which the first threshold of the first stage is exceeded, by the current gain of the receive path; if not a single excess of the threshold of the first stage has occurred, then the generated input digital complex signal is multiplied by a factor equal to unity.

A current estimate of the frequency shift is formed, for example, as the ratio of the averaged phase difference of the complex responses of the first stage to the duration of a short multi-frequency symbol.

The beginning of the a priori time interval of the temporal position of the second part of the preamble is determined, for example, by the sum of the preliminary estimate of the temporal position of the second part of the preamble, the duration of the (N-1) x short multi-frequency symbols and the duration of the prefix, where N is the number of short multi-frequency symbols in the preamble.

The end of the a priori time interval of the temporal position of the second part of the preamble is determined, for example, by the sum of the preliminary estimate of the temporal position of the second part of the preamble, the duration of (N + 2) -x short multi-frequency characters and the duration of the prefix, where N is the number of short multi-frequency characters in the preamble.

The phase of the input digital complex signal in the interval of operation of the second stage is adjusted by multiplying the samples of the input digital complex signal by a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the time positions of the samples.

An additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of the corresponding elements of the complex spectra of long multi-frequency symbols to the duration of a long multi-frequency symbol.

The final assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined equal to the difference in the temporary position corresponding to the first exceeding of the threshold of the second stage and the sum of the durations of the first part of the preamble and the prefix.

The inventive method is implemented on the device of the time-frequency synchronization of a communication system, a structural diagram of which is shown in Fig.3.

The preamble signal is used for time-frequency synchronization, which consists of two stages. In this case, at the first stage, a preliminary estimate of the temporary position of the second part of the preamble and a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are determined. At the second stage, a final estimate of the temporal position of the preamble and a final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are carried out.

In the receiving path 1, the input signal that is fed to its input is pre-filtered, amplified, and the gain is automatically adjusted, calculating the gain of the input signal depending on the input signal power level, transferred to the video frequency, and its analog-to-digital conversion, decimation, etc. .d. As a result, an input digital complex signal is generated at the video frequency.

The in-phase and quadrature components of the input digital signal from the first and second output of the receiving path 1 are respectively supplied to the first and second inputs of the complex multiplier 7 and, respectively, to the first inputs of the fifth 21 and sixth 22 multipliers.

The gain of the input signal or a value proportional to the gain (which change during the reception of the signal by the automatic gain control system) from the third output of the receive path 1 is fed to the first input of the power factor correction coefficient calculation unit 23 of the generated input signal, the second input of which a signal is received from the output of the comparison unit 10 with a threshold.

The calculated correction coefficient of the power level of the generated input signal from the output of block 23 is supplied to the second inputs of the fifth 21 and sixth 22 multipliers.

From the output of the fifth 21 and sixth 22 multipliers, the corrected in-phase and quadrature components of the input digital signal are fed to the inputs of the first 2 and second 3 matched filters.

In the first matched filter 2, the common-mode component of the input signal is matched with one short multi-frequency symbol. In the second matched filter 3, the quadrature component of the input signal is matched with one short multi-frequency symbol.

The outputs of the first 2 and second 3 matched filters generate correlation responses, respectively, for the in-phase and quadrature components of the input digital complex signal, which are received respectively at the inputs of the first 24 and second 25 delay lines for the in-phase and quadrature components of the signal.

In the first 24 and second 25 delay lines, responses for the in-phase and quadrature components with a discrete, for example, equal to the ratio of the duration of the short multi-frequency symbol to the number of subcarriers in the duration interval N of short multi-frequency symbols, are stored (recorded), respectively. Each delay line, respectively, for in-phase and quadrature components has N outputs.

In the first 4 ₁ -4 _N and second 5 ₁ -5 _N multipliers, the squares of the corresponding responses for the in-phase and quadrature components of the first stage are calculated, which are fed to the corresponding first and second inputs of the first adder 6.

In the first adder 6, by summing the corresponding squares of the in-phase and quadrature components of the responses, the sum of N squares of the modules of the complex responses of the first stage, taken at intervals equal to the duration of the short multi-frequency symbol, which are received at the first input of the comparison unit 10 with a threshold, is calculated. At the second input of the comparison unit 10 with a threshold from the first output of the control unit 11, a control signal is supplied that determines the moment of completion or restart of the first stage. At the third input of the comparison threshold unit 10 and the first input of the control unit 11, from the first output of the a priori interval boundary determination unit 25, a threshold signal of the first stage is not exceeded for the duration of the short multi-frequency symbol (after the last threshold of the first stage is exceeded), according to which the initial ( initial) threshold value of the first stage. This setting is necessary to start the next cycle of the first phase of synchronization.

To the second input of the control unit 11 from the second output of the unit for determining the boundaries of the a priori interval 25, a signal of the beginning of the a priori time interval of the second position of the preamble is supplied.

In block 10, the comparison with the threshold sequentially compares the results of the summation from the output of the first adder 6 with the threshold of the first stage H1. The comparison results from the output of the comparison threshold unit 10 are sent to the first input of the a priori interval boundary determining unit 25, to the first input of the frequency shift calculation unit 9 and to the second input of the power level correction coefficient calculation unit 23 of the generated input signal.

If the threshold of the first stage is exceeded:

the current temporary position of the preamble is considered the temporary position of the beginning of the preamble corresponding to the result of the summation;

in the block 9 calculation of the frequency shift form the current estimate of the frequency shift;

in block 25 for determining the boundaries of the a priori interval, the beginning of the a priori interval of the time position of the second part of the preamble and the end of the a priori interval of the time position of the second part of the preamble are determined;

the current estimate of the frequency shift is formed in the block 9 for calculating the frequency shift by the average phase difference of the complex responses of the first stage, arriving at the second and third inputs of block 9.

The averaged phase difference is formed, for example, as the sum of the products of complex responses to complex conjugate neighboring responses. Moreover, the (n-1) initial and (n-1) last correlation responses are not used in the formation of the sum. The value of the argument of the obtained complex number is equal to the averaged phase difference. In this case, the ratio of the averaged phase difference to the duration of a short multi-frequency symbol is equal to the estimate of the current frequency shift.

An estimate of the current frequency shift is received from the output of block 9 to the first input of the harmonic generation block 8 and to the first input of the third adder 20 and corresponds to the current preliminary (“rough”) estimate of the frequency detuning. At the second input of the harmonics generation unit 8, at the second input of the a priori interval boundary determination unit 25 and at the fourth input of the additional frequency shift calculation unit 19, the clock signal is output from the output of the clock generator 12.

The beginning of the a priori interval of the time position of the second part of the preamble is determined in block 25 for determining the boundaries of the a priori interval, for example, equal to the sum of the preliminary estimate of the time position of the second part of the preamble corresponding to the last excess of the threshold of the first stage (after which there was no excess of the threshold of the first stage for a short multi-frequency symbol), duration (N-2) of short multi-frequency symbols, and prefix duration. Starting from the beginning of the a priori time interval of the second part of the preamble, a signal equal, for example, to a logical unit, from the second output of the a priori interval boundary determination unit 25 is supplied to the second input of the control unit 11.

The end of the a priori interval of the time position of the second part of the preamble is determined in block 25 for determining the boundaries of the a priori interval, for example, equal to the sum of the preliminary estimate of the time position of the second part of the preamble, the duration of (N + 2) -x short multi-frequency symbols and the duration of the prefix. The signal for the end of the a priori interval comes from the third output of the block for determining the boundaries of the a priori interval 25 to the third input of the control unit 11.

After each exceeding the threshold of the first stage, its value is set in block 10 comparing with the threshold equal to the result of the summation in the first adder 6.

By the time the second stage begins, in the frequency shift calculation unit 9, a preliminary estimate of the frequency shift between the input signal carrier and the reference signal frequency is formed, which is equal to the last current frequency shift estimate.

In block 8, the formation of harmonics according to a preliminary estimate of the frequency shift and the signal from the clock generator 12 form a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the temporary position of the current samples. The quadrature components of the complex factor from the first and second outputs of the harmonic generation unit 8 are respectively supplied to the third and fourth inputs of the complex multiplier 7, in which the phase of the input digital complex signal is corrected in the second stage. To do this, in the complex multiplier 7 carry out the well-known operation of multiplying the samples of the input digital complex signal by a complex factor.

At a point in time corresponding to not exceeding the threshold of the first stage, for the duration of the short symbol (after the last exceeding the threshold of the first stage), in the block 10 comparing with the threshold, the threshold of the first stage is set equal to the initial value H1. From this moment in time, the second stage begins, during which the final estimate of the temporal position of the preamble and the final estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal are carried out.

In the interval of operation of the second stage in the complex multiplier 7, the phase of the input digital complex signal is constantly adjusted taking into account a preliminary estimate of the frequency shift between the carrier of the input signal and the frequency of the reference signal obtained in the first stage.

The in-phase and quadrature components of the input digital complex signal, phase-corrected, from the first and second outputs of the complex multiplier 7 are received respectively at the inputs of the third 13 and fourth 14 matched filters and, respectively, at the second and third inputs of the additional frequency shift calculation unit 19.

In the third 13 and fourth 14 matched filters, matched filtering is performed with one long multi-frequency symbol, respectively, for the in-phase and quadrature components of the input phase-corrected digital complex signal and the in-phase and quadrature components of the responses of the second stage are formed respectively. The generated in-phase components of the responses of the second stage from the output of the third matched filter 13 are supplied to the first and second inputs of the third multiplier 15. The generated quadrature components of the responses of the second stage from the output of the fourth matched filter 14 are fed to the first and second inputs of the fourth multiplier 16.

In the third 15 and fourth 16 multipliers, respectively, the squares of the in-phase and quadrature components of the responses of the second stage are formed, which arrive respectively at the first and second input of the second adder 17, where by summing them up, the squares of the modules of the complex responses of the second stage are calculated.

The calculated squares of the second-stage complex response modules from the output of the second adder 17 go to the second input of the key 27. The control signal is equal to, for example, a logical unit if the current time delay is inside the a priori time interval from the fourth output of control unit 11 provisions of the second part of the preamble. From the output of the key 27, the squares of the complex response modules of the second stage are fed to the input of the comparator 28.

In the comparator 28 for the time delays on the a priori time interval of the second position of the preamble, the squares of the modules of the complex responses of the second stage are compared with the threshold of the second stage H2. The comparison result from the output of the comparator 28 is fed to the fourth input of the control unit 11.

If the threshold H2 is not exceeded in the a priori time interval of the second part of the preamble, the preamble is assumed to be undetected, the first stage restart signal is generated at the first output of the control unit 11, which is fed to the second input of the comparison unit 10 with a threshold, and the time-frequency synchronization procedure is repeated starting from the first stage.

If the threshold H2 is exceeded (at least once) in the a priori interval of the time position of the second part of the preamble, the preamble is considered to be detected. Moreover, the signals for exceeding the threshold in the control unit 11 determine the final assessment of the temporary position of the preamble as the temporary position of the first excess of the threshold of the second stage H2. The resulting estimate from the second output of the control unit 11 is fed to the first output of the device and to the fifth input of the additional frequency shift calculation unit 19.

The final assessment of the temporal position of the preamble (the beginning of the preamble) is uniquely determined by the temporal position of the first exceeding the threshold of the second stage H2 and is equal to the difference between the temporal position of the first exceeding the threshold of the second stage H2 and the sum of the durations of the first part of the preamble and prefix.

In the block 19 for calculating the additional frequency shift, the time position corresponding to the first and second outputs of the control unit 11 is determined from the control signal of the presence of a threshold threshold exceeding the second stage and the control signal corresponding to the temporary position of the second threshold threshold exceeding, respectively long multi-frequency symbols. The time moment of the first exceeding the threshold of the second stage corresponds to the end of the first multi-frequency symbol and the beginning of the second multi-frequency symbol.

In block 19 for calculating the additional frequency shift, the in-phase and quadrature components of the input digital complex signal, corrected for the phase of the first and second long multi-frequency symbols, are used to determine an additional estimate of the frequency shift.

Evaluation is performed, for example, as follows. Complex spectra of two long multi-frequency symbols are formed, then the average phase difference of the corresponding elements of the complex spectra is found as the sum of the products of the complex conjugate elements of the first symbol and the corresponding complex spectrum elements of the second symbol. As a result, the argument of the obtained complex number is equal to the averaged phase difference and determines the estimate of the additional phase shift. An additional estimate of the frequency shift is determined, for example, as the ratio of the averaged phase difference of the elements of complex spectra to the duration of a long multi-frequency symbol. An additional estimate of the frequency shift from the output of block 19 goes to the second input of the third adder 20.

In the third adder 20, the final estimate of the frequency shift between the input carrier and the frequency of the reference signal is determined as the sum of the preliminary and additional estimates of the frequency shift. The resulting final assessment from the output of the third adder 20 is fed to the second output of the device.

For a better understanding of the implementation of the inventive method of time-frequency synchronization of a communication system and a device for its implementation, we consider the operation of the block 23 for calculating the correction coefficient of the power level of the generated input signal, the block 10 for comparing with a threshold, the block 25 for determining the boundaries of the a priori interval, the block 19 for calculating the additional frequency shift and control unit 11.

Block 23 calculating the coefficient of correction of the power level of the generated input signal (Figure 4) works as follows.

The first input of block 23 receives the gain (or a value proportional to it) from the output of the receiving path 1. From the first input of block 23, the signal is supplied to the combined first inputs of the first register 29, key 31, and the node for calculating the ratio of the gain of the input signal corresponding to the first excess the threshold of the first stage, to the current value of the gain of the receiving path 32.

From the second input of block 23, the signal of the comparison result with a predetermined threshold of the first stage H1 is received at the first signal input and at the second recording input of the second register 30, according to which, if there is at least one excess, a signal equal to a logical one is written to the second register 30. The output of the second register 30 is connected to the input of the pulse shaper 33 and the input of the circuit 34 "NOT". The output signal from the second register 30 at the output of the pulse shaper 33 generates a signal in the form of a pulse, the temporary position of which corresponds to the first excess of the threshold of the first stage. According to this signal, the value of the gain of the receiving path is stored in the first register 29. From the output of the first register 29, the value of the gain of the receive path corresponding to the first excess of the threshold of the first stage is fed to the input of the node 32 for calculating the ratio of the gain of the input signal corresponding to the first excess of the threshold of the first stage to the current value of the gain of the receive path. From the output of node 32, the calculated correction coefficient for the power level of the generated input signal is sent to the output of block 23. If the threshold of the first stage was not exceeded, a ratio equal to unity is generated in node 32, because in this case, the key 31 is closed (there is no signal from the output of the first register 29), and at the node 32 the dividend and divisor are equal.

An embodiment of block 25 for determining the boundaries of the a priori interval is shown in FIG. 5. Block 25 operates as follows.

In the first arm containing the first register 35, the first key 36, and the first counter 37, a signal of the beginning of the region of the a priori interval of the second stage is generated. In the second arm containing the second register 38, the second key 39 and the second counter 40, the end signal of the region of the a priori interval of the second stage is generated. In the third arm, which contains the third register 41, the third key 42 and the third counter 43, a threshold is not exceeded during the interval of the short symbol (after the last threshold is exceeded in the first stage).

The first and second inputs of the first 35, second 38 and third 41 registers and the second inputs of the first 37, second 40, third 43 counters receive a comparison signal with the threshold of the first stage.

From the output of the first counter 37 (beginning) to the third input of reset (zeroing) of the first register 35 and to the second output of block 25, a signal equal to logical zero until the start of the a priori interval of the second stage and equal to logical unit otherwise is received.

The third reset input (reset) of the second register 38 and the third output of block 25 from the output of the second counter 40 (end) receives a signal equal to logical zero until the end of the a priori interval of the second stage, and equal to a logical unit in the opposite case.

The third reset input (reset) of the third register 41 and the first output of block 25 from the output of the third counter 43 (end) receives a signal equal to logical zero until the time corresponding to not exceeding the threshold of the first stage for a short symbol (after the last exceeding of the threshold of the first stage ) and equal to a logical unit in the opposite case.

When the threshold of the first stage is exceeded, in the first 35, second 38 and third 41 registers record a signal equal to a logical unit, which from the outputs of the first 35 and second 38 and third 41 registers goes to the first controlled inputs of the first 37, second 40 and third 43 keys, respectively. The second inputs of the first 37, second 40 and third 43 keys from the second input of block 25 receives a signal from the clock generator, which through the first key 36 is fed to the input of the first counter 37, through the second key 39 - to the first input of the second counter 40, and through the third the key 42 is supplied to the first input of the third counter 43.

When the threshold of the first stage is exceeded, the first key 36 closes and the first counter 37 accumulates clock pulses. It is programmed in such a way that the signal of the beginning of the a priori time interval of the second part of the preamble, equal to a logical unit, appears at its output at a point in time equal, for example, to the sum of the temporary position of the preamble corresponding to exceeding the threshold of the first stage, the duration of (N-2) short multi-frequency characters and prefix duration.

The signal of the beginning of the a priori time interval of the second part of the preamble, equal to a logical unit, from the output of the first counter 37 goes to the second output of block 25 and to the third input of the first register 35, by which the first register 35 is reset.

Each time the threshold of the first stage is exceeded, a signal equal to a logical unit is supplied to the reset inputs of all counters, as a result, they are reset.

It should be noted that each subsequent excess of the threshold of the first stage corresponds to a greater response of the first stage. Therefore, the last excess of the threshold of the first stage for the proposed reception procedure determines the greatest response of the first stage. The temporary position of this response in the proposed procedure is used to form an a priori interval of the temporary position of the second part of the preamble. Ultimately, the procedure for determining the a priori time interval of the second part of the preamble is to determine the time position of the highest response of the first stage.

The proposed procedure for resetting counters by a signal that exceeds the threshold of the first stage ensures the formation of output signals according to the temporary position of the highest response of the first stage.

The second counter 40 is programmed in such a way that the signal for the end of the a priori time interval of the second part of the preamble, equal to a logical unit, appears at its output at a point in time equal, for example, to the sum of the temporary position of the preamble corresponding to exceeding the threshold of the first stage, duration (N + 2) -x short multi-frequency characters and prefix durations.

The signal for the end of the a priori time interval of the second preamble’s second position, equal to a logical one, from the output of the second counter 40 is fed to the third output of block 25 and to the third input of the second register 38. This signal is used to reset the second register 38 and complete the procedure for generating the a priori time interval of the second parts of the preamble.

The third counter 43 is programmed in such a way that a threshold non-exceeding signal equal to a logical one appears at its output at a time instant equal, for example, to the sum of the current temporary position of the preamble, the duration of one short multi-frequency symbol.

The signal does not exceed the threshold during the interval of a short symbol (after the last threshold is exceeded in the first stage), equal to a logical unit, from the output of the third counter 43 is fed to the first output of block 25 and to the third input of the third register 41. This signal is used to reset the third register 41.

The first 37, second 40 and third 43 counters can be implemented, for example, on the basis of standard programmable counters such as 564IE10 or the like.

Consider the operation of block 10 comparison with the threshold, a structural diagram of which is shown in Fig.6.

The second controlled input of the first key 46 from the second input of the comparison unit 10 with a threshold receives a control signal that determines the moment of completion or restart of the first synchronization stage. The first controlled input of the third key 48 from the third input of block 10 receives a signal for not exceeding the threshold during the interval of a short symbol (after the last threshold of the first stage is exceeded).

Preliminarily, when the receiving device is turned on, a signal equal to a logical unit is set to the second controlled input of the first key 46, by which the first key 46 is opened (closed), and the threshold is exceeded from the output of the comparator 45 through the first key 46 to the output of the comparison unit 10 with the threshold and to the second controlled input of the second key 47. Previously, the initial threshold value of the first stage H1 is recorded in the register 44. At the second controlled input of the third key 48, a signal is set equal to logical zero, by which this key is closed (open). The signal from the output of the third key 48 or the signal from the output of the second key 47 goes to the input of the register 44, is stored in it and from the output of the register 44 goes to the first input of the comparator 45.

The first input of the second key 47 and the second input of the comparator 45 from the first input of block 10 receives the squares of the complex response modules of the first stage, which are compared in the comparator 45 with the threshold of the first stage.

When the threshold is exceeded, the output of the comparator 45 generates a signal equal to a logical unit, which, through the first key 46, enters the output of the comparison unit 10 with the threshold and the second controlled input of the second key 47. By this signal, the square of the module of the current complex response through the second key 47 is transmitted to the input of the register 44 is stored in it and from its output goes to the first input of the comparator 45 as the value of the current threshold of the first stage, and the comparison procedure with the threshold is repeated.

The comparison procedure with the threshold ends at the moment the first key 46 of the control signal arrives at the second controlled input, which determines the moment of completion or restart of the first stage (logical zero). In this case, the first key 46 is blocked (open).

The signal does not exceed the threshold during the interval of a short symbol (after the last threshold of the first stage is exceeded) (logical unit), which is fed to the first controlled input of the third key 48, and a signal equal to the initial value of the threshold of the first stage H1 (stored inside the block), and stored in the register 44.

Block 19 calculation of the additional frequency shift (Fig.7) works as follows.

The input of the first register 49 from the second input of block 19 receives the in-phase components of the input corrected digital signal.

The input of the second register 50 from the third input of block 19 receives the quadrature components of the input corrected digital signal.

The first input of the OR circuit 55 and the second inputs of the registers 51 and 52 from the fifth input of the block 19 receive a pulse signal of the first exceeding the threshold of the second stage.

The first input of the key 57 from the fourth input of the block 19 receives a pulse signal of the clock frequency. From the output of the key 57 to the input of the counter 56 receives a clock signal. The second controllable key input from the first input of block 19 receives a signal of the presence of exceeding the threshold of the second stage.

The first 49 and second 50 registers (with serial input and parallel output) store in-phase and quadrature components of the samples of the input digital signal in the interval of a long multi-frequency symbol.

The signal exceeding the threshold of the second stage in the node 53 for calculating the complex spectrum of the signal performs the Fourier transform of the signal recorded in the registers (which corresponds to the first long multi-frequency symbol), and store the result of the conversion in the third 51 and fourth 52 registers.

At the second input of the key 57, a signal equal to a logical unit arrives if there was at least one excess of the threshold in the a priori interval of the time position of the second part of the preamble. According to this signal, from the output of the key 57 to the (counting) input of the counter 56, a clock signal is received, which accumulates in it. The counter 56 is programmed in such a way that a pulse signal is generated at its output with a period equal to the duration of a long multi-frequency symbol. The Fourier transform of the signal recorded in registers 49 and 50 (which corresponds to the second long multi-frequency symbol) is performed by this signal in the complex spectrum signal calculation unit 53, and the frequency shift is calculated.

According to the output signal of the counter 56, in the node 54 for calculating the frequency shift of the M common-mode and quadrature components of the first (stored in the third and fourth registers) and second spectra of long symbols (at the outputs of the node 53 for calculating the complex signal spectrum), the procedure for calculating the frequency detuning estimate w in according to the expression:

where Lδ is the duration of a long multi-frequency symbol,

- комплексные элементы спектра первого символа,U _k = Uc _k + jUs _k ,

- complex elements of the spectrum of the first symbol,

- соответственно синфазные и квадратурные составляющие элементов спектра первого символа,Uc _k , Us _k ,

- respectively, in-phase and quadrature components of the spectrum elements of the first symbol,

- комплексные элементы спектра второго символа,Y _k = Yc _k + jYs _k ,

- complex elements of the spectrum of the second symbol,

- соответственно синфазные и квадратурные составляющие элементов спектра второго символа,Yc _k , Ys _k ,

- respectively, in-phase and quadrature components of the spectrum elements of the second symbol,

(*) - complex conjugation operation.

The obtained additional estimate of the frequency detuning w from the output of the frequency shift calculation unit 54 is supplied to the output of the additional frequency shift calculation unit 19.

Registers 49, 50 with sequential recording and parallel reading are implemented, for example, on the basis of standard microcircuits of the 561PR1 series or 1564IR8 series, or the like.

Registers 51 and 52 with parallel writing and parallel reading are implemented, for example, on the basis of standard 561IR6 series microcircuits or the like.

The counter 56 can be performed, for example, on the basis of standard microcircuits of the type 564IE10 or the like.

The control unit 11 for the inventive device, the structural diagram of which is made in Fig. 8, operates as follows.

From the second input of the control unit 11 to the first input of the first circuit 58 "And" receives the signal of the beginning of the a priori interval of the temporary position of the second part of the preamble.

From the third input of the control unit 11, the signal of the end of the a priori time interval of the time position of the second part of the preamble is supplied to the first input of the first “NOT” circuit 60. The inverse signal of the end of the a priori time interval of the second part of the preamble from the output of the first "60" circuit is supplied to the second input of the first "58" circuit and to the second input of the second "59" circuit. The control signal from the output of the first circuit And 58, equal, for example, to a logical unit, if the current time delay is inside the a priori time interval of the second position of the preamble, is fed to the fourth output of the control unit 11.

From the fourth input of the control unit 11, the signal of the comparison result with a predetermined threshold of the second stage H2 is received at the first signal input and at the second input of the register register 63, according to which, if there is at least one excess, a signal equal to a logical unit is recorded in register 63. The signal from the output of the register 63 is fed to the second input of the OR circuit 62, to the input of the pulse shaper 64 and to the third output of the control unit 11.

At the output of register 63, a signal equal to a logical unit is generated if there was at least one excess of the threshold of the second stage.

The output signal from the register 63 at the output of the pulse shaper 64 forms an estimate of the temporary position of the first threshold exceeding the second stage H2 in the form of a pulse, the temporary position of which corresponds to the first exceeding the threshold of the second stage or the beam signal with the least time delay. The output of the pulse shaper 64 is the second output of the control unit 11.

From the first input of the control unit 11, the signal, for example, equal to a logical unit, is received at the first input of the second AND circuit 59, if at least one threshold is exceeded for the first stage, and then the threshold for the first stage is not exceeded from the time the last threshold was exceeded during an interval equal to the duration of a short multi-frequency symbol.

The control signal from the output of the second AND circuit 59, for example, equal to a logical unit if the current time delay is inside the interval between the time corresponding to the threshold of the first stage not exceeding the duration of the short multi-frequency symbol and the time position of the end of the a priori time interval of the second part of the preamble, is fed to the first input of the OR circuit 62.

At the output of the OR circuit 62, a signal is generated that is equal to a logical unit if there was at least one excess of the threshold of the second stage or if the current time delay is within the interval between the time corresponding to the non-exceeding of the threshold of the first stage during the duration of a short multi-frequency symbol and the time the end position of the a priori time interval of the second part of the preamble, or if both of these conditions are observed simultaneously. Otherwise, the signal at the output of the OR circuit 62 is logic zero. The signal from the output of the circuit 62 "OR" is fed to the input of the second circuit 61 "NOT".

The output of the second circuit 61 "NOT" form a control signal that determines the moment of completion or restart of the first stage. The output of the second NOT circuit 61 is the first output of the control unit 11.

The pulse generator 64 can be implemented in the form of a well-known single-pulse generator based on, for example, a standard microcircuit (trigger) 564TM2 or similar.

The claimed group of inventions is a method of time-frequency synchronization of a communication system and a device for its implementation, created in a single inventive concept, in comparison with the known technical solutions in the art has the following advantages: the temporal position of the preamble signal is evaluated in two stages, and in the first at the stage they form the decisive function with a wide useful response, which increases the probability of the correct detection of the preamble signal, at the second stage they form the decisive a function with a narrow useful response that allows you to get an accurate estimate of the temporal position of the preamble signal; the frequency shift estimate is also formed in two stages, and the quality of this estimate is high, because it is based on a qualitative estimate of the temporal position of the signal. Another distinguishing feature of the invention is the ability to synchronize at relatively large initial values of the frequency shift, which is not available to many known methods of time-frequency synchronization.

The proposed invention significantly increase the noise immunity of the time-frequency synchronization of the communication system and expand the scope of its applicability.

Claims (9)

1. The method of time-frequency synchronization of a communication system, namely, that the input signal is filtered, amplified, automatic gain control is performed, calculating the gain of the input signal depending on the power level of the input signal, transferred to the video frequency, carry out its analog-to-digital conversion and decimation, forming an input digital complex signal at a video frequency, time-frequency synchronization is performed in two stages: at the first stage, a preliminary estimate of the frequency shift is determined hectare between the carrier frequency of the input signal and the frequency of the reference signal, at the second stage, the temporal position of the preamble and the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal are estimated, for which the phase of the input digital complex signal is adjusted at the interval of operation of the second stage, taking into account the preliminary estimates of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal, carry out consistent with one long multi-frequency symbol filtering the phase-corrected input digital complex signal, forming the complex responses of the second stage, calculate the squares of the modules of the complex responses of the second stage, compare with the given threshold of the second stage, if the threshold is not exceeded, the preamble is considered undetected, if the threshold is exceeded, the preamble is detected, then the estimate is determined the temporary position of the preamble according to the temporary position of the first exceeding the threshold of the second stage, determine an additional estimate of the frequency the first shift by the phase difference of the complex responses of the second stage, determine the final estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal, as the sum of the preliminary and additional estimates of the frequency shift, characterized in that when performing the first stage of the time-frequency synchronization, a preliminary estimate of the time the provisions of the second part of the preamble, for which the power factor correction factor of the generated input signal is calculated, the generated the input digital complex signal, using the calculated correction coefficient of the power level of the generated input signal, filter the adjusted input digital complex signal, consistent with one short multi-frequency symbol, forming complex responses of the first stage, calculate the sum of N squares of the complex modules of the complex responses of the first stage, taken at an interval equal to the duration of a short multi-frequency symbol, compare the received amounts with a given threshold of the first stage, if exceeded At the threshold value, the temporal position of the beginning of the preamble corresponding to the sum obtained is assumed to be the current temporal position of the preamble, form the current estimate of the frequency shift by the averaged phase difference of the adjacent complex responses of the first stage from the n-th to (M-n + 1) -th corresponding to the summation terms, where n is an integer and N is the number of short multi-frequency symbols in the preamble,

, the threshold of the first stage is set equal to the sum obtained, if at least one excess of the threshold of the first stage occurs, and then the threshold of the first stage is not exceeded from the time of the last threshold exceeding during the interval equal to the duration of the short multi-frequency symbol, then a preliminary estimate of the temporal position of the second parts of the preamble according to the current temporary position of the preamble, a preliminary estimate of the frequency shift between the carrier frequency of the input signal and the frequency of the reference signal divided as the current estimate of the frequency shift, the threshold of the first stage is assumed to be equal to the original value, and the current temporary position of the preamble is considered undefined; at the second stage, the final assessment of the temporal position of the preamble is carried out, for which a priori time interval of the temporal position of the second part of the preamble is determined by preliminary estimation of the temporal position of the second part of the preamble, the squares of the complex response modules of the second stage are compared with a predetermined threshold of the second stage on the a priori interval of the temporal position of the second part of the preamble, according to the temporary position of the first excess of the threshold of the second stage, the assessment of the temporary position of the preamble is determined as final, n complex spectra of long multi-frequency symbols of the phase-corrected input digital complex signal are found, the temporal positions of which are determined by the temporal position of the first threshold exceeding the second stage, an additional estimate of the frequency shift is determined by the averaged phase difference of the corresponding elements of the complex spectra of long multi-frequency symbols. 2. The method according to claim 1, characterized in that the generated digital complex signal is corrected by multiplying by the ratio of the gain of the receive path, at which the first threshold of the first stage is exceeded by the current gain of the receive path; if not a single excess of the threshold of the first stage has occurred, then the generated input digital complex signal is multiplied by a factor equal to unity. 3. The method according to claim 1, characterized in that the current frequency shift estimate is formed as the ratio of the average phase difference of the complex responses of the first stage to the duration of a short multi-frequency symbol. 4. The method according to claim 1, characterized in that the beginning of the a priori time interval of the second part of the preamble is equal to the sum of the preliminary estimate of the temporary position of the second part of the preamble, the duration of (N-2) -x short multi-frequency characters and the duration of the prefix, where N is the number short multi-frequency characters in the preamble. 5. The method according to claim 1, characterized in that the end of the a priori time interval of the second part of the preamble is equal to the sum of the preliminary estimate of the temporary position of the second part of the preamble, the duration of (N + 2) -x short multi-frequency characters and the duration of the prefix, where N is the number short multi-frequency characters in the preamble. 6. The method according to claim 1, characterized in that the phase of the input digital complex signal in the interval of operation of the second stage is adjusted by multiplying the samples of the input digital complex signal by a complex factor of unit amplitude, the phase of which is equal to the product of the preliminary estimate of the frequency shift by the temporal positions of the samples. 7. The method according to claim 1, characterized in that the additional estimate of the frequency shift is defined as the ratio of the average phase difference of the corresponding elements of the complex spectra of long multi-frequency symbols to the duration of a long multi-frequency symbol. 8. The method according to claim 1, characterized in that the final assessment of the temporary position of the preamble, namely the beginning of the preamble, is determined equal to the difference in the temporary position corresponding to the first excess of the threshold of the second stage and the sum of the durations of the first part of the preamble and prefix. 9. A frequency-time synchronization device for a communication system, comprising a receiving path that generates an input digital complex signal at a video frequency, first and second matched filters, filtering, respectively, in-phase and quadrature components of the generated digital complex signal, matched with one short multi-frequency symbol, forming complex responses of the first stage, first and second multipliers, first adder, complex multiplier, harmonic generation unit Onics, a frequency shift calculation unit, a threshold comparison unit, a control unit, a clock generator that generates a clock signal at the output, the third and fourth matched filters that filter the phase-corrected input complex digital signal matched to one long multi-frequency symbol, forming complex responses the second stage, the third and fourth multipliers, the second adder, the unit for calculating the additional frequency shift and the third adder, while the input of the receiving path is are the input of the device, the first and second outputs of the receiving path are connected respectively to the first and second inputs of the complex multiplier, the outputs of the first and second multipliers are connected respectively to the first and second inputs of the first adder, the output of which is connected to the first input of the comparison unit with a threshold, the second input of which is connected with the first output of the control unit, the output of the comparison unit with a threshold is connected to the first input of the frequency shift calculation unit, the output of which is connected to the first input of the harmonic formation unit the first input of the third adder, the second input of the harmonic generation unit is connected to the output of the clock generator, the first and second outputs of the harmonic generation unit are connected respectively to the third and fourth inputs of the complex multiplier, the first and second outputs of which are connected respectively to the inputs of the third and fourth matched filters, the output of the third matched filter is connected to the first and second inputs of the third multiplier, the output of the fourth matched filter is connected to the first and second by the strokes of the fourth multiplier, the outputs of the third and fourth multipliers are connected respectively to the first and second inputs of the second adder, the second output of the control unit is the first output of the device, which generates an estimate signal for the temporary position of the preamble at this output, the third output of the control unit is connected to the first input of the additional calculation unit the frequency shift, the output of which is connected to the second input of the third adder, forming the output signal of the final assessment of the frequency shift, the third output about the adder is the second output of the device, characterized in that the fifth and sixth multipliers are added to correct the power level of the generated input signal, the block calculates the power level correction factor of the generated input signal, the first and second delay lines, (N-1) first and (N -1) of the second multipliers, a block for determining the boundaries of the a priori interval, which generates at the first output a signal for not exceeding the threshold of the first stage from the time of the last exceeding of the threshold for an interval equal to duration of the short multi-frequency symbol, at the second output is the signal of the beginning of the a priori time interval of the second part of the preamble, at the third output is the signal of the end of the a priori time interval of the second position of the preamble, key, comparator, while the first output of the receive path is connected to the first input of the fifth multiplier, the second output of the receiving path is connected to the first input of the sixth multiplier, the third output of the receiving path is connected to the first input of the block for calculating the power level correction coefficient the generated input signal, the second input of which is combined with the first input of the block determining the boundaries of the a priori interval and is connected to the output of the comparison unit with a threshold, the output of the block for calculating the power level correction coefficient of the generated input signal is connected to the second inputs of the fifth and sixth multipliers, the output of the fifth multiplier is connected to the input the first matched filter filtering the adjusted input digital complex signal, the output of the first matched filter soy inen with the input of the first delay line, the output of the sixth multiplier is connected to the input of the second matched filter, the output of which is connected to the input of the second delay line, N outputs of the first delay line are connected to their respective N first and N second inputs of the corresponding N first multipliers and N second inputs of the frequency shift calculation unit, the outputs (N-1) of the first multipliers are connected to (N-1) additional first inputs of the first adder, N outputs of the second delay line are connected to their respective N first and N second by the first inputs of the corresponding N second multipliers and N by the third inputs of the frequency shift calculator, the outputs (N-1) of the second multipliers are connected to (N-1) by the additional second inputs of the first adder, which generates the sum of N squares of the complex response modules of the first stage, the second and the third inputs of the block for calculating the additional frequency shift are connected respectively to the first and second outputs of the complex multiplier, the second input of the block for determining the boundaries of the a priori interval, and the fourth input of the block for calculating the additional frequency shift are combined and connected to the output of the clock generator, the first input of the control unit and the third input of the comparison unit with a threshold are combined and connected to the first output of the unit for determining the boundaries of the a priori interval, the second and third outputs of which are connected respectively to the second and third inputs of the control unit forming at the first output, a control signal that determines the moment of completion or restart of the first stage; at the third, a signal of the presence of at least one second threshold about the stage, at the fourth output - a control signal that determines the time interval when the current time delay is inside the a priori time interval of the second part of the preamble, the fourth output of the control unit is connected to the first input of the key, the second input of the key is connected to the output of the second adder, and the output is with the input of the comparator, the output of which is connected to the fourth input of the control unit, the second output of which is connected to the fifth input of the unit for calculating the additional frequency shift.

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