RU2352061C1 - Differential comparator with sample of input signal - Google Patents

Abstract

FIELD: physics; electronics.

SUBSTANCE: invention can be used in microelectronic systems of processing of analogue signals and transformations of analogue information in digital, in particular, in high-speed analogue-digital transformers (ADT). The voltage comparator (VC) includes device of sample-storage of input signal (SSD) on switched condensers with unitary or double sample and, at least, one differential amplifier (DA) with a pair of input MOS transistors of the first type with the general source connected to cell, and sinks connected to drains of first and second pairs of MOS transistors of the second type and forming differential DA exits, and between shutters of first pair of MOS transistors of the second type and the general busbar of sources of first and second pair of MOS transistors of the second type the pair of condensers is included, shutters of second pair of MOS transistors of the second type are connected crosswise to the drains of opposite transistors of pair, forming the plus feedback, and DA differential exits are shunted with MOS key. DA works with alternating stages of zeroing and comparison, and the stage of zeroing DA comes to end after the moment of sample of the SSD input signal with cutout of shutters of the first pair of transistors of the second type from the drains then the DA source increases current, at least, on response time of the plus feedback of the second MOS pair of transistors of the second type. The MOS key shunts differential DA exits only for the period of switching SSD from sample phase in phase of comparison and formation on the DA inlets of signal of sufficient amplitude.

EFFECT: speed and accuracy increase, reduction of consumption and power of differential voltage comparators with sample of differential input signal.

10 cl, 8 dwg

Description

The invention relates to electronics and can be used in microelectronic systems for processing analog signals and converting analog information to digital, and in particular, in high-speed analog-to-digital converters (ADCs).

The purpose of the invention is to increase the speed and accuracy, as well as reducing the power consumption of high-speed differential voltage comparators (KH) with a sample of the input differential signal.

There are many schemes of high-speed differential VF, but far from all high-speed differential VFs satisfy the following set of requirements:

but. use auto-correction of zero offset to increase accuracy;

b. using a sample of the input signal with a known aperture delay and low temporal noise or jitter (jitter) of the sampling time;

from. provide a comparison of the differential input signal with the differential reference voltage;

d. provide operability and accuracy in a wide range of input signal voltages at low supply voltages.

The specified set of requirements for the SC is necessary to ensure high speed and accuracy of modern parallel (flash), conveyor (pipeline), and combined multi-stage (subranging) ADCs.

Autocorrection of zero bias is necessary to minimize the conversion error in high-bit ADCs when using small sizes of elements (transistors) in the SC, which increase the SC zero offset due to errors in matching parameters of identical elements (mismatch).

Sampling an input signal with a known aperture delay and a small jigger is necessary to reduce the dynamic sampling error of a rapidly changing input signal, which is especially critical for parallel ADCs, but it can also be a problem for high-bit pipelined and multi-stage ADCs with input signal frequencies of tens of megahertz and higher.

The differential input signal, as a rule, is used in modern high-speed ADCs integrated in a single chip of a digital signal processing system to reduce the ADC sensitivity to noise on power buses, ground, and analog signals generated by digital circuits.

The need to ensure accuracy of signal conversion in a wide voltage range is dictated by the requirement to increase the signal-to-noise ratio, which is especially important when using modern submicron technologies with a reduced supply voltage to 1-2 V.

Known differential KN (see US patent No. 5644313, M. Cl. H03M 1/40, pr. 5.06.95, published 1.07.97), including a device for sampling the differential input signal (CVC) on switched capacitors with double (double sampling) sampling for the period of the clock signal. A gated differential amplifier (DU) is connected to the differential output of the UVC. The remote control includes a R-MOS key, connected by the source to the positive power bus and acting as a switched current source of the remote control, 3 pairs of matched R-MOS transistors, 3 pairs of matched N-MOS transistors and a pair of N-MOS keys, switching the outputs of the amplifier to the ground bus. The sources of two pairs of R-MOS transistors are connected to the drain of the R-MOS switch key of the switched source, and the R-MOS transistors of the first pair are connected by drains to the sources of the third pair of R-MOS transistors connected by gates to the differential inputs of the amplifier and the gates of the third pair of N-MOS transistors and drains to the differential outputs of the amplifier and drains of the third pair of N-MOS transistors. The sources of the third pair of N-MOS transistors are connected to the drains of the first pair of N-MOS transistors, the drains of the second pair of N-MOS transistors and the second pair of P-MOS transistors are connected to the outputs of the amplifier, and the sources of the first and second pairs of N-MOS transistors are connected to the ground bus.

The well-known SC corresponds to the above requirements b and c, since it has a CVC on switched capacitors with differential inputs. However, this KN does not have auto-correction of zero offset, which limits its accuracy, and is not able to provide high speed and accuracy with a reduced voltage to 2V or lower, since it has a series connection of 5 transistors (3 P-MOS and 2 N-MOS) between the buses nutrition. In addition, the R-MOS key, acting as a switched current source of the amplifier, produces increased noise, since it completely turns off the current of the amplifier.

Closest to the claimed is a differential KN with auto-correction of zero offset, presented in US patent No. 4899154, M. Kl. Н03М 1/36, pr. July 26, 88, published on February 6, 1990. This KN shown in FIG. 1 includes a first differential amplifier with a current source on a P-MOS transistor 101 connected between the positive power bus vdd 102 and a common source 103 of the input pair of R-MOS transistors 105, 106, the gates of which 109, 110 are connected by two pairs of keys 131, 133 and 132, 134 to the reference 150 and signal 151 of the KN inputs, and the drains of which 107, 108, which are the outputs of the first remote control, shunted by key 119, switched to the earth bus 100 by keys 124, 125, and connected to the drains of the first 113, 114 and second 111, 112 pairs of N-MOSFET ranzistors whose sources are connected to the earth bus. The gates of the first pair of N-MOS transistors are connected to the upper plates of the first pair of capacitors 115, 116, the lower plate of which is connected to the ground bus. The upper plates of the second pair of capacitors 122, 123, with the lower plates connected to the ground, are switched by the first pair of keys 117, 118 to the gates of the pair of N-MOS transistors 113, 114, and the second pair of keys 120, 121 to the outputs of the first remote control 107, 108. The gates of the input pair of N-MOS transistors 141, 142 of the second remote control are connected to the outputs of the first remote control 107, 108, and their drains are connected to the drains of the pair of R-MOS transistors 145,146. A pair of R-MOS transistors 145, 146 with sources connected to the positive supply bus, forming a current mirror, converts the differential signal of the second remote control input into a single-phase signal at the output of the second remote control 144. The output inverter 147 converts the signal at the output of the second remote control 144 to a digital signal output 152 of the inverter.

The described KN has a zero offset auto-correction circuit formed by a pair of N-MOS transistors 113,114, pairs of capacitors 115, 116 and 122, 123 and pairs of keys 120, 121 and 117, 118, and the capacitances of the capacitors 122, 123 should be much larger than the capacitors 117, 118. The autocorrection of the KN zero offset is carried out in the phase of zeroing the KN with the keys 132, 134 closed (high signal level b 181 in Fig. 1b), supplying the same voltage of the reference level of the source Vref 150 to the differential inputs. Autocorrection of the zero offset over many periods of the clock the clock 182, by sequentially switching on the key pairs 120, 121 and 117, 118 with the signals c0 183 and c1 184 (the high level of signals in Fig.1b), while the output potentials of the first remote control 107, 108 are transmitted to the upper plates of the capacitors 115, 116 and gates MOS transistors 115, 116 and are stored in the working phase of the SC (high signal level a 180). Formed over several periods of the clock clock signal, the voltages at the gates of the MOS transistors 113, 114 in the zeroing phase include the zero bias voltage of the output of the first remote control caused by the mismatch of the parameters of identical pairs of transistors. Negative feedback gate-drain MOS transistors 113, 114, reduces the specified bias voltage. For a more complete transfer of the potentials of the outputs 107, 108 KN to the capacitors 115, 116 and, accordingly, for more accurate bias correction, several periods of the clock signal are required, since the capacitance of the storage capacitors 115, 116 is much larger than the capacitance of the capacitors 122, 123, which carry out intermediate storage and transmission potentials of outputs 107, 108.

Auto-correction of the zero offset of this KN allows for high accuracy of comparing the input signal with the reference voltage Vref.

However, as can be seen from the diagrams of the control signals of this SC in Fig.1b, for its normal operation it is necessary that the frequency of the sampling and comparison cycles of the input signal (signals a 180 and b 181, which control keys 133, 134) is 4 times lower, than the clock frequency of the clock signal 182. The limiting frequency of the clock signal is limited by the relatively large time of recharging the capacitances of the outputs of the first ДУ 107, 108, including stray capacitances of the drains of transistor pairs 105, 106; 111, 112; 113, 114, keys 119, 124, 125 and gates of transistors 141, 142, from the ground potential to a relatively high voltage, a higher threshold voltage of N-MOS transistors 141, 142. Accordingly, the limiting frequency of the samples and comparing the input signal is significantly limited KN. In addition, this VF does not have an input I / O, which provides sampling of the input signal with a small and stable aperture delay, therefore, a large jitter of the sampling time will not allow this VF to process the high-frequency input signal with sufficient accuracy.

Also, due to the lack of input CVC on switched capacitors, it is impossible to use this KN for accurate sampling of a high-frequency input signal simultaneously with a CVM multiplying digital-to-analog converter (DAC), which is necessary in combined and pipelined ADCs. For example, the RSD (Redundant Signed Digit) ADC in the aforementioned US Patent No. 4,899,154 uses KN with input I / O on switched capacitors.

Despite the fact that the described well-known КН consists of differential amplifiers, it compares the potential at a single-wire input of the КН with the potential level at the reference input Vref, not providing the possibility of working with a differential input signal.

The aim of the invention is to increase the speed and accuracy, as well as reducing the power consumption of high-speed differential KV with a sample of the input differential signal.

To simplify the description, hereinafter we will call MOS transistors of the first or second type of conductivity, respectively, transistors of the first or second type, MOS keys - keys, a differential KN with a sample of the input differential signal - just KN, and a differential amplifier with input transistors of the first or second type of conductivity - the first or the second type, respectively.

The goals are achieved in that in a conductor containing at least one remote control of the first type with a pair of input transistors of the first type with a common source connected to a current source, and drains connected to the drains of the first and second pairs of transistors of the second type and forming differential remote control outputs, and between the gates of the first pair of transistors of the second type and the common source bus of the first and second pairs of transistors of the second type, a pair of capacitors is connected, the gates of the second pair of transistors of the second type are cross-connected to the drains the opposite transistors of the pair, forming positive feedback, the differential outputs of the remote control are shunted by the key, the gates of the first pair of transistors of the second type are connected by a pair of keys to their drains, and the gates of a pair of input transistors are connected to the differential outputs of the input-current characteristics of the input signal on switched capacitors and by the keys to the common-mode bus, in this case, after the completion of the sampling phase of the input signal of the UVX and disconnecting the gates of the first pair of transistors of the second type from their drains, the current source of the remote control increases the current, at least for the duration of the positive feedback operation of the second pair of transistors of the second type.

In the particular case, the goals are achieved by the fact that in the input wiring plates of the pair of capacitors UVX are connected by the first pair of keys closed in the phase of sampling the input signal to the differential inputs of the core and the second pair of keys closed in the phase of storing the input signal to the differential reference inputs of the KN and the output plates of these capacitors are connected by a third pair of keys, closed in the sampling phase, to the common-mode bus and a fourth pair of keys, closed in the storage phase, to the inputs of the remote control of the first type, and in the sampling phase, the inputs of the remote control of disconnected from the I / O and connected by keys to the common-mode bus, the gates of the first pair of transistors of the second type are connected by keys to their drains and the KV is in the zero state, and during the storage phase the gates of the first pair of transistors of the second type are disconnected from their drains, the remote control inputs are disconnected from the common-mode bus level and connected to the outputs of the I / O, as a result of which the KN switches to the state of comparison of the differential input signal of the KN with the voltage difference of the differential reference inputs of the KN.

In another particular case, an additional increase in speed is achieved by the fact that the KN produces a double sampling of the input differential signal for the period of the clock signal, for which the KN:

- input plates of the first pair of UVC capacitors are connected by the first pair of keys, closed in the sampling phase of the input signal by this pair of capacitors, to the differential inputs of the KN and the second pair of keys, closed in the phase of storing the input signal on this pair of capacitors, to the differential reference inputs of the KN, and the output the plates of said first pair of UVC capacitors are connected by a third pair of keys closed in the phase of sampling the input signal by this pair of capacitors to the common-mode bus and a fourth pair of keys closed in the xp phase anenia of the input signal on this pair of capacitors to the inputs of the remote control of the first type;

- the input plates of the second pair of UVC capacitors are connected by the fifth pair of keys, closed in the phase of sampling the input signal by this pair of capacitors, to the differential inputs of the KN and the sixth pair of keys, closed in the phase of storing the input signal on this pair of capacitors, to the differential reference inputs of the KN, and the output the plates of the mentioned second pair of UVC capacitors are connected by the seventh pair of keys closed in the phase of sampling the input signal by this pair of capacitors to the common-mode bus and the eighth pair of keys closed in the storage phase input signal on this pair of capacitors, to the inputs of the mentioned remote control;

- during the sampling phase of the input signal by the first pair of UVX capacitors, the second pair of UVX capacitors is in the storage phase of the input signal and, conversely, during the sampling phase of the input signal by the second pair of UVX capacitors, the first pair of UVX capacitors is in the storage phase of the input signal;

- at the end of each phase of the selection of any of the pairs of capacitors, the remote control inputs are disconnected from the I / O circuit and connected by keys to the common-mode bus, the gates of the first pair of transistors of the second type are connected by keys to their drains and the KV is in a state of zeroing;

- at the end of each sampling phase, the gates of the first pair of transistors of the second type are disconnected from their drains, and the remote control inputs are disconnected from the common-mode bus and connected to the UVX outputs for a time shorter than the duration of the UVX storage phase, as a result of which the KN switches to the comparison state for this time differential KN input signal with the voltage difference of the differential KN reference inputs.

In the particular case, the goals are achieved by the fact that in the gate to the output of the first type of remote control with input transistors of the first type are connected the gates of a pair of transistors of the second type of the subsequent second-type remote control with a common source connected to a switched current source, and drains that form the differential outputs of this remote control and connected to the drains of a pair of transistors of the first type, and the gates of a pair of transistors of the first type are cross-connected to the drains of the opposite transistors of the pair, forming a positive feedback, and the pair to Luch commutes the gates of a pair of transistors of the first type to their common source.

The increase in speed in the above and the following private versions of the SC is also achieved by the fact that after completing the sampling phase of the input signal and disconnecting the gates of the first pair of transistors of the second type from their sinks, the outputs of the remote control of the first type are shunted with a closed key, at least for the duration of the signal from the reference inputs of the KN to the outputs of the remote control.

In the particular case of the KH design, including the second type of remote control, the goals are achieved by the fact that the switched second-order current source of the second type turns on the current of this remote control after disconnecting the gates of the first pair of transistors of the second type of the previous first type remote control from its drains, at least for a while positive feedback triggering of a pair of transistors of the first type in the second type of remote control, and at the same time, the keys switching the gates of the first type of transistors of the second type of remote control to their source are opened.

In the particular case of the design of the KN with two series-connected remote controls of the first type, the goal of increasing accuracy is achieved by the fact that the gates of the input pair of the transistors of the first type of the second remote control of the first type are connected to the differential output of the first remote control of the first type, and the input gates of the second control of the second type pairs of transistors of the second type of the third remote control of the second type, the common source of which is connected to a switched current source, and the drains forming the differential outputs of the third remote control are connected enes to the drains of a pair of first type transistors and the gates of pairs of transistors of the first type cross connected to the drains of transistors of opposite pairs to form a positive feedback, and the pair of keys commutes closures pair of transistors of the first type to their common origin.

In the particular case of KH design with two series-type remote controls of the first type, the set goal of improving accuracy is also achieved by the fact that the key shunting the outputs of the second remote control of the first type is turned off with a delay relative to the key shunting the outputs of the first remote control of the first type, the switched current source of the third remote control of the second type turns on the current of the third remote control after turning off the key, shunting the outputs of the second remote control of the first type, and the keys connecting the drains of the transistors of the first type of the third remote control of the second type to their common source turn off kzhe after turning off the key, outputs the second control diverter first type.

In another particular case of KH execution, an additional increase in accuracy and speed is also achieved by the fact that the outputs of the last remote control of the second type are connected via one of the inputs of two logical AND gate, the second inputs of which are cross-connected to their outputs, forming a trigger latch, and the valve outputs are direct and inverse KN outputs.

The goal of increasing accuracy is achieved in the CV, including the first type of remote control also by the fact that the steepness of the second pair of transistors of the second type is less than the steepness of the input transistors and much less than the steepness of the second type of transistors of the first pair.

The invention is illustrated by drawings.

Figure 1 presents the already described scheme of the known KN with auto-correction of zero offset, closest to the claimed.

Figure 2 presents a diagram of the inventive differential KN with a single sampling of the input differential signal, the first remote control of the first type and the second remote control of the second type, using auto-correction of zero offset.

Figure 3 presents a diagram of the inventive differential KN with double sampling of the input differential signal, the first remote control of the first type and the second remote control of the second type, using auto-correction of zero offset.

Figure 4 presents a diagram of the control signals necessary for organizing the operation of the inventive SC with a single (Fig. 4a) and a double (Fig. 4b) sampling of the input differential signal, as well as the waveform at the outputs of the remote control.

Figure 5 presents an embodiment of a logical circuit for the formation of control signals of the inventive SC with a double sampling of the input differential signal.

Figure 6 presents a diagram of the inventive differential KN with a sample of the input differential signal, the first three and the second remote control of the first type, and the third remote control of the second type, using auto-correction of zero offset.

Below, by the example of the drawings, a description is given of the device and operation of the claimed differential KN with sampling of the input signal and auto-correction of zero offset.

Figure 2 presents a diagram of the inventive differential KN with a single sampling of the input differential signal, the first remote control of the first type and the second remote control of the second type, using auto-correction of zero offset according to claims 1, 2, 4, 5, 6, 10 of the Formula.

The differential input signal is supplied to the differential inputs 261, 262 of the CVC KH connected to the inputs of the first pair of input keys 255, 256, which are closed in the sampling phase of the input signal, and the outputs of which are connected to the input plates of the pair of sample-storage capacitors 253, 254. Differential reference voltage arrives at the differential reference inputs UVX 263, 264 connected to the inputs of the second pair of input keys 257, 258, closed in the phase of storage of the input signal, and the outputs of which are also connected to the input plates of the mentioned pair of condensation orov 253, 254. The output plates of the mentioned pair of capacitors 253, 254 are connected by a third pair of keys 251, 252, locked in the phase of sampling the input signal, to the common-mode bus vcm 232 and a fourth pair of keys 233, 234, closed in the phase of storing the input signal, to differential outputs of UVX 209, 210. The mentioned differential outputs of UVX are connected to the gates of a pair of input transistors 205, 206 of the first type (in the design shown in the drawing, P-type) of the input remote control, and the gates of the said pair of transistors 205, 206 are in the sampling phase of the input signal I will connect They are coupled by a pair of keys 230, 231 to the common-mode bus vcm 232. The sources of the aforementioned pair of input transistors 205, 206 are combined and connected to the output of a direct current source on transistor 201 of the first type (P), and their drains to the outputs 207, 208 of the remote control and to the drains of the first 213, 214 and second 211, 212 pairs of transistors of the second type (N), and the source of the transistor of the current source is connected to the positive power bus vdd 202, and a voltage defining a constant current of the remote control is supplied to its gate 204. The gates of the first pair of transistors 213, 214 of the second type are connected by a pair of keys 217, 218 to their drains, and the pair of capacitors 215, 216 to the common source of the first and second pairs of transistors of the second type and to the negative power (or ground) bus vss 200. The gates of the second pair transistors 211, 212 of the second type are cross-connected to their drains, forming a positive feedback, and the outputs of the first remote control are shunted by key 219.

An additional switched current source is also connected to the common source of input transistors of the first remote control on a series-connected transistor of the first (P) type 220 and key 221, which increases the total remote control current after completing the sampling phase of the input signal and disconnecting the gates of the first pair of transistors of the second type from their drains, at least during the formation of the required amplitude of the output signal of the remote control due to the positive feedback of the second pair of transistors of the second type.

The outputs of the first remote control 207, 208 are connected to the gates of the input transistors 241, 242 of the second (N) type of the next (in the drawing of the second) remote control of the second type in accordance with paragraphs 4, 6 of the Formula. The common source of the mentioned input transistors of the second remote control is connected to the output of the switched current source 243, and their drains are connected to the drains of the pair of transistors 246, 247 of the first (P) type and form the differential outputs of this remote control 244, 245. The gates of the pair of transistors 246, 247 of the first type are connected cross to their drains, forming a positive feedback, and a pair of keys 248, 249 commutates the gates of transistors 246,247 and the corresponding outputs of this remote control to the positive power bus 202.

The I / O and remote control keys of the comparator are controlled by two pairs of clock signals a0 280, b0 281 and a1 282, b1 283 with non-overlapping high-level active phases usually used to control the I / O, and the pair of signals a1, b1 is delayed relative to the pair a0, b0. The key 219 of the first remote control is controlled by an additional signal nab 287, formed from the signals a0, b0, for example, a logical function OR-NOT. The key 221 of the first remote control is controlled by an additional signal a2 285, delayed relative to a1.

The diagrams of the control signals a0 280, b0 281, a1 282, b1 283, a2 285, nab 287 for the keys of the described KN with the usual (one-time per clock signal) sampling of the input signal and the form of voltages at the outputs 207, 208 of the first remote control are shown in FIG. 4a.

During the sampling phase of the input signal 400, the capacitors 253, 254 of the UVC are connected at a high signal level a1 282 with closed keys 255, 256 to the differential inputs of the comparator 261, 262 and at a high signal level a0 280 with closed keys 251, 252 to the common mode bus vcm 232. The keys 217, 218 of the remote control are closed at a high level of the signal a0 280, connecting the gates of the transistors 213, 214 with their drains, the key 219 of the remote control is open at a low level of signal nab 287, and the key 221 of the remote control (P-type) is open at a high level of signal a2 285 . In the sampling phase, including the actual sampling time, input gates of transistors ДУ 205, 206 are disconnected from the I / O output by open keys 233, 234 at a low signal level b0 281 and connected to the common-mode bus vcm 232 with keys 230, 231 at a high signal level a1 282. Thus, in the sampling phase, the remote control is in the stage zeroing, since the voltages at the gates of the input transistors of the remote control are equal (vcm), and transistors 213, 214 with gates shorted with their drains provide a voltage equal to the zero bias voltage of the output of the remote control 422 at the differential output of the remote control 207, 208.

The zero offset voltage of the remote control output at the zeroing stage (Voffs_out) _{0 is} approximately determined by the relations below.

where ΔVt ₁ , ΔVt ₂₁ , ΔVt ₂₂ is the mismatch of the threshold voltages of the transistors of the input pair and the transistors of the first and second pairs of the second type, respectively;

gm ₁ , gm ₂₁ , gm ₂₂ - the steepness of the transistors of the input pair and the transistors of the first and second pairs of the second type, respectively;

Δgm ₁ , Δgm ₂₁ , Δgm ₂₂ - the mismatch of the steepness of the transistors of the input pair and the transistors of the first and second pairs of the second type, respectively;

I ₁ , I ₂₁ , I ₂₂ are the currents of the transistors of the input pair and the transistors of the first and second pairs of the second type, respectively;

ΔI ₁ , ΔI ₂₂ - the mismatch of the currents of the transistors of the input pair and the second pair of transistors of the second type, respectively.

The subscript ₀ means that the value of the corresponding parameter corresponds to the zeroing stage of the remote control.

From (3) it is seen that the mismatch of the currents of the second pair of transistors of the second type is determined by the output zero bias voltage multiplied by half the steepness of the transistors of the second pair of the second type, due to the positive feedback of the cross-connection of the gates of these transistors. Therefore, to ensure a low voltage of zero bias of the output of the remote control, the steepness of the transistors of the second pair of the second type should not be large, on the contrary, from (1) it follows that the greater the steepness of the transistors of the first pair of the second type, the lower the voltage of the bias of the zero of the output of the remote control.

Indeed, substituting (2) and (3) in (1) and omitting the terms with low weight, we obtain relation (4), simplified for clarity, that determines the zero-point voltage of the remote control output.

From (4) it follows that in order to reduce the zero-bias voltage of the remote control output due to the mismatch of the parameters of all pairs of remote control transistors, the slope of the transistors of the second pair of the second type should be much less than the slope of the transistors of the first pair of the second type.

The moment of the first sampling tsp1 401 (Fig. 4a) of the input signal is determined by the moment of opening of the keys 251, 252 (Fig. 2) at the trailing edge of the signal a0 280, while the keys 217, 218 are also opened, disconnecting the gates of the transistors 213, 214 from the drains and fixing potential on capacitors 215, 216. After opening the keys 251, 252, 217, 218, the key 219 closes for a high level of signal nab 287, preventing the voltage at the differential output of the remote control from changing due to the positive feedback of transistors 211, 212 under the influence of random interference. The voltage difference at the differential outputs of the remote control (420, 421 of Fig. 4a) with the key 219 closed is close to 0. With a certain delay from the sampling time tsp1 401, determined by the non-overlap of the phases a0, b0, the capacitors 253, 254 of the CVC are disconnected from the KN and bus inputs in-phase level and are connected by keys 257, 258 to the differential reference inputs of KN 263, 264, and by keys 233, 234 to the gates of the input transistors of the remote control at a high signal level b0 281. This state corresponds to phase 402 of storage of the first sample of the input signal at the I / O circuit, while input capacitor plates 253, 254, and accordingly at the input of the remote control, a differential signal is generated corresponding to the difference between the input and reference voltages. When the signal nab 287 goes to a low level, the key 219 opens, allowing the voltages of the differential outputs of the remote control to change in accordance with the difference between the differential input signal and the differential voltage reference of the KN.

At the end of the sampling storage and comparison phase 402 (Fig. 4a), the signal level b0 281 changes to low, and the signal a0 280 changes to high, transferring the I – V characteristic to the sampling phase and the remote control to the zeroing state. The high-level signal pulse nab 287 formed at the moment of transition closes the key 219, accelerating the process of zeroing the differential voltage of the remote control output. Then, similarly, the next (second) sample of the input signal at the time tsp2 404 is also performed.

The zero bias voltage of the input Voffs _ in the remote control with gain Ku when the gates of the transistors of the first pair of the second type are disconnected from the drains (in the comparison stage) is determined by the relations:

where R ₁ is the output resistance (drain-source) of the transistors of the input pair of the remote control;

Ri is the output resistance of the remote control (parallel connection of the output resistances of the transistors of the input pair and both pairs of the second type);

Note that the current dependences of the slope (gm) and the drain-source output resistance (Rds) for MOS transistors are determined by well-known relations (7), (8).

where n = 0.5 at sufficiently high currents and increases to 1 at low channel current densities (in the near-threshold region of operation of a MOS transistor with a gate-source voltage lower than the threshold voltage).

As can be seen from the above relations, in order to reduce the bias voltage of the input of the remote control and the KN, as well as increase the gain Ku, and accordingly the sensitivity (resolution) of the KN, it is necessary to increase the slope of the transistors of the first pair of the second type (gm ₂₁ ) and the input transistors (gm ₁ ) of the remote control without increasing the current, for example, by increasing the shape factor (the ratio of the channel width of the transistor to its length).

On the contrary, an increase in the remote control current necessary to increase the speed leads to a decrease in the gain, and, accordingly, to a deterioration in sensitivity, and an increase in the bias voltage of the input of the remote control and the main voltage as a whole.

The second pair of transistors of the second type of remote control with a cross-connection of the gates with drains, forming a positive feedback, is used to increase the gain and speed of the remote control. Obviously, the greater the steepness and current of the transistors of the second pair of the second type, the higher the gain and speed of the remote control, but the greater the bias voltage and the hysteresis of the remote control, leading to the possibility of incorrect operation of the SC at the moment of transition from the zeroing stage to the comparison stage. This contradiction can be resolved by using a small remote control current in the zeroing stage and by increasing the current after disconnecting the gates of the first pair of the second type of transistors from the drains and receiving an input signal from the I / O output to the remote control input. Moreover, due to the gate voltages of the transistors of the first pair of the second type fixed on the capacitors, these transistors cannot pass the increasing current, therefore, the voltages at their drains (remote control outputs) and, accordingly, at the gates of the transistors of the second pair of the second type should increase. In turn, an increase in the voltage at the gates of the transistors of the second pair of the second type leads to a strong increase in the current and the steepness of this pair of transistors. For example, when the ratio of the channel width of the transistors of the first pair of the second type to the channel width of the transistors of the second pair of the second type (Wg ₂₁ / Wg ₂₂ ) = 0.05, the ratio of the currents of these transistors (I ₂₁ / I ₂₂ ) in the zeroing stage is also 0.05 . A subsequent increase in the remote control current by a factor of 2 can cause an increase in the current of the transistors of the second pair of the second type by almost 20 times. Accordingly, in (20) ^0.5 ... (20) ¹ = 4.5 ... 20 times the steepness of the transistors of the second pair of the second type will increase, while the output resistance of the remote control (Ri), determined in a first approximation by the resistance of the drain-source transistors of the input pair of the first type and the first pair of the second type, will decrease by only 2 times. If, in this case, the parameters of the remote control transistors are selected so that gm22 · Ri is close to 2, then Ku, defined by relation (3), can increase by tens of times. Accordingly, the sensitivity of the KN will increase, while the voltage of the zero bias of the input will increase slightly due to a change in the zero bias of the output of the remote control when the current changes. Indeed, it can be seen from (1) that for sufficiently large gm21, the contribution of the second and third terms on the right-hand side of relation (1) to the bias voltage of the output of the remote control can be insignificant. However, with a sufficiently large increase in current, gm22 · Ri can exceed 2, which means that the polarity of the gain of the remote control is positive. In practice, this means that if the output differential voltage of the remote control has not yet reached a sufficient level as a result of the influence of the input KH signal, then the transistors of the second pair of the second type will draw due to the positive feedback and the output voltage of the remote control will change to the opposite, snapping the remote control in the wrong state.

It should be noted that the effect of a sharp increase in the current and the steepness of the transistors of the second pair of the second type (similar to an increase in the remote control current) can be exerted by the charge injection on the upper plates of the capacitors 215, 216 when the keys 217, 218 are opened. The aforementioned charge injection leads to a decrease in the voltage across the gates of the transistors the first pair of the second type, and thereby, to a decrease in the current in the transistors of the first pair of the second type and a corresponding increase in the current of the transistors of the second pair of the second type. The aforementioned injection effect leads to a deterioration of the QW operation, since it occurs in the absence of the correct input signal at the remote control input (the gates of the input transistors of the remote control are still shorted), and is also an additional source of current mismatch in the remote control arms due to the mismatch of the parameters of the keys and capacitors. Thus, the injection of the charge of the keys 217, 218, which leads to an increase in the current and the steepness of the transistors of the second pair of the second type and, accordingly, to the strengthening of the positive feedback, can lead to improper operation (snapping) of the remote control and the primary voltage even before the input signal arrives. Therefore, this effect must be minimized by reducing or compensating for the charge injected by the keys and increasing the capacitance of the capacitors 215, 216.

It is known that the mismatch of the parameters of paired transistors in a first approximation is inversely proportional to the square root of the gate area of the transistors. Therefore, reducing the steepness of the transistors of the second pair of the second type is advisable both by decreasing the channel width and increasing the length, providing a shutter area sufficient for the required accuracy of matching the parameters.

Thus, from the consideration of the features of the remote control, we can draw the following conclusions:

- in the remote control with input transistors of the first type, it is necessary to set the slope of the transistors of the second pair of the second type less than the slope of the input transistors and transistors of the second type of the first pair, reducing the width and (or) increasing the length of the channel. The increased channel length of the transistors of the second pair of the second type, compared with the first pair, despite the increased stray capacitance, may be preferable, since transistors with a channel length greater than the minimum have an increased threshold voltage and begin to work more efficiently with increasing remote control current;

- in order to minimize the voltage of the KV zero bias, increase its sensitivity (gain) and at the same time achieve maximum performance at the minimum current consumption, it is necessary to minimize the remote control current in the zeroing stage and increase it in the comparison stage after disconnecting the gates of the first pair of transistors of the second type from their drains ;

- it is possible to increase the remote control current only after connecting the gates of the input transistors of the remote control to the output of the I / O and the input of the KH input signal through the I / O to the input of the remote control. If there is a key 219, which shunts the remote control outputs for the time of switching the I / O into the storage phase and the input of the KH input signal to the remote control input, an increase in the remote control current can begin during switching of the I / O and formation of the input remote control signal. However, before the formation of a sufficient level of the output differential voltage of the remote control, there should not be a significant increase in current in order to avoid incorrect latches of the remote control;

- increased remote control current is necessary only for the duration of the remote control output voltage generation under the influence of positive feedback formed by cross-connecting the gates of the transistors of the second pair of the second type to their drains, after which the remote control current can decrease again to minimize the average current consumption of the KV.

The second remote control with input transistors of the second type connected to the output of the first remote control, shown in figure 2, is necessary to further increase the gain of the gain and the formation of the output differential voltage sufficient to trigger the subsequent logic circuit (usually a trigger-latch).

The second remote control has a switched current source 243, which ensures that the current of this remote control is turned on only for the time necessary to form the output voltage of the remote control, and switches 248, 249, which provide a high voltage level at both outputs of the second remote control (logical unit level) while the first remote control is in zeroing stages. The main requirement for the control signal b1 283 is its small delay for activating the second remote control only after the correct output signal of the first remote control of sufficient amplitude.

Figure 3 presents a diagram of the inventive differential KN with double sampling of the input differential signal for the period of the clock signal, two remote control and auto-correction of zero offset according to claim 1, 3, 4, 5, 6, 10 of the Formula.

The differential input signal is supplied to the differential inputs 361, 362 of the I / O CV connected to the input plates of the first pair of sample-storage capacitors 353, 354 by the first pair of input keys 355, 356, which are closed in the sample phase of the input signal by the first pair of capacitors, and also connected to the input the plates of the second pair of capacitors of the sample-storage 373, 374 by the fifth pair of input keys 375, 376, which are closed in the phase of sampling the input signal by the said second pair of capacitors. The differential reference voltage is supplied to the differential reference inputs 363, 364 of the UVC connected to the input plates of said first pair of capacitors by a second pair of input keys 357, 358, closed in the phase of storing the input signal on said first pair of capacitors, and also connected to the input plates of said second pair capacitors the sixth pair of input keys 377, 378, locked in the phase of storage of the input signal on said second pair of capacitors. The output plates of the aforementioned first pair of capacitors are connected to the common-mode bus vcm 332 by a third pair of keys 351, 352, closed in the phase of sampling the input signal by the first pair of capacitors, and to the differential outputs UVX 309, 310 by a fourth pair of keys 333, 334, closed in the storage phase an input signal on said first pair of capacitors. The output plates of the said second pair of capacitors are connected to the common-mode bus vcm 332 by the seventh pair of keys 371, 372, closed in the phase of sampling the input signal by the second pair of capacitors, and to the differential outputs UVX 309, 310 by the eighth pair of keys 333, 334, closed in the storage phase an input signal to said second pair of capacitors.

The differential outputs of the UVX are connected to the gates of the pair of input transistors 305, 306 of the first type (in the design shown in the drawing, P-type) of the input remote control, and the gates of the said pair of transistors 305, 306 in the sampling phase of the input signal are connected by a pair of keys 330, 331 to the bus in-phase level vcm 332. The sources of the aforementioned pair of input transistors 305, 306 are combined and connected to the output of a direct current source on the transistor 301 of the first type (P), and their drains to the outputs 307, 308 of the remote control and to the drains of the first 313, 314 and second 311, 312 pairs of transistors of the second type (N), with than the source of the transistor of the current source is connected to the positive power bus vdd 302, and a voltage is supplied to its gate 304, which specifies the operating mode current of the remote control. The gates of the first pair of transistors 313, 314 of the second type are connected by a pair of keys 317, 318 to their drains, and the pair of capacitors 315, 316 are connected to the common source of the first and second pairs of transistors of the second type and to the negative power (or ground) bus vss 300. The gates of the second pairs of transistors 311, 312 of the second type are cross-connected to their drains, forming a positive feedback, and the outputs of the input remote control are shunted by a key 319.

An additional switched current source is also connected to the common source of the input transistors of the first remote control on a series-connected transistor of the first (P) type 320 and a key 321, which increases the total current of the remote control current source after completing the sampling phase of the input signal at the IWX and disconnecting the gates of the first pair of second type transistors from their stocks. An increased remote control current is necessary, at least for the duration of the formation of the remote control output signal under the influence of an input signal amplified by the positive feedback of the second pair of transistors of the second type.

The gates of the input transistors 341, 342 of the second type (in the N-type drawing) of the next (in the second drawing) of the remote control in accordance with paragraphs 4, 6 of the Formula are connected to the outputs of the first remote control 307, 308. The common source of the mentioned input transistors of the second remote control is connected to the output of the switched current source 343, and their drains are connected to the drains of a pair of transistors 346, 347 of the first (P) type and form the differential outputs 344, 345 of this remote control. The gates of the pair of transistors 346, 347 are cross-connected to their drains, forming a positive feedback, and the pair of keys 348, 349 commutes the gates of the transistors 346, 347 and the corresponding outputs of this remote control to the positive power bus 302.

The I / O keys of this comparator are also controlled by two pairs of clock signals a0 380, b0 381 and a1 382, b1 383 with non-overlapping high-level active phases, usually used to control similar I / O, and the pair of signals a1, b1 is delayed relative to the pair a0, b0.

The remote control key 319 is controlled by an additional signal nab 387 generated from the signals a0, b0, for example, by a logical function OR-NOT. The keys 321 and 343, 348, 349 of the remote control are controlled by additional signals ncw1 397 and cw1 396, respectively, generated from the additional signal cw 394, which determines the duration of the active stage of comparing the input signal of the SC, for example, two (cw1) and three inversions (ncw1) (see Figure 5). Note that instead of the ncw1 signal, the new signal obtained from cw by one inversion can also be used.

The keys of the remote control 330, 331, 317, 318 are controlled by an additional signal abncw 398, formed from the signals a0, b0, and cw, for example, two consecutive logical functions OR-NOT (Figure 5).

Diagrams of control signals a0 380, b0 381, a1 382, b1 383, nab 387, cw 394, new 395, cw1 396, ncw1 397 for the keys of the described KN with a double (per clock signal) sampling of the input signal and voltage diagram 420, 421 at the outputs 307, 308 of the first remote control and 423, 424 at the outputs 344, 345 of the second remote control (second type) are presented in Fig.4b.

Consider the features of a more complex SC with a double sampling of the input signal, which allows to double the frequency of samples of one SC.

The design and principle of operation of the CVC with double sampling of the input signal on independent capacitors are known, see, for example, US patent "Switched capacitor gain stage", No. 5574457, M. Kl. Н03М 1/12, published November 12, 1996. At the same time, the sampling frequency doubles, but additional sampling errors appear due to the mismatch of capacitors and key parameters of different sample blocks.

The scheme and principles of operation of a double-sample CVC are generally similar to the operation of a conventional single-sample CVC. The main difference between the double-sampling UVC is the presence of two identical sampling and storage units that operate alternately: during the sampling phase by the first block, the second block is in the storage phase, and, conversely, during the storage phase by the first block, the second block is in the sampling phase . The control of both units of the IWC is carried out, as already mentioned, by two pairs of signals a0 380, b0 381, a1 382, b1 383 (Fig. 4b), and the pairs of signals a0, a1 and b0, b1 have non-overlapping high-level active phases, and a pair signals a1, b1 is delayed relative to a pair of signals a0, b0. The sampling times of the input signal (tspi) are determined by the trailing edges of the signals a0, b0. In a double-sampling KN, similar to the single-sampling KN considered above, the nab 387 signal is also used, the high level of which closes the key, which shunts the differential output of the remote control during switching of the CVC from the sampling phase to the comparison phase, and thereby preventing false triggering of the remote control after shutting off the gates of the second pair of transistors of the second type until the correct input signal appears at its input.

As you can see, the remote control in the double-walled SC should work twice as fast, providing processing of the samples of both UHFs, and accordingly, both stages of operation (zeroing and comparison) for such a remote control should fit into the half-period of signals a0, b0. To implement such a mode of operation of the remote control, an additional signal cw 394 is required, which determines the time interval (window) of the stage of comparison of the remote control from the moment of sampling the input signal of the UVC. Obviously, the window duration of the remote control comparison stage should be minimal, but sufficient for reliable operation of the SC with a minimum differential input signal. The cw signal forms a delayed signal cw1 396, the high level of which turns on the current source 343 and turns off the keys 348, 349 of the second remote control with input transistors of the second type, as well as the delayed and inverted signal ncw1 397, the low level of which connects an additional current source 321 to increase the current of the remote control . Signals cw and a0, b0 also form the signal abncw 398, the low level of which opens the remote control keys 317, 318, 330, 331, ensuring the remote control enters the comparison stage. Obviously, for normal operation of a VF with a double sampling, the stage of comparing the remote control must have a duration substantially shorter than the duration of the storage phases of the UVC, since a sufficiently large time is required for the subsequent stage of zeroing the remote control, taking into account the need to remove the remote control from the state of the maximum differential output signal under the influence of a positive feedback communication and possibly more accurately establish the bias voltage zero at the output of the remote control.

On the diagram of Fig. 4b, the moments of successive samples of the input signal tsp1 401, tsp2 404, tsp3 407 and the sequence of stages of zeroing 400, 403, 406, 409 and comparison 402, 405, 408 for samples by blocks A and B of the I / O are indicated. Conventional forms of voltages at the differential outputs of the first V ₃₀₇ 420, V ₃₀₈ 421 and the second V _outp 423, V _outn 424 for the remote control shown in Figure 3 are shown. The diagram also shows: zero bias voltage at the output of the first remote control in the zeroing stage 422; the formation of a large signal at the outputs of the first remote control in the comparison stage at a low signal level abncw; high voltage level (power supply) at both outputs of the second remote control at the zeroing stage; the formation of a large signal at the output of the second remote control in the comparison stage at a high signal level cw1.

Figure 5 shows a variant of the schemes for generating additional control signals required for the operation of the SC, shown in Figure 3. As you can see, these schemes are extremely simple.

Figure 6 shows the SC scheme with three remote controls necessary to increase the gain and, accordingly, further reduce the bias voltage of zero and increase the resolution of the SC. In this KN, two remote controls with input transistors of the first type and auto-correction of zero offset and a third remote control with input transistors of the second type are used to form the output signal with a full amplitude in the range of the supply voltage. The principles of operation of this SC are similar to those already considered. However, for the effective operation of such a SC, it is necessary to generate additional control signals ncw2, nab1 and cw2 for the second and third remote control with optimal delays, forming a conveyor signal passing through all the remote control.

Evaluation of the practical feasibility and effectiveness of the proposed SC was carried out by modeling the SC scheme with a double sample of the input signal and two remote controls, shown in Figure 3, based on 0.18 μm CMOS technology with a supply voltage of 1.8 V.

A digital trigger latch on two NAND elements is connected to the output of the second remote control. The purpose of the simulation was to develop a conductor suitable for use in high-speed (more than 100 million samples per second) 12-bit multi-stage (pipelined) ADCs as the first stage with sampling of the ADC input signal and 4-bit parallel conversion. The amplitude of the differential input signal of the ADC is 1V rr, the permissible error of the KN is 31 mV, taking into account the use of the well-known digital correction technology.

In the simulation, the control signals a0, b0, a1, b1, cw, formed by real CMOS generators used in the high-speed conveyor ADC circuit, were used. Additional control signals cw1, ncw1, nab, abncw were generated by the circuits shown in Fig.5 in accordance with the diagram shown in Fig.4b.

Some design characteristics of the main elements of the SC:

- the width and length of the channel of the input transistors (RMOS) of the first remote control is 8 μm / 0.18 μm;

- the width and length of the channel of the first pair of NMOP transistors of the first remote control is 14 μm / 0.36 μm;

- the width and channel length of the second pair of NMOP transistors of the first remote control is 1.4 μm / 0.36 μm;

- the capacitance of the capacitors sample UVH and storage bias DN - 0.03 pF and 0.04 pF

- typical current of direct and switched current sources of the first remote control - 35 μA and 47 μA

As a result of the simulation, the main characteristics of the SC are obtained for typical conditions (typical supply voltage 1.8 V, medium temperature 25 ° C, typical element models and ideal matching of remote control transistors) and for the worst case (supply voltage in the range 1.6-2.0 C, the temperature of the medium is in the range of minus 40-150 ° C, all available models of elements and the worst combination of the mismatch of transistors of all pairs of both remote controls of 3 sigma).

The following characteristics of KN are obtained:

- minimum differential input signal for correct operation of the KN (Vin):

12 mV typical; 18 mV worst;

- the maximum delay of the output signal KN at the output of the trigger:

from the time of sampling (trailing edge of the signals a0, b0), (td _ kn):

1.63 ns typical (at Vin = 12 mV); 2.10 ns worst case (at Vin = 18 mV);

from the moment of connecting the I / O to the remote control (leading edge of the signals a1, b1), (td remote control):

0.97 ns typical; 1.23 ns worst;

- averaged current consumption KN (Idd _ avg): 124 μA typical; 151 μA is the worst.

Note that the time of switching the CVC from the sampling phase to the comparison phase, including the non-overlap of the high-level phases a0, b0 and the signal delay a1, b1 and determined by the speed of the used element base, amounted to 0.87 ns in the worst case, i.e., the signal delay time on two remote controls and an output trigger (td remote), in the worst case, it was only 1.23 ns. The use of a faster element base, for example, technologies with dimensions of 0.13 microns or less, will allow for even shorter time delay of the SC.

From the above data it is seen that the inventive CL has excellent performance characteristics at low current consumption and acceptable accuracy, allowing you to implement 12-bit pipelined ADC with a capacity of up to 150 million samples per second.

Thus, the claimed KN has novelty, can be implemented and can significantly improve the speed and accuracy of the comparison of the input signal, as well as reduce power consumption.

Claims (10)

1. A differential voltage comparator (KN) with a sample of the input differential signal, containing at least one differential amplifier (DU) with a pair of input MOS transistors of the first conductivity type with a common source connected to the current source, and drains connected to the drains of the first and the second pair of MOS transistors of the second type of conductivity and forming the differential outputs of the remote control, and between the gates of the first pair of MOS transistors of the second type of conductivity and the common source bus of the first and second pairs of MOS transistors the second type of conductivity includes a pair of capacitors, the gates of the second pair of MOS transistors of the second type of conductivity are connected crosswise to the drains of the opposite transistors of the pair, forming positive feedback, and the differential outputs of the remote control are shunted by the MOS key, characterized in that the gates of the first pair of MOS transistors of the second type of conductivity are connected by a pair MOS keys to their sinks, the gates of a pair of input MOS transistors are connected to the differential outputs of the device for sampling and storing (UVX) the input signal to switched capacitors and MOSFETs with the keys to the common-mode bus, and after completing the sampling phase of the input UVX signal and disconnecting the gates of the first pair of MOSFETs of the second type of conductivity from their drains, the current source of the remote control increases the current, at least for the duration of the positive feedback operation of the second pair MOS transistors of the second type of conductivity. 2. Differential KN with sampling of the input differential signal according to claim 1, characterized in that the input plates of the pair of capacitors UVX are connected to the differential inputs of the KN by the first pair of MOS keys, the second pair of MOS keys to the differential reference inputs of the KN, and the output plates of the mentioned capacitors are connected by the third a pair of MOS keys to the common-mode bus and a fourth pair of MOS keys to the remote control inputs, and in the sampling phase, the remote control inputs are disconnected from the I / O and the MOS keys are connected to the common-mode bus, the gates of the first pair of MOS transients Of the second conductivity type, the MOS keys are connected to their drains by the keys and the SC is in the zero state, and during the storage phase, the gates of the first pair of the second conductivity type MOS transistors are disconnected from the drains, the remote control inputs are disconnected from the common-mode bus and connected to the UVX outputs, as a result of which the SC goes into a state of comparison of the differential input signal with the voltage difference of the differential reference inputs. 3. The differential KN according to claim 1 with a double sampling of the input differential signal for the period of the clock signal, characterized in that the input plates of the first pair of capacitors UVX are connected by the first pair of MOS keys to the differential inputs of the KN and the second pair of MOS keys to the differential reference inputs of the KN, and the output plates of the aforementioned first pair of capacitors are connected by the third pair of MOS keys to the common-mode bus and the fourth pair of MOS keys to the inputs of the remote control, the input plates of the second pair of capacitors UVX are connected by the fifth pair MOS keys to the differential inputs of the KN and the sixth pair of MOS keys to the differential reference inputs of the KN, and the output plates of the mentioned second pair of capacitors are connected by the seventh pair of MOS keys to the common-mode bus and the eighth pair of MOS keys to the inputs of the remote control, and during the sampling phase of the input signal mentioned the first pair of capacitors, the second pair of capacitors is in the storage phase of the input signal and, conversely, during the sampling phase of the said second pair of capacitors, the first pair of capacitors is in the storage phase I of the input signal, at the end of each phase of the sampling of any of the pairs of capacitors, the remote control inputs are disconnected from the I / O circuit and connected by the MOS keys to the common-mode bus, the gates of the first pair of MOS transistors of the second type of conductivity are connected by the MOS keys to their drains and the KN is in the zero state, at the end of each sample, the gates of the first pair of MOS transistors of the second type of conductivity are disconnected from their drains, and the inputs of the remote control are disconnected from the common-mode bus and connected to the UVC outputs for a time shorter than the duration of the UVC storage phase, ensuring I state comparison of the differential input signal with the difference between differential inputs reference voltages. 4. A differential KN with a sample of the input differential signal according to claim 1, characterized in that the gates of a pair of input MOS transistors of the second conductivity type of the next remote control with a common source connected to a switched current source are connected to the differential output of the remote control with input MOS transistors of the first type of conductivity and drains forming the differential outputs of this remote control and connected to the drains of a pair of MOS transistors of the first conductivity type, and the gates of a pair of MOS transistors of the first conductivity type are connected crosswise to the drains of the opposite transistors of the pair, forming a positive feedback, and the pair of MOS keys switches the gates of the pair of MOS transistors of the first type of conductivity to their common source. 5. Differential KN with sampling the input differential signal according to claim 1, characterized in that at the end of the sampling phase of the input signal and disconnecting the gates of the first pair of MOS transistors of the second type of conductivity from their sinks, the outputs of the remote control with input MOS transistors of the first type of conductivity are shunted by a closed MOS key, at least for the duration of the signal from the reference inputs of the SC to the outputs of this remote control. 6. Differential KN with sampling the input differential signal according to claim 4, characterized in that after opening the MOS keys connecting the gates and drains of the first pair of MOS transistors of the second conductivity type of the previous remote control with the input MOS transistors of the first conductivity type, the switched current source includes the current of the remote control with input MOS transistors of the second type of conductivity, at least for the time of positive feedback operation of a pair of MOS transistors of the first type, and at the same time, MOS switches open, the commutator MOS transistors of the first type to their source. 7. Differential CV with a sample of the input differential signal according to claim 1, characterized in that the gates of the input pair of MOS transistors of the first conductivity type of the second remote control, similar to the first, are connected to the differential output of the first remote control with input MOS transistors of the first type, and the differential output of the second The gates are connected to the gates of the input pair of MOS transistors of the second type of conductivity of the third remote control with a common source connected to a switched current source, and drains forming differential outputs of the remote control and connected to the drains of a pair of MOS transistors of the first conductivity type, and the gates of a pair of MOS transistors of the first conductivity type are cross-connected to the drains of the opposite transistors of the pair, forming positive feedback, and a pair of MOS switches switches the gates of a pair of MOS transistors of the first conductivity type to their common source . 8. Differential KN with sampling the input differential signal according to claim 7, characterized in that the key shunting the outputs of the second remote control is turned off with a delay relative to the key shunting the outputs of the first remote control, the switched current source of the third remote control turns on the current of the third remote control after turning off the key shunting the outputs of the second remote control, and the keys connecting the drains of the MOS transistors of the first conductivity type of the third remote control to their common source are also turned off after turning off the key bypassing the outputs of the second remote control. 9. Differential KN with sampling of the input differential signal according to claim 1, or 2, or 3, or 4, or 5, or 6, 7, or 8, characterized in that the outputs of the last remote control are connected through one of the inputs of two logical AND-NOT gates, the second inputs of which are cross-connected to their outputs, forming a trigger latch, and the gate outputs are direct and inverse KN outputs. 10. Differential CV with a sample of the input differential signal according to claim 1, or 2, or 3, or 4, or 5, or 6, 7, or 8, characterized in that in the remote control with input MOS transistors of the first type of conductivity, the slope of the second pairs of MOS transistors of the second type of conductivity are less than the steepness of the input MOS transistors and much less than the steepness of MOS transistors of the second type of conductivity of the first pair.

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