RU223472U1 - DEVICE FOR PROCESSING DESCRIPTORS AND PARALLEL SEARCHING FOR INTERNETWORK INTERACTION CANDIDATES - Google Patents

Abstract

The utility model relates to the field of computer technology and data transmission networks; it can be used for parallel search of elements in route maps of systems and data transmission networks, information retrieval systems, network databases, specialized tools for providing system or network reconfiguration by searching for elements by their descriptors to manage the configuration of a system or network. The technical task of the utility model is to expand the functionality by entering an additional mask bit for each sample element and processing descriptor fields based on the bit mask, which will allow you to search not only for full and partial occurrences, but also to exclude irrelevant data about the state of the network from the search. The technical problem is solved by introducing a matrix masked search block for occurrences and intersections of words into the characteristic matrix, which is the basis of the matrix search block for occurrences and intersections of words, which allows for a parallel search through the descriptors of network elements, taking into account the actual fields in the descriptor, highlighted by a mask. 4 ill.

Description

The utility model relates to computing systems, data networks with a variable composition of elements during operation and can be used for processing words describing the state of the network and parallel search for elements in route maps of data transmission systems and networks, information retrieval systems, network databases , specialized tools for providing system or network reconfiguration by searching for elements by their descriptors to manage the configuration of the system or network. A network element descriptor is a one-dimensional descriptive object containing bit sequences to control the state of the network and evaluate its configuration.

Let one-dimensional objects (words, strings) be given: O is a descriptor word (a pattern of n characters long), S is a network configurator (a configuration word of m characters long), where n>0 , m>0 and n<m . Let a bitmask M of length n bits be given. The mask is necessary for selecting (processing) descriptor symbols that are essential for organizing parallel search.

You need to find the positions of all complete occurrences of a patternO to configuration wordStaking into account the mask (hereinafter we will agree to name the occurrences according to the pattern), i.e. determine all position valuesi, at whichS(i, m+n-1) =O(1, n)∨(¬M[i])=1,where ¬ is the inversion operation, 1≤i≤n. It is also necessary to find the positions of all intersections of the pattern's own originO with its own ending of the configuration wordSincluding maskM(hereinafter we will agree to call “left intersections”), i.e. identify all suchi, for which (S(i, m) = O(1, m-i+1)∨(¬M[i])=1, where ¬ is the inversion operation,k+1≤ i<m,k=m-n+1, and it is necessary to find the positions of all intersections of the own end of the patternO with its own beginning of the configuration wordSincluding maskM(hereinafter we will agree to call “right intersections”), i.e. identify all suchi, for which (S(1, i) = O(n-i+1, n) )∨(¬M[i])=1, where ¬ is the inversion operation, 1≤i<n,. Processing of descriptor fields is carried out based on the logical operation of disjunction of the result of comparing the pattern symbolO with configuration word symbolS and inverse mask bitM.

Managing the configuration of a system or network, among other things, is based on the search and analysis of its elements whose descriptor fields contain target values. In this case, the target values, taking into account the impact of interference, may be inaccurate, and the fields themselves may be distributed according to the descriptor format. The search and subsequent processing of descriptors of system or network elements that take into account the variability of values is carried out on the basis of a parallel masked search for full and partial occurrences of the descriptor in the configuration word.

A device for searching arbitrary occurrences is known (patent No. RU 2202823 C2, MCP G06F17/30). The disadvantage of this device is the sequential way of processing text and indented pattern when handling partial occurrences.

A device for parallel search and processing of data is also known, consisting of two blocks for storing and comparing associative features, a memory block for logical vectors, an operation block and a matrix search block (patent No. RU 72771 U1, MKP G06F12/00), which performs parallel processing of a set of characteristic vectors , combined into a two-dimensional search matrix.

The disadvantage of this device is its limited functionality - the device only allows you to search for all occurrences of a pattern in the text. The characteristic search matrix has the geometric shape of a parallelogram, which does not allow this device to solve the problem of searching for intersections.

The closest to the claimed one is a device for parallel search for occurrences and intersections of words [Patent 2430408 Russian Federation, IPC G06F17/30. Device for parallel search for occurrences and intersections of words / E.A. Titenko, D.A. Voronin, V.S. Evsyukov, V.A. Semenikhin, M.Z. Nabil Imhammed, A.O. Atakischev, applicant and patent holder Kursk. state those. univ., publ. 09/27/2011, Bulletin. No. 27, 2011 - 14 pp.], which consists of constructing a rectangular binary matrix of comparisons of sample symbols and text of size n × m search cells. Search in the device comes down to parallel processing of full k ( k = m - n +1) matrix diagonals passing through all rows to form the resulting k -bit vector of occurrences, as well as parallel processing of partial (left and right) 2⋅( n - 1) diagonals of the matrix containing (1,2, ... n -1) elements.

However, this device cannot conduct a selective search for the necessary elements of the sample word (descriptor), which limits the use of the device for network configuration management.

The technical task of the utility model is to expand the functionality by entering an additional mask bit for each sample element and processing the sample fields based on the bit mask, which will allow you to search not only for full and partial occurrences, but also to exclude irrelevant data about the state of the network from the search.

The technical problem is solved by the fact that a device for processing descriptors and parallel search for candidates for internetworking, containing the first and second blocks for storing and comparing associative features, a memory block of logical vectors and an operating unit, wherein the information inputs of the first and second blocks for storing and comparing associative features are, respectively, the first and the second information inputs of the device, and the outputs of the storage and comparison blocks of associative features are connected, respectively, to the first and second address inputs of the logical vector memory block, the inputs for setting the modes of the first and second storage and comparison blocks of associative features and the write-read input of the logical vector memory block are respectively the first, second and third inputs for setting device modes, and the fourth, fifth, sixth inputs for setting device modes are respectively connected to three inputs of operation codes of the operating unit, the first output of which is the first output of the device, the first input of the initial setting of the device is connected to the initial setting input of the operating unit , the second input of the initial setting - to the inputs of the initial setting of the first and second blocks for storing and comparing associative features, the first and second outputs of the logical vector memory block are connected, respectively, to the first and second information inputs of the operating unit of the device, an additional block of matrix masked search for occurrences and intersections of words is introduced , having four inputs and three outputs, and the first input of the matrix masked search block for occurrences and intersections of words is connected to the first input of the initial installation of the device, the second input is connected to the second output of the operating unit, the third and fourth inputs of the matrix masked search for occurrences and intersections of words are, respectively, the third and fourth information inputs of the device, the first, second and third outputs of the matrix masked search block for occurrences and intersections of words are, respectively, the second, third and fourth outputs of the device. The matrix masked search block for occurrences and intersections of words contains one delay element,n pattern character code registers bit depthp+1 bit each character, where firstp bits are informational, andpThe +1st bit is the mask bit,m configuration word character code registers, bit depthp bits of each character, as well as a characteristic matrix consisting of search cells, the geometric shape of which is a rectangle of sizem*ncells wheren - sample length,m - length of the configuration word,k triggers of the position of occurrences, triggers of the position of intersection of the pattern with the configuration word, number 2*(n-1), among themn-1 position triggers “left intersections”, andn-1 triggers of the “right intersection” position, while each register of the pattern symbol code has three inputs (the first and second one-bit control inputs and the thirdp+1-bit input) and onep+1-bit output, each configuration word character code register has three inputs (the first and second one-bit control inputs and the thirdp-bit input) and onep-bit output, each search cell has three information inputs (the firstp+1-bit input and secondp-bit input, the third is a single-bit input) and one output, each trigger of the “left intersections” position and each trigger of the “right intersections” position has, respectively, three inputs (the first and second control inputs and the third information input) and one output, each search the cell contains a two-input equality comparison circuitp- bit codes of sample symbols and configuration words, consisting ofp two-input modulo-2 sum elements with inversion and one p-input AND element, one two-input AND element, as well as one two-input OR element having the first direct and second inverse inputs, the firstp+1 bit search cell inputsith line (i=1…n) connected top+1 bit outputsi-th sample character code register, secondp-bit input of search cellsjth column (j=1…m) connected top-bit outputjth register of the configuration word symbol code, output (i, j)th (i=2…n,j=2…m) of the search cell is connected to the third input (i-1, j-1)th search cell, output (i, j)th (i=1,j=1…k) search cell connected to the third inputjth trigger position entry, exit (i, j)th (i=1,j=k+1…m) of the search cell is connected to the third input (jk)-th trigger position “left intersections”, exit (i, j)th (i=2…n,j=1) the search cell is connected to the third input (i-1)-th position trigger “right intersections”, third input (i, j)th (i=n,j=1…m-1 Andi=1…n, j=m) search cell, i.e. the bottom line and right column of the characteristic matrix are intended to supply the initial value - logical “1” - to organize the search, the initial setting input is connected to the first inputn-1 triggers of the “left intersection” position, with the first inputn-1 position triggers “right intersections”, with the first inputn pattern character code registers andm configuration word symbol code registers, as well as with the first inputkoccurrence position triggers, the “Write Rows” input is connected to the second inputn pattern character code registers andm registers of the configuration word symbol code, as well as with the input of the delay element, the output of which is connected to the second inputn-1 triggers of the “left intersection” position, with a second inputn-1 triggers of the position “right intersections” and with the second inputktriggers position entries, exitsk entry position triggers,n-1 position triggers “left intersections” andn-1 triggers of the position "right intersections" are, accordingly, the firstk-bit, secondn-1 -bit and thirdn-1 - bit information outputs of the block of matrix masked search for occurrences and intersections of words, the third input of the block of matrix masked search of occurrences and intersections of words consists ofn groups byp+1st category each group, where the firstp digits encode the pattern symbol, andpThe +1st bit is a mask bit, andith group of digits (i=1…n) served on the thirdp+1-bit inputith register of the sample symbol code, the fourth input of the matrix masked search block for occurrences and intersections of words consists ofm groups of categories according top digits each group encoding the symbols of the configuration word, andjth group of digits (j=1…m) served on the thirdp-bit inputjth register of the configuration word symbol code, search cells containing two-input equality comparison circuits, each of which consists ofp two-input equality comparison elements (sum modulo 2 with inversion) and onep-input element AND, first inputl-th (l =1…p)comparison element connected tol-m rankp+1-bit sample character code register output, second inputl-th (l =1…p) comparison element connected tol-m rankp-bit output of the configuration word symbol code register, outputl-th (l =1…p) comparison element is connected tol-th entrancep-input element AND (l =1…p),the output of which is connected to the first input of a two-input OR element, the second inverse input of which is suppliedp+1st bit (mask bit) ofp+1-bit sample symbol code, the output of the two-input OR element is connected to the first input of the two-input AND element, the second input of which is connected to the third input of the search cell, the output of the two-input AND element is the output of the search cell.

The essence of the utility model is illustrated by drawings, where

in fig. Figure 1 shows a block diagram of a device for processing descriptors and parallel search for candidates for internetworking;

in fig. 2 - functional diagram of a block of matrix masked search for occurrences and intersections of words;

in fig. 3 - functional diagram of the search cell of the characteristic matrix;

in fig. 4 is an example of parallel masked search for occurrences and intersections of words.

The device for processing descriptors and parallel search for candidates for internetworking of words (Fig. 1) contains blocks 1 ₁ and 1 ₂ for storing and comparing associative features, block 2 of memory of logical vectors, operating block 3, block 4 of matrix masked search for occurrences and intersections of words, information inputs 4 ₁ , 4 ₂ , 4 ₃ and 4 ₄ , information outputs 5 ₁ -5 ₄ , inputs 6 ₁ -6 ₆ for setting the operating mode, inputs 7 ₁ and 7 ₂ for initial setting.

Blocks 1 ₁ , 1 ₂ , 2, 3 strictly correspond to the prototype device in structural and functional terms, consisting of matching elements and connections between them.

Block 4 (Fig. 2) of the matrix masked search for occurrences and intersections of words contains two control inputs: “Initial setting” 7 ₁ (first input) and the “Write strings” input (second input), the third and fourth information inputs for supplying sample symbols with mask and configuration word in parallel code through the information inputs 4 ₃ and 4 ₄ of the device, each symbol of the sample is accompanied by 1 bit of the mask, as well as three information outputs, which are the second 5 ₂ , third 5 ₃ and fourth 5 ₄ output of the device. In this case, the second control input of block 4 is connected to the second output of the operating block 3.

Block 4 of the matrix masked search for occurrences and intersections of words contains a delay element 31, consisting ofn pairs of inverters,n registers 32₁…32_n sample character codes,m registers 33₁…33_m configuration word character codes, characteristic matrix of search cells 34_eleven…34_nm,k triggers 37₁…37 _k entry positions,n-1 triggers 41₁…41 _n-1 “left intersection” positions,n-1 triggers 40₁…40 _n-1 positions “right intersections”, registers 32_i (i=1…n) and registers 33_j (j=1…m),which have first and second control inputs, register 32_i (i=1…n) has a thirdp+1-bit input and one output respectively, and the register is 33_j (j=1…m) has a thirdp-bit input and one output respectively. First and second entrancesn registers 32₁…32_n pattern character codes and first and second inputsm registers 33 codes of the configuration word symbols are connected, respectively, to the first and second control inputs of block 4 of the matrix masked search for occurrences and intersections of words, the third input of which has a bit width (p+1)⋅n bit is intended for parallel writing of a sample into registers 32₁…32 _n together withn bitmask and consists ofn groups of categories according top+1 bit each group encoding sample symbols and one mask bit, and
i-th group of digits(i=1…n) served on the thirdp+1-bit register 32 input _i (i=1…n), the fourth input of block 4 of the matrix masked search for occurrences and intersections of words with bit depthp⋅m the bit is intended for parallel writing of the configuration word to registers 33₁…33 _m and consists ofm groups of categories according top digits each group encoding the symbols of the configuration word, andj-th group of digits(j=1…m) served on the thirdp-bit input of register 33 _j (j=1…m). The second control input of block 4 of the matrix masked search for occurrences and intersections of words is also connected to the input of delay element 31.

The characteristic matrix of search cells 34 ₁₁ -34 _nm with a size of m×n cells has the shape of a rectangle, which provides the direction of a masked search along all diagonals passing through the cells as follows:

The lth (l= 1 ...n- 1 ) diagonal along which the search for “left intersections” occurs passes through l search cells 34 _ij , where i=l... 1 , j=m...m- l+ 1;

The f -th (f=n ... m) diagonal along which the search for occurrences occurs passes through n search cells 34 _ij , where i=n... 1 , j=m-f+n...m-f+ 1;

The g -th (g=m+ 1 ...m+n- 1 ) diagonal along which the search for “right intersections” occurs passes through n+mg search cells 34 _ij , where i=n...g-m+ 1 , j=g-n+ 1 ...m .

Firstp+1-bit inputsm search cellsi-th row of the characteristic matrix(i =1…n) connected top+1-bit register 32 output _i . Exitp-bit register 33 _j (j =1...m) connected to the secondp-bit inputs of all search cells included injth column of the matrix. Output of each search cell 34_ij, excepti =1, j =1..n (top row of the characteristic matrix), excepti=2..m, j =1 (left column of the characteristic matrix), connected to the third input of search cell 34 _{i -1 j -1}. Search cell 34 output _ij (i=2..m, j=1), located in the left column of the characteristic matrix, is connected to information input 3 of trigger 41 _{i -1} positions “left intersections”, output of search cell 34 _ij (i=1, j=1…k), located in the top row of the characteristic matrix, is connected to information input 3 of trigger 37 _j entry positions, search cell output 34 _ij (i=1, j=k+1...m), connected to information input 3 of trigger 40 _{j - k} positions "right intersections", the third input of each search cell located at the bottomn-th row of the matrix and in the rightmThe th column of the matrix is intended to supply a logical “1” value, thereby setting the initial value for searching along the corresponding diagonal from the bottom row of the characteristic matrix to its top row.

Search cell 34 _ij (Fig. 3) contains a two-input comparison circuit 35 _ij for equalityp- bit codes of sample symbols and configuration words, consisting ofp two-input elements 38 _l (l=1...p) comparison for equality (sum modulo 2 with inversion) and p-input element AND 39, two-input element OR 42, two-input element I36, first inputl-th (l =1…p)comparison element 38 connected tol-m rankp+1-bit register 32 output _i (i=1…n), second entrancel-th (l =1…p) comparison element 38 connected tol-m rankp-bit output of register 33 _i (i=1…m) , exitl-th (l =1…p) comparison element 38 connected tol-th input of element AND 39 (l =1…p),the output of which is connected to the first input of the two-input element OR 42, the second inverse input of which is suppliedp+1st bit (mask bit) ofp+1-bit register 32 output _i (i=1…n), the output of the two-input element OR 42 is connected to the first input of the two-input element AND 36, the second input of which is connected to the third input of the search cell 34 _ij , the output of two-input AND element 36 is the output of search cell 34 _ij .

Triggers 37₁-37 _k entry positions, triggers 41₁-41 _{n -1} “left intersection” positions, triggers 40₁-40 _{n -1} “right intersection” positions store the search result in the form, respectivelyk-bit,n-1 -bit,n-1 -bit codes, in which the logical value “1” marks the positions of the beginning of occurrences of the pattern in the configuration word, “left intersections” and “right intersections,” respectively. Triggers 37_i occurrence positions(i=1…k), triggers 41 _j “left intersection” positions(j =1..n-1), triggers 40 _j positions “right intersections”(j =1..n-1) contain three inputs (the first and second control ones, the third one-bit information input) and one output, respectively, each. The first input of block 4 of the matrix masked search for occurrences and intersections of words is connected to the first inputsk triggers 37 entry positions,n-1 triggers 41 positions “left intersections”,n-1 triggers 40 positions “right intersections”, second inputsk triggers 37 entry positions,n-1 triggers 41 positions “left intersections”,n-1 triggers 40 positions “right intersections” are connected to the output of the delay element 31. Trigger outputs 37₁-37 _k occurrence positions form the firstk-bit information output of block 4 of the matrix masked search for occurrences and intersections of words, trigger outputs 41₁-41 _{n -1} positions “left intersections” form the secondn-1-bit information output of block 4 of matrix masked search for occurrences and intersections of words, trigger outputs 40₁-40 _{n -1} positions “right intersections” form the thirdn-1-bit information output of block 4 of the matrix masked search for occurrences and intersections of words, which are respectively outputs 5₂, 5₃ and 5₄ devices.

This device, like the prototype device, operates in the “Record” and “Operation” modes. The “Record” mode strictly corresponds to the algorithm described in the prototype device.

In the algorithm of the “Operation” mode, the operation performed in the device is a masked “PVP” (masked search for the occurrence and intersection of words). To implement this additional functionality, the following additions are made to the “Operation” mode algorithm.

Let the device perform "Operation" mode with the masked "PVP" operation code. At input 7 ₁ “Initial setting” of block 4 of the matrix masked search for occurrences and intersections of words, an initial setting pulse signal is supplied, which resets k triggers 37 entry positions, n- 1 triggers 41 “left intersection” positions, n-1 triggers 40 positions “right intersections” at their input 1, n registers 32 at their input 1 and m registers 33 at their input 1. After the end of the initial installation signal, a pulse is applied to the second input “Write lines” of block 4 of the matrix masked search for occurrences and intersections of words signal from the operating unit. This pulse signal at the “Write Rows” input of block 4 of the masked matrix search for occurrences and intersections of words is supplied, respectively, to the second write permission inputs of n registers of 32 sample character codes with the nth mask and to the second write permission inputs of m registers of 33 configuration word character codes, thereby ensuring that n sample symbols are written together with the nth bit mask and m configuration word symbols in parallel code from inputs 4 ₃ and 4 ₄ of the device, respectively. Also, the pulse signal at the input “Write lines” of block 4 of the matrix masked search for occurrences and intersections of words through delay element 31 is supplied, respectively, to the second inputs of recording permission k flip-flops 37 entry positions, n- 1 triggers 41 “left intersection” positions, n- 1 flip-flops 40 “right intersection” positions. Delay element 31, made in the form of n pairs of inverters, is necessary to complete the processes of parallel search for occurrences and intersections along the diagonals of the characteristic matrix, consisting of search cells 34 ₁₁ -34 _nm .

The search process in the characteristic matrix of search cells 34 ₁₁ -34 _nm is described as follows.

The search begins with the cells of the bottom row and the right column of the characteristic matrix 34_eleven-34 _nm . Initial m-bit and n-bit characteristic vectors, equal respectively, are fed respectively to the third inputs of the search cells of the n-th (bottom) row of the matrix and to the third inputs of the search cells of the m-th (right) column of the characteristic matrix, which are connected to the input of logical 1, thereby determining the direction of parallel search along all diagonals of the characteristic matrix from the search cells of the bottom row and right column to the search cells of the top row and left column of the characteristic matrix, inclusive. To the first and second inputs of search cell 34_ij characteristic matrix is supplied (p+1)-bit code of the sample symbol andp-bit code of the configuration word symbol, respectively. Based on comparison scheme 35 _ij the first ones are compared for equalityp pattern character code bit andp bit of the configuration word symbol code. Comparison circuit 35 _ij for equality consists ofp two-input elements 38 comparisons for equality (sum modulo 2 with inversion) and onep-input element AND 39. The result of comparing two character codes is processedp+1st bit of the descriptor character code (mask bit) using two-input OR element 42. The first input of OR element 42 receives a bit of the result of comparing two character codes from circuit 35 _ij , the mask bit is received at the second (inverse) input of OR element 42. The result of the masked comparison is generated at the output of the two-input element OR 42, which is fed to the first input of the two-input element I35. The second input of the two-input element I35 is the third input of the search cell 34 _{i j}, which is connected to the search output 34 _{i -1 j -1}located along the diagonal of the characteristic matrix, excepti = 1,j = 1..n (top row of the characteristic matrix), excepti=2..m,j = 1 (left column of the characteristic matrix).

Upon completion of the masked search processes along all diagonals of the characteristic matrix, the pulse signal from the output of delay element 31 is recordedk-bit result of searching for the beginning of entries in flip-flops 37₁-37 _k occurrence positions, (n-1)-bit search result for “left intersections” in flip-flops 41₁…41 _{n -1}, (n-1) - bit result of the search for “right intersections” in triggers 40₁…40 _{n -1}. Trigger outputs 37₁…37 _k occurrence positions arek-bit output of block 4 of masked matrix search for occurrences and intersections of words and form the first output of device 5₂,n-1-bit trigger outputs 41₁…41 _{n -1} positions “left intersections” andn-1-bit trigger outputs 40₁…40 _{n -1} positions “right intersections” form the second and third outputs of device 5₃ and 5₄ respectively. Presence of logical 1s in the bits of information output 5₂ indicates the positions of occurrences of the descriptor in the configuration word. Presence of logical 1s in the bits of information output 5₃indicates the positions of the “right intersections” of the pattern with the configuration word. Presence of logical 1s in the bits of information output 5₄ indicates the positions of the “right intersections” of the pattern with the configuration word.

Execution of the algorithm in the “Operation” mode for other operations strictly corresponds to the prototype device

Thus, the expansion of the functionality of the device is achieved by introducing a bit mask and organizing a parallel masked search for occurrences and partial intersections of a sample and a configuration word.

Claims (1)

A device for processing descriptors and parallel search for candidates for internetworking, containing first and second blocks for storing and comparing associative features, a memory block of logical vectors and an operating unit, wherein the information inputs of the first and second blocks for storing and comparing associative features are, respectively, the first and second information inputs of the device, and the outputs of the storage and comparison blocks of associative features are connected, respectively, to the first and second address inputs of the logical vector memory block, the inputs for setting the modes of the first and second storage and comparison blocks of associative features and the write-read input of the logical vector memory block are the first, second and third inputs, respectively setting device modes, and the fourth, fifth, sixth inputs setting device modes are respectively connected to three inputs of operation codes of the operating unit, the first output of which is the first output of the device, the first input of the initial setting of the device is connected to the initial setting input of the operating unit, the second input of the initial setting is to the inputs of the initial installation of the first and second blocks for storing and comparing associative features, the first and second outputs of the logical vector memory block are connected, respectively, to the first and second information inputs of the operating unit of the device, characterized in that a block of matrix masked search for occurrences and intersections of words is additionally introduced, having four inputs and three outputs, the first input of the block of matrix masked search for occurrences and intersections of words is connected to the first input of the initial installation of the device, the second input is connected to the second output of the operating unit, the third and fourth inputs of the block of matrix masked search for occurrences and intersections of words are respectively the third and the fourth information inputs of the device, the first, second and third outputs of the matrix masked search block for occurrences and intersections of words are the second, third and fourth outputs of the device, respectively; the block of matrix masked search for occurrences and intersections of words contains one delay element, n registers of the sample symbol code with a width of p+1 bits each symbol, where the first p bits are informational, and the p+1th bit is a mask bit, m registers of the configuration word symbol code each symbol is p- bit wide, as well as a characteristic matrix consisting of search cells, the geometric shape of which is a rectangle of m*n cells in size, where n is the length of the sample, m is the length of the configuration word, k triggers of the position of occurrences, triggers of the position of the intersection of the sample with configuration word in the amount of 2*(n-1) , including n-1 flip-flops of the “left intersection” position, and n-1 flip-flops of the “right intersection” position, while each register of the sample symbol code has three inputs (the first and second one-bit control inputs and a third p+1 -bit input) and one p+1 -bit output, each configuration word character code register has three inputs (the first and second one-bit control inputs and the third p -bit input) and one p -bit output, each search cell has three information inputs (the first p+1 -bit input and the second p -bit input, the third is a single-bit input) and one output, each trigger of the “left intersections” position and each trigger of the “right intersections” position has three respectively input (the first and second control inputs and the third information input) and one output, each search cell contains a two-input comparison circuit for equality of p -bit codes of the sample symbols and the configuration word, one two-input AND element, as well as one two-input OR element having the first direct and the second inverse inputs, a two-input equality comparison circuit consists of p two-input equality comparison elements (modulo 2 sum with inversion) and one p -input AND element, the first p+ 1-bit inputs of search cells of the i -th row (i=1... n) are connected to p+1 bits of the output of the i -th register of the sample symbol code, the second p -bit input of the search cells of the j -th column (j=1...m) is connected to the p -bit output of the j -th register of the configuration word symbol code, the output (i, j) -th ( i =2…n, j=2…m) search cell is connected to the third input (i-1, j-1) -th search cell, output (i, j) -th ( i=1, j=1…k) of the search cell is connected to the third input of the j -th trigger of the occurrence position, the output (i, j) of the (i=1, j=k+1…m) search cell is connected to the third input (jk) -th trigger of the “left intersections” position, the output of the (i, j) -th (i=2…n, j=1) search cell is connected to the third input (i-1) of the (i-1) -th trigger of the “right intersections” position , the third input (i, j) is the th (i=n, j=1…m-1 and i=1…n, j=m) search cell, i.e. the bottom row and right column of the characteristic matrix are intended to supply the initial value - logical 1 - to organize the search, the initial setting input is connected to the first input of n-1 triggers of the “left intersection” position, with the first input of n-1 triggers of the “right intersection” position , with the first input of n sample symbol code registers and m configuration word symbol code registers, as well as with the first input of k occurrence position triggers, the Write Strings input is connected to the second input of n sample symbol code registers and m configuration word symbol code registers, as well as with input of a delay element, the output of which is connected to the second input of n-1 flip-flops of the “left intersection” position, with the second input of n-1 triggers of the “right intersection” position and to the second input of k flip-flops of the entry position, outputs of k flip-flops of the entry position, n-1 triggers of the “left intersections” position and n-1 triggers of the “right intersections” position are respectively the first k -bit, second n-1 -bit and third -bit information outputs of the matrix masked search block for occurrences and intersections of words, the third input of the matrix masked search block occurrences and intersections of words consists of n groups of p+1 digits each group, where the first p digits encode the sample symbol, and the p+1th digit is a mask bit, and the i -th group of digits (i=1...n) is supplied to the third p+1 -bit input of the i -th register of the sample symbol code, the fourth input of the block of matrix masked search for occurrences and intersections of words consists of m groups of bits with p bits each group encoding the symbols of the configuration word, and the j -th group of bits (j= 1…m) is fed to the third p -bit input of the j -th register of the configuration word symbol code, search cells containing p two-input comparison elements (sum modulo 2 with inversion), the first input of the l-th (l=1…p) element comparison element is connected to the l-th digit of the p+1 -bit output of the sample symbol code register, the second input of the l-th (l=1...p) comparison element is connected to the l-th digit of the p -bit output of the configuration word symbol code register, output l -th (l=1...p) comparison element is connected to the l-th input of the p -input element AND ( l=1...p ), the output of which is connected to the first input of the two-input OR element, the second inverse input of which is supplied with p+1- th bit (mask bit) from the p+1 -bit code of the sample symbol, the output of the two-input OR element is connected to the first input of the two-input AND element, the second input of which is connected to the third input of the search cell, the output of the two-input AND element is the output of the search cell.