RU2233540C2 - Device and method for converting tfci indicator bits into characters for fixed division mode in cdma mobile communication system - Google Patents

Abstract

FIELD: data transfer systems.

SUBSTANCE: proposed method and device are designed to display coded TFCI characters for transmission over physical channel in CDMA mobile communication system. First and second coded TFCI characters are multiplexed so as to uniformly distribute them in compliance with mode of frame data transmission and speed, coded character output, and multiplexed coded character display in frame adhering to number of coded characters that can be displayed in one frame defined according to frame data transfer mode and speed. Proposed device has at least one coder for coding first TFCI bits at first coding speed to output first coded TFCI characters and for coding second TFCI bits at second coding speed to output second coded TFCI characters; coded character linkage editor for multiplexing coded characters so as to provide for uniform distribution of mentioned first and second TFCI characters in compliance with data frame transmission mode and speed for outputting mentioned multiplexed coded characters.

EFFECT: provision for displaying coded characters for sending them over physical channel in mobile code-division multiple access communication system.

22 cl, 20 dwg, 7 tbl

Description

A PRIORITY

This application claims the priority of the application entitled "Device and method for converting TFCI pointer bits to hard split mode in the CDMA mobile communication system" registered with the Korean Industrial Property Protection Authority on July 9, 2001 under No. 2001-44673, the application entitled " A device and method for converting TFCI pointer bits to hard symbols in the CDMA mobile communication system "registered with the Korean Industrial Property Protection Authority on August 25, 2001 under No. 2001-5160 5 and the application entitled “Device and method for converting TFCI pointer bits to hard-split mode characters in a CDMA mobile communication system” registered with the Korean Industrial Property Protection Authority on August 29, 2001 under No. 2001-52596, the contents of which are incorporated by reference in this description.

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The present invention generally relates to a transmission apparatus and method for hard split mode in a CDMA mobile communication system (CDMA) and, in particular, to a conversion apparatus and method for transmitting TFCI (Transport Format Combination) indicator bits Indicator, transport format association pointer, FFEP).

State of the art

In the general case, the downlink shared channel (DSCH, Downlink Shared Channel) is shared by multiple users based on time sharing. The DSCH channel is established together with a dedicated VK channel (DCH, Dedicated Channel) for each user. The signal of the DCH channel is transmitted through the dedicated physical channel of the VFK (DPCH, Dedicated Physical Control Channel), and the signal of the channel DPCH is formed by combining the dedicated physical control channel of the VFKU (DPCCH, Dedicated Physical Control Channel) and the dedicated physical channel of the VFKD data (DPDCH, Dedicated Physical Data Channel ) based on time division.

A DSCH channel signal is transmitted on a Physical Downlink Shared Channel (PDSCH), and channel control information for a PDSCH is transmitted on a DPCCH in a DPCH. The control information transmitted over the DPCCH includes information about: (i) a Transmitted Power Control (Transmitted Power Control) command for controlling uplink transmission power from user equipment; (ii) a pilot signal field used to evaluate changes in channel characteristics, measure transmit power, and set synchronization over time intervals (slots) and transmitted from Node B to user equipment; and (iii) a TFCI indicator. From this information, the TPC command and the pilot are used as physical control information for the PDSCH and DPCH, and the TFCI is used to indicate information characteristics (e.g., information transfer rate and a combination of various information, i.e., a combination of voice information and packet information) for data transmitted on the channel DSCH and DPDCH.

As described above, the TFCI indicator, that is, control information indicating information characteristics for data transmitted on the physical channels DSCH and DPDCH, is 10 bits long and is encoded in 32 bits. That is, information about the amount of data is expressed in 10 bits, and 10-bit information is encoded in 32 bits transmitted over the physical channel.

Index TFCI is transmitted over the physical channel using the following method described in the specification standard 25.212 3GPP (3 ^rd Generation Partnership Project, partnership in third generation mobile networks) for the UMTS system (Universal Mobile Telecommunication System, Universal Mobile Telecommunications System).

a _k = k-th information bit of information about the transport combination (0≤k≤9),

b ₁ = 1st encoded bit of transport combination information (0≤1≤31),

d _m = mth transmitted encoded bit of transport combination information.

a _k is 10-bit information indicating the transmission rate, type and combination of data transmitted over the DPDCH; b ₁ consists of 32 encoded bits obtained by encoding a _k ; and d _m represents transmitted encoded bits when b ₁ is transmitted on the DPCCH. Here, the value of m varies in accordance with certain conditions.

The conditions for determining the number of bits d _{m are} determined based on the transmission mode on the DPCCH and the data rate on the DPCH. The transmission mode for the DPCCH includes a conventional transmission mode and a compressed transmission mode. The compressed transmission mode is used when user equipment having one radio frequency transceiver is about to measure in a different frequency band. When operating in compressed transmission mode, transmission in the current frequency band is temporarily stopped, allowing the user equipment to measure in a different frequency band. Data to be transmitted during the period of termination of transmission is compressed immediately before and after the said period of temporary termination of transmission.

A “DPCH data rate”, which is one of the conditions for determining the number of bits d _m , refers to the physical data rate of the DPCH and is determined in accordance with the data expansion coefficient (RS). The expansion coefficient varies in the range from 4 to 512, and the data transfer rate varies in the range from 15 Kbps to 1920 Kbps. When the expansion coefficient increases, the data rate decreases. The reason for determining the number of bits d _m in accordance with the data rate of the DPCH is because the size (or length) of the TFCI field transmitting the TFCI bits of the DPCCH changes in accordance with the data rate of the DPCH.

The number of bits d _m transmitted if each of the conditions for determining d _m is present is calculated as follows.

A1. Normal transfer mode, DPCH data transfer rate below 60 Kbps

In the case of condition A1 for determining the number of bits d _m , the number of bits d _m becomes equal to 30. In the 3GPP standard, the main block of transmission over the physical channel is a radio frame. The radio frame is 10 ms long and contains 15 time slots. Each time slot has fields for transmitting the TFCI. In the case of condition A1, each time interval (slot) contains 2 TFCI pointer transmission fields, as a result of which the number of code bits d _m for transmitting the TFCI pointer that can be transmitted in one radio frame becomes 30. Thus, although the number of coded bits is b ₁ obtained on the basis of information bits a _k is 32, the last two bits b ₃₀ and b _{31 of the} information about the transport combination are not transmitted due to the limitation on the number of actually transmitted fields of the TFCI pointer.

A2. Normal transfer mode, DPCH data transfer rate above 60 Kbps

In the case of condition A2 for determining the number of bits d _{m, the} length of the TFCI field in the time interval is 8 bits and the total number of bits d _m that can be transmitted on the DPCCH in one radio frame becomes 120. When the total number of bits d _m is 120, the bits b _{1 are} repeated in the following way:

d ₀ (b ₀ ), ..., d ₃₁ (b ₃₁ ), d ₃₂ (b ₀ ), ..., d ₆₃ (b ₃₁ ), ..., d ₉₆ (b ₀ ), ... , d ₁₁₉ (b ₂₃ )

In the case of condition A2, during transmission, bits b ₁ from the 0th to the 23rd are repeated 4 times, and bits b ₁ from the 24th to the 31st are repeated 3 times.

A3. Packed mode, DPCH data transfer rate below 60 Kbps or equal to 120 Kbps

In the case of condition A3 for determining the number of bits d _{m, the} length of the TFCI field in the time interval is 4 bits, and the number of TFCI fields that can be transmitted in one radio frame changes according to the number of time intervals used in the compressed transmission mode. In compressed transmission mode, the number of time slots in the period of temporary cessation of transmission varies from a minimum of 1 to a maximum of 7 and the number of bits d _m varies from 32 to 56. The number of transmitted encoded bits d _{m is} limited to a maximum of 32, as a result of which all bits are transmitted b ₁ from the 0th to the 31st in this changed number of bits d _m and bits b _{1 are} not transmitted in the case of other numbers of bits d _m .

A4. Compressed mode, DPCH data transfer rate above 120 Kbps or equal to 60 Kbps

In the case of condition A4, for determining the number of bits d _{m, the} length of the TFCI field in the time interval is 16 bits, and the number of TFCI fields that can be transmitted in one radio frame varies according to the number of time intervals used in the compressed transmission mode. In compressed transmission mode, the number of time slots under conditions of temporary suspension of transmission varies from a minimum of 1 to a maximum of 7, and the number of bits d _m varies from 128 to 244. The number of transmitted encoded bits d _{m is} limited to a maximum of 128, resulting in bits b ₁ from the 0th to the 31st are transmitted 4 times in this changed number of bits d _m and bits b _{1 are} not transmitted in the case of other numbers of bits d _m .

In the compressed transmission mode, in the presence of conditions A3 and A4, bits d _m are placed in a period spaced as far as possible from the period of temporary suspension of transmission in order to maximize the reliability of the transmission of bits d _m .

Conditions A1, A2, A3, and A4 are used when the TFCI indicates the transport combination and the type of DPCH. The method of dividing the TFCI by TFCI for the DSCH and the TFCI for the DPCH during transmission can be divided into two separate methods.

The first method is for hard partitioning ((RLR), HSM, Hard Split Mode), and the second method is for logical partitioning ((RLR), LSM, Logical Split Mode).

The TFCI for the BCH (DCH) will be called the TFCI (field 1) or the first TFCI, and the TFCI for the DSCH (DSCH) will be called the TFCI (field 2) or the second TFCI.

In the LSM method, the TFCI indicator (field 1) and the TFCI indicator (field 2), as a single TFCI indicator, are encoded using a second-order Reed-Muller code subcode (32.10). The TFCI (field 1) and TFCI (field 2) pointers express 10-bit TFCI information in various ratios, and 10 information bits are encoded into one block before transmission, i.e. sub-code (32.10) of the second-order Reed-Muller code corresponding to conditions A1, A2, A3 and A4. The bit ratios in the TFCI (field 1) and TFCI (field 2) indicators include 1: 9, 2: 8, 3: 7, 4: 6, 5: 5, 6: 4, 7: 3, 8: 2, and 9: 1. The sum of the information bits of the first TFCI and information bits of the second TFCI may be less than 10. In the LSM method, if the sum of the information bits of the first TFCI and information bits of the second TFCI is less than 10, then the number of zeros equal to the number of missing bits is inserted. As a result, the information bits of the first TFCI and the information bits of the second TFCI can be encoded using the Reed-Muller code (32.10) before transmission.

In the HSM method, the TFCI (field 1) and TFCI (field 2) indicators are fixed in 5 bits, respectively, and each information is generated using a binary orthogonal code (16.5), followed by 16 bits for the TFCI indicator (field 1) and the TFCI indicator (field 2) are transmitted alternately in accordance with conditions A1, A2, A3 and A4. When the maximum number of information bits of the first TFCI and the maximum number of information bits of the second TFCI are both limited to 5, if the number of information bits of the first TFCI or information bits of the second TFCI is greater than 5, then the HSM method cannot be used. Therefore, if the number of information bits of the first TFCI or information bits of the second TFCI is less than 5, the number of zeros equal to the number of empty bits is inserted before encoding using the binary orthogonal code (16.5).

Figure 1 shows a block diagram of a transmitter whose operation is based on the use of the conventional HSM method. As shown in FIG. 1, an encoder 100 for binary orthogonal encoding (16.5) encodes a 5-bit TFCI pointer (field 1) for a 16-coded DCH channel and feeds these 16 coded characters to a multiplexer 110. In the same the time encoder 105 for encoding in binary orthogonal code (16.5) encodes a 5-bit TFCI pointer (field 2) for the DSCH channel into 16 encoded symbols and provides these 16 encoded symbols to multiplexer 110. Then, multiplexer 110 time-multiplexes 16 encoded symbols received from encoder 100 and 16 encoded characters fishing received from the encoder 105, and after linking displays 32 characters. Multiplexer 120 time-multiplexes 32 symbols from multiplexer 110 and other signals and provides a result to expander 130. Expander 130 expands the output of multiplexer 120 using an spreading code coming from spreading code generator 135. The scrambler 140 encrypts the extended signal with a scrambling code coming from the scrambling code generator 145.

If the user equipment is in the handover area, the LSM method has many limitations for the following reasons. For convenience of explanation, a brief description of the 3GPP wireless transmission network is provided below. A radio access network (RAN, Radio Access Network) consists of a radio network controller (RNC, Radio Network Controller), a Node B managed by an RNC, and user equipment. The RNC controller controls the Node B, the Node B serves as a base station, and the user equipment operates as a terminal. The RNC controller can be divided into a Serving Radio Network Controller (SRNC) serving radio network controller and a Control Radio Network Controller (CRNC), according to their relationship with user equipment. The SRNC controller, that is, the RNC controller in which the user equipment is registered, processes the data to be transmitted to or received from the user equipment, and controls the user equipment. The CRNC controller, that is, the RNC controller to which the user equipment is currently connected, connects the user equipment to the SRNC controller.

When Nodes B are in communication with user equipment, they belong to different RNC controllers, Nodes B that do not transmit a DSCH channel signal cannot recognize the value of TFCI coded bits for DSCH, as a result of which it is impossible to correctly transmit TFCI coded bits to user equipment.

In the above HSM method, the TFCI information bits for the DSCH channel and the TFCI information bits for the DCH channel are independently encoded, so it is not difficult for the user equipment to decode the received TFCI bits. However, in the existing HSM method for 3GPP, the number of TFCI bits for the DCH and the number of TFCI bits for the DSCH are both hard coded to 5 bits to express 32 information bits. Therefore, when more TFCI bits are required for the DCH or DSCH, the HSM method cannot be used.

SUMMARY OF THE INVENTION

Thus, it is an object of the present invention to provide an apparatus and method for transmitting / receiving TFCI bits in a CDMA mobile communication system.

Another objective of the present invention is to provide a device and method for converting (displaying) encoded TFCI symbols for transmission over a physical channel in a CDMA mobile communication system.

A further object of the present invention is to provide an apparatus and method for converting coded TFCI symbols for a DCH channel and coded TFCI symbols for a DSCH channel, separated in a predetermined ratio, for transmission over a physical channel in a CDMA mobile communication system.

A further object of the present invention is to provide an apparatus and method for receiving TFCI encoded symbols converted for transmission over a physical channel before transmission in a CDMA mobile communication system.

A further object of the present invention is to provide an apparatus and method for receiving TFCI encoded symbols for a DCH and TFCI encoded symbols for a DSCH, separated in a specific ratio, converted for transmission over a physical channel before transmission in a CDMA mobile communication system.

According to a first aspect of the present invention, there is provided a method for mapping first encoded TFCI symbols and second encoded TFCI symbols into a radio frame in a transmitter of a mobile communication system for encoding the first k bits of TFCI and second (10-k) bits of TFCI, the sum of the first encoded symbols TFCI and the second encoded TFCI symbols is 32. The method comprises multiplexing the encoded symbols such that the first encoded TFCI symbols and the second encoded TFCI symbols are uniformly distributed are allocated in accordance with the transmission mode and data rate of the radio frame, and the output of 32 encoded characters; the conversion of 32 multiplexed encoded symbols into a radio frame in compliance with the number of encoded symbols that can be placed in one radio frame, and this number is determined in accordance with the transmission mode and data rate of the radio frame.

In accordance with a second aspect of the present invention, there is provided an apparatus for transmitting first TFCI bits and second TFCI bits in a radio frame of a transmitter of a mobile communication system. Said device comprises at least one encoder designed to encode the k first TFCI bits with a first coding rate to output (3k + 1) the first TFCI encoded symbols and encode (10-k) the second TFCI bits with a second coding rate for output (31-3k) second coded TFCI symbols; a coded symbol compiler for multiplexing coded symbols such that the first TFCI encoded symbols and the second TFCI encoded symbols are evenly distributed in accordance with a transmission mode and a data rate of a radio frame, and outputting multiplexed encoded symbols corresponding to the number of encoded symbols that can be transmitted in one radio frame.

According to a third aspect of the present invention, there is provided a method for transmitting first TFCI bits and second TFCI bits in a radio frame in a transmitter of a mobile communication system. Said method comprises encoding k first TFCI bits with a first coding rate to output (3k + 1) first encoded TFCI symbols; encoding (10-k) the second TFCI bits with a second coding rate to output (31-3k) the second encoded TFCI symbols; a coded character composer (for multiplexing coded characters) such that the first coded TFCI characters and the second coded TFCI characters are evenly distributed in accordance with a transmission mode and a data rate of a radio frame; output multiplexed encoded characters corresponding to the number of encoded characters that can be transmitted in one radio frame.

According to a fourth aspect of the present invention, there is provided an apparatus for decoding k first TFCI bits and (10-k) second TFCI bits in a receiver of a mobile communication system for receiving (3k-1) first TFCI encoded symbols for a DCH (dedicated) channel) and (31-3k) of the second TFCI encoded symbols for the DSCH (common downlink channel). Said device comprises a coded symbol remover intended to separate, in accordance with a value of k, the first encoded TFCI symbols and the second encoded TFCI symbols transmitted on the DPCH (dedicated physical channel) for recomposition and at least one decoder, for decoding the first TFCI encoded symbols to output k first TFCI bits and decoding the second TFCI encoded symbols to output (10-k) second TFCI bits.

According to a fifth aspect of the present invention, there is provided a method of decoding k first TFCI bits and (10-k) second TFCI bits in a receiver of a mobile communication system for receiving (3k-1) first TFCI encoded symbols for a DCH (dedicated channel) and (31-3k) second TFCI encoded symbols for the DSCH (common downlink channel). Said method comprises the step of separating, in accordance with the value of k, the first encoded TFCI symbols and the second encoded TFCI pointer symbols transmitted on the DPCH (dedicated physical channel) for the purpose of re-arrangement; and decoding the first encoded TFCI symbols to output k first TFCI bits; and decoding the second TFCI encoded symbols to output (10-k) second TFCI bits.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objectives, features and advantages of the present invention will become more apparent from the following detailed description when considered in conjunction with the accompanying drawings, in which

figure 1 shows a block diagram of a conventional transmitter based on the use of hard split mode (HSM);

figure 2 shows a structural diagram of a transmitter located in the Node In, corresponding to one embodiment of the present invention;

Fig. 3 shows another structural diagram of a transmitter located in the Node B corresponding to one embodiment of the present invention; Fig. 4 shows a detailed structural diagram of the encoder shown in Figs. 2 and 3;

5 illustrates a structure of a downlink radio frame transmitted from a Node B to a user equipment;

FIG. 6 is a detailed block diagram of the symbol builder shown in FIG. 2;

Fig.7 shows a detailed structural diagram of the selector shown in Fig.3;

on Fig shows another detailed structural diagram of the linker shown in figure 3;

figure 9 shows a structural diagram located in the user equipment of the receiver, corresponding to one embodiment of the present invention;

figure 10 shows another structural diagram located in the user equipment of the receiver corresponding to another embodiment of the present invention;

figure 11 shows the detailed structure of the decoder used in the receiver shown in figure 10;

12 illustrates a method for selecting codes used for a first TFCI and a second TFCI in accordance with one embodiment of the present invention;

on Fig depicts another embodiment of the connection of the encoders and the linker in accordance with one embodiment of the present invention;

on Fig depicts another embodiment of the connection of the encoder and the linker in accordance with one embodiment of the present invention;

on Fig depicts the following embodiment of the connection of the encoder and the linker in accordance with one embodiment of the present invention;

Fig. 16 illustrates an encoding operation in accordance with one embodiment of the present invention;

on Fig depicts a decoding operation corresponding to one embodiment of the present invention;

on figa and 18B depict two different structural diagrams of the symbol builder, corresponding to one of the embodiments of the present invention;

on Fig depicts a structural diagram of a linker encoded characters corresponding to one embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

A preferred embodiment of the present invention is described below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not considered in detail, since they may complicate the understanding of the invention due to the description of parts that are not necessary.

The present invention provides a device and method for dividing a total of 10 input information bits into information bits for a DCH channel and information bits for a DSCH channel in a ratio of 1: 9, 2: 8, 3: 7, 4: 6, 5: 5, 6: 4, 7: 3, 8: 2 or 9: 1 in the HSM method, followed by separate coding of information bits for the DCH channel and information bits for the DSCH channel. If the sum of the number of information bits of the first TFCI and the number of information bits of the second TFCI is less than 10, then the device and method corresponding to one embodiment of the present invention increase the reliability of the information bits of the first TFCI or information bits of the second TFCI before encoding. Alternatively, said apparatus and method improves the reliability of both the information bits of the first TFCI and the information bits of the second TFCI before encoding.

First, a description is given of the encoder for the case where the sum of the information bits of the first TFCI and information bits of the second TFCI is 10.

In one radio frame, in accordance with the conditions A1, A2, A3 and A4, 30, 120, 32 and 128 coded TFCI symbols are transmitted, respectively. In each case, not taking into account the retransmission, the basic coding rate is 10/32, and if condition A1 is present, the coding rate becomes 10/30 due to the limited transmission on the physical channel. Thus, when the information bits of the TFCI indicator for the DSCH channel and the information bits of the TFCI indicator for the DCH channel are separated in a specific ratio of 1: 9, 2: 8, 3: 7, 4: 6, 5: 5, 6: 4, 7: 3 , 8: 2 or 9: 1, it is natural to maintain the coding rate by separating the encoded characters in the above ratios. Saving the coding rate means maintaining the basic coding rate (32, 10). In the HSM method, the reason for maintaining the processing gain by coding for the differently coded TFCIs for the DSCH and the TFCIs for the DCH is to save the processing gains by coding by simply maintaining the coding rate (32, 10), despite the fact that the TFCI for the DSCH and the TFCI for the DCH are separately encoded. An example of separation of coded bits in accordance with the ratio of input bits is described for the case of condition A1.

In case of condition A1, if 10 input information bits are divided in a ratio of 1: 9, then 30 encoded output symbols are divided in a ratio of 3:27, and if 10 input information bits are divided in a ratio of 2: 8, then 30 encoded output symbols are divided in a ratio 6:24 a.m. Further, if 10 input information bits are divided in a ratio of 3: 7, then 30 encoded output symbols are divided in a ratio of 9:21, and if 10 input information bits are divided in a ratio of 4: 6, then 30 encoded output symbols are divided in a ratio of 12:18 . However, in cases of conditions A2, A3 and A4, 32 encoded characters are transmitted in full or 32 encoded characters are transmitted repeatedly (in a repeating manner), therefore, encoded characters cannot be separated correctly, as in the case of condition A1.

Thus, in this embodiment of the present invention, the coding rates for coded symbols determined based on the ratio of the input bits can be calculated, as shown in Table 1.

The criterion for determining the encoding rates shown in Table 1 in accordance with the ratio of the input bits is described below. In this embodiment of the present invention, the sum of the coded symbols is set to 30 by using the minimum required value of the real coding rate (30, 10) for the most frequently used case A1 from conditions A1, A2, A3 and A4 and setting the coding rate of the first TFCI and coding rate the second TFCI pointer to the minimum value 1/3, and then the remaining 2 encoded characters are allocated respectively to the encoded character of the first TFCI pointer and the encoded character of the second pointer for TFCI. Thus, in this embodiment of the present invention, both the coding rate of the first TFCI and the coding rate of the second TFCI are increased, or either the coding rate of the first TFCI or the coding rate of the second TFCI is increased by using the remaining 2 encoded characters as encoded characters of the first TFCI or encoded characters of the second TFCI. In this embodiment of the present invention, when determining coding rates, the coding rate of either the first TFCI or the second TFCI is increased when it is necessary to increase efficiency by increasing only the coding speed of the first TFCI or the coding rate of the second TFCI, provided that the sum of the number of encoded characters for the first TFCI and the number of coded symbols for the second TFCI should be 32.

After the ratio of the input bits is shown in Table 1, one of the 3 encoding methods is used in accordance with the ratio of encoded characters.

The present invention proposes an encoder capable of encoding at all speeds shown in Table 1. As shown in Table 1, if the ratio of the input bits (or the ratio of the volumes of information, that is, the ratio of the bits of the first TFCI to bits of the second TFCI) is 1: 9 , the ratio of encoded characters becomes equal to 3:29, 4:28 or 5:27. If the ratio of input bits is 2: 8, the ratio of encoded characters becomes 6:26, 7:25 or 8:24, and if the ratio of input bits is 3: 7, the ratio of encoded characters becomes 9:23, 10:22 or 11 : 21. If the ratio of input bits is 4: 6, the ratio of encoded characters becomes 12:20, 13:19, or 14:18. If the ratio of input bits is 6: 4, the ratio of encoded characters becomes 18:14, 19:13 or 20:12, and if the ratio of input bits is 7: 3, the ratio of encoded characters becomes 21:11, 22:10 or 23 :9. If the ratio of input bits is 8: 2, the ratio of encoded characters becomes 24: 8, 25: 7 or 26: 6, and if the ratio of input bits is 9: 1, the ratio of encoded characters becomes 27: 5, 28: 4 or 29 : 3.

Therefore, if the ratio of the input bits is 1: 9, then {encoder (3, 1), encoder (29, 9), encoder (4, 1) and encoder (28, 9)} or {encoder (5, 1) are required and encoder (27, 9)}. If the input bit ratio is 2: 8, then {encoder (6, 2), encoder (26, 8), encoder (7, 2) and encoder (25, 8)} or {encoder (8, 2) and encoder are required (24, 8)}. If the input bit ratio is 3: 7, then {encoder (9, 3), encoder (23, 7), encoder (10, 3) and encoder (22, 7)} or {encoder (11, 3) and encoder are required (21, 7)}. If the input bit ratio is 4: 6, then {encoder (12, 4), encoder (20, 6), encoder (13, 4) and encoder (19, 6)} or {encoder (14, 4) and encoder are required (18, 6)}. Thus, taking into account 24 encoders and currently used encoder (16, 5) and encoder (32, 10), there is a need for an encoder capable of working as 18 encoders with one structure in order to increase work efficiency and reduce complexity hardware.

In the general case, a measure of the effectiveness of linear error-correcting codes can be the distribution of Hamming distances for the code words of error-correcting codes. Hamming distance is the number of non-zero characters in the codeword. That is, if for some word “0111” the number of units contained in the word is 3, then the Hamming distance is 3. The smallest of the Hamming distances is called the “minimum distance d _min ”, and increasing the minimum distance in the code word increases the error correction efficiency for error correction codes. In other words, “optimal code” means a code having optimal error correction efficiency. This is described in detail in the article "Theory of Error Correcting Codes" by F.J. Macwilliams, N.J. A. Sloane, NJASloane, North-Holland.

In addition, in order to reduce the complexity of the hardware, using a single encoder block diagram for encoders generating codewords of different lengths, it is preferable to shorten the code having the longest length, i.e. code (32, 10). For shortening it is necessary to "perforate" coded characters. However, during “punching”, said minimum distance for the code changes in accordance with the “punching” positions. Therefore, it is preferable to calculate the “punch” positions so that the “perforated” code has a minimum distance.

For example, from the point of view of ensuring a minimum distance, it is most preferable to use the optimal code (7, 2) having one of the coding rates shown in Table 1 and obtained by repeating the simplex code (3, 2) three times and then punching (deleting) the last two coded characters. Table 2 shows the relationship between the input information bits of a simplex code (3, 2) and the output simplex codewords obtained on their basis (3, 2).

Table 3 shows the relationship between the input information bits and simplex codewords (7, 2), obtained by repeating the simplex words (3, 2) three times and then punching the last two encoded characters.

However, simplex codewords (7, 2) obtained by repeating three times simplex codewords (3, 2) and then punching the last two encoded characters can be created by shortening the existing Reed-Muller code (16, 4).

First, a shortening method is described as an example. The Reed-Muller code (16, 4) is a linear combination of 4 basic code words of length 16, where "4" is the number of input information bits. Reception of only 2 bits of 16 input information bits is equivalent to using a linear combination of only 2 basic codewords of 4 basic codewords of length 16 and not using the remaining codewords. In addition, by restricting the use of basic codewords and then punching 9 characters out of 16, it is possible to implement an encoder (7, 2) using an encoder (16, 4). The shortening method is illustrated in Table 4.

As shown in Table 4, each codeword (16, 4) is a linear combination of 4 bold basic codewords of length 16. To obtain the code (6, 2), only the top 2 codewords of 4 basic codewords are used. Then the remaining lower 12 codewords are automatically unused. Therefore, only the top 4 codewords are used. In addition, to generate a base codeword of length 7 using the top 4 base codewords, you must perforate 9 characters. You can get simplex codewords (7, 2) shown in Table 3 by punching the characters indicated by (*) in Table 4 and then assembling the remaining 7 coded characters.

Below will be described the structural diagram of the encoder designed to create {optimal code (3, 1), optimal code (29, 9), optimal code (4, 1) and optimal code (28, 9)} and {optimal code (5, 1) and the optimal code (27, 9)} used for the ratio of information bits 1: 9; block diagram of an encoder designed to create {optimal code (6, 2), optimal code (26, 8), optimal code (7, 2) and optimal code (25, 8)} and {optimal code (8, 2) and optimal code (24, 8)} used for the ratio of information bits 2: 8; block diagram of an encoder designed to create {optimal code (9, 3), optimal code (23, 7), optimal code (10, 3) and optimal code (22, 7)} and {optimal code (11, 3) and optimal code (21, 7)} used for the ratio of information bits 3: 7; block diagram of an encoder designed to generate {optimal code (12, 4), optimal code (20, 6), optimal code (13, 4) and optimal code (19, 6)} and {optimal code (14, 4) and optimal code (18, 6)} used for the ratio of information bits 4: 6; and a block diagram of an encoder designed to create an optimal code (16, 5) and an optimal code (32, 10) used to correlate information bits 5: 5 by shortening the subcode (32, 10) of the second-order Reed-Muller code. In addition, a block diagram of a decoder corresponding to an encoder will also be described.

1. The first embodiment of the transmitter

One embodiment of the present invention provides a device and method for separating 10 information bits in a ratio of 1: 9, 2: 8, 3: 7, 4: 6, 5: 5, 6: 4, 7: 3, 8: 2 or 9: 1 before encoding in hard split mode, as is done in logical split mode, when the ratio of input information bits is 5: 5.

Figure 2 shows a block diagram of a transmitter corresponding to one embodiment of the present invention. As shown in FIG. 2, the TFCI bits for the DSCH channel and the TFCI bits for the DCH channel, separated in one of the above information bit ratios, are supplied to the first and second encoders 200 and 205, respectively. Here, the TFCI bits for the DSCH channel are called TFCI indicator bits (field 1) or the first TFCI, and the TFCI bits for the DCH are called bits of the TFCI indicator (field 2) or the second TFCI. The TFCI bits for the DSCH come from the 250 bit generator of the first TFCI, and the TFCI bits for the DCH come from the 255 bit generator of the second TFCI. The number of bits of the first TFCI is different from the number of bits of the second TFCI in accordance with the above information bit ratios. In addition, a control signal containing information about the length of the code, i.e. information on the length of the codeword set in accordance with the ratio of information bits. Information about the length of the code comes from the generator 260 information about the length of the code and has a value that varies according to the bit length of the first TFCI and the second TFCI.

When the information bit ratio is 6: 4, encoder 200 receives a length control signal that allows this encoder to operate as an encoder (20, 6), encoder (19, 6), or encoder (18, 6) when receiving 6 TFCI bits for a channel DSCH and serve as one of the above 3 encoders; at the same time, encoder 205 receives a length control signal that allows this encoder 205 to act as an encoder (12, 4), encoder (13, 4) or encoder (14, 4) when receiving 4 TFCI bits for the DCH and serve as one of the above 3 encoders. When the information bit ratio is 7: 3, encoder 200 receives a length control signal that allows this encoder to operate as an encoder (23, 7), encoder (22, 7) or encoder (21, 7) when receiving 7 TFCI bits for a channel DSCH to act as one of the above 3 encoders; at the same time, encoder 205 receives a length control signal that allows this encoder to act as an encoder (9, 3), encoder (10, 3) or encoder (11, 3) when receiving 3 TFCI bits for a DCH and serve as one of the above 3 encoders. When the information bit ratio is 8: 2, the encoder 200 receives a length control signal that allows this encoder to operate as an encoder (26, 8), an encoder (25, 8) or. an encoder (24, 8) when receiving 8 TFCI bits for a DSCH channel and serve as one of the above 3 encoders; at the same time, encoder 205 receives a length control signal that allows this encoder to act as an encoder (6, 2), encoder (7, 2) or encoder (8, 2) when receiving 2 TFCI bits for a DCH and serve as one of the above 3 encoders. When the information bit ratio is 9: 1, encoder 200 receives a length control signal that allows this encoder to operate as an encoder (29, 9), encoder (28, 9), or encoder (27, 9) when receiving 9 TFCI bits for a channel DSCH and serve as one of the above 3 encoders; at the same time, encoder 205 receives a length control signal that allows this encoder to operate as an encoder (3, 1), encoder (4, 1) or encoder (5, 1) when receiving 1 TFCI bit for a DCH and serve as one of the above 3 encoders. The length control signal should be generated so that the sum of the bits of the first TFCI and the bits of the second TFCI is 32. That is, if the encoder for the first pointer is an encoder (4, 1), then the encoder for the second TFCI should be an encoder (28, 9), not the encoder (29, 9) or the encoder (27, 9). If the encoder for the second TFCI pointer becomes an encoder (29, 9), the number of encoded bits b ₁ becomes 33, and if the encoder for the second TFCI pointer becomes an encoder (27, 9), then the number of encoded bits b ₁ becomes 31. In this In this case, this transmitter is incompatible with a conventional transmitter that uses two encoders (16, 5) or one encoder (32, 10). In addition, the transmitter is incompatible with a conventional transmitter when converting bits b ₁ to bits d _m .

Figure 4 shows a detailed block diagram of the encoders 200 and 205. Namely, the encoder 200 for encoding the first TFCI, and the encoder 205 for encoding the second TFCI, have the structure shown in Figure 4. However, when generating code words of the first TFCI and code words of the second TFCI with a time delay, the encoder for the first TFCI and the encoder for the second TFCI can be implemented in one encoder. A block diagram of a transmitter for generating code words of a first TFCI and a time delay of a second TFCI is shown in FIG. 3.

First, with reference to FIG. 2, an encoder according to the present invention is described in detail for the case where the ratio of the bits of the first TFCI to bits of the second TFCI is 1: 9.

When the ratio of information bits is 1: 9, encoder 200 operates as an encoder (3, 1), and encoder 205 operates as an encoder (29, 9); encoder 200 operates as an encoder (4, 1), and encoder 205 operates as an encoder (28, 9); or encoder 200 operates as an encoder (5, 1), and encoder 205 operates as an encoder (27, 9).

Now, the operation of the encoder (3, 1), encoder (29, 9), encoder (4, 1), encoder (28, 9), encoder (5, 1) and encoder (27, 9) will be described in detail with reference to FIG. .4.

At the first stage, the operation of the encoder is described (3, 1). As shown in Figure 4, in the usual form, the encoder receives one input bit a0, and the remaining input bits a1, a2, a3, a4, a5, a6, a7, a8 and a9 are all filled with zeros. The input bit a0 is supplied to the multiplier 410, the input bit a1 is sent to the multiplier 412, the input bit a2 is sent to the multiplier 414, the input bit a3 is sent to the multiplier 416, the input bit a4 is sent to the multiplier 418, the input bit a5 is sent to the multiplier 420, the input bit a6 to the multiplier 422, input bit a7 to the multiplier 424, input bit a8 to the multiplier 426 and input bit a9 to the multiplier 428. At the same time, the Walsh code generator 400 generates the base code word W1 = 101010101010101011010101010101010100 and feeds the generated base word W1 to the multiplier 410. After that, the multiplier 410 multiplies the input bit a0 by the base code word W1 pos mvolno and delivers the result obtained at the output 440 to the logic "exclusive OR". Next, the Walsh code generator 400 creates the other base codewords W2, W4, W8 and W16 and feeds them to the multipliers 412, 414, 416 and 418, respectively. The All Units code generator 402 generates a base code word consisting of one units (or the All Units sequence), and feeds the created one unit code base word to the multiplier 420. The mask generator 404 creates the base code words M1, M2, M4 and M8 and feeds these generated base codewords to multipliers 422, 424, 426 and 428, respectively. However, since the input bits a1, a2, a3, a4, a5, a6, a7, a8 and a9 supplied to the multipliers 412, 414, 416, 418, 420, 422, 424, 426 and 428 are one zeros, then multipliers 412, 414, 416, 418, 420, 422, 424, 426, and 428 output zeros to the exclusive-OR logic 440, thereby not affecting the result obtained from the exclusive-OR logic 440. That is, the value determined by applying the Exclusive OR operation in the logic circuit 440 to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, 426 and 428 is equal to the value at the output of the multiplier 410. 32 characters, coming from the exclusive-OR logic 440 are supplied to the punch device 460. At this point, the controller 450 receives the code length information and, based on the code length information, provides a control signal indicating the position of the punch to the punching device 460. After which the device 460 punching perforates the 1st, 3rd, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 13th, 14th, 15th, 16th, 17th, 18th, 19th, 20th, 21st, 22nd, 23rd, 24th, 25th, 26th th, 27th, 28th, 29th, 30th and 31st coded characters from a total of 32 coded characters from 0 to 31 in accordance with a control signal received from controller 450. Others in words, the punching device 460 perforates 29 characters out of 32 encoded characters and thus outputs 3 unperforated encoded characters.

At the second stage, the operation of the encoder is described (29, 9). As shown in FIG. 4, in the normal form, nine input bits a0, a1, a2, a3, a4, a5, a6, a7 and a8 are supplied to the encoder, and the remaining input bit a9 is filled with zero. The input bit a0 is supplied to the multiplier 410, the input bit a1 is sent to the multiplier 412, the input bit a2 is sent to the multiplier 414, the input bit a3 is sent to the multiplier 416, the input bit a4 is sent to the multiplier 418, the input bit a5 is sent to the multiplier 420, the input bit a6 to the multiplier 422, input bit a7 to the multiplier 424, input bit a8 to the multiplier 426 and input bit a9 to the multiplier 428. At the same time, the Walsh code generator 400 supplies the base code word W1 = 1010101010101011010101010101010100 to the multiplier 410, the base codeword W2 = 01100110011001101100110011001100 - to the multiplier 412, base codeword W4 = 00011110000111100011110000111100 - to the multiplier 414, bases The codeword W8 = 00000001111111100000001111111100 is multiplied by the multiplier 416 and the base codeword W16 = 0000000000000001011111111111111101 is multiplied by the multiplier 418. After that, the multiplier 410 multiplies the base codeword W1 by the input bit a0 character by character and feeds the resulting output to the OR logic 440 " , the multiplier 412 multiplies the base code word W2 by the input bit a1 character-by-bit and feeds the resulting output to the exclusive-OR logic 440, the multiplier 414 multiplies the base code word W4 by the input bit a2 character-by-character and feeds the resulting by you While the result is in the exclusive-OR logic 440, the multiplier 416 multiplies the base codeword W8 by the input bit a3 character-by-bit and feeds the resultant output into the exclusive-logic OR 440 and the multiplier 418 multiplies the base codeword W16 by the input-bit a4 character-by-character and feeds the resulting output to the exclusive-OR logic 440. In addition, the All Units code generator 402 generates a base code word of one units with a length of 32 characters and supplies the generated base code word of one units to the multiplier 420. Then, the multiplier 420 multiplies the code word from one units by the input bit a5 character-by-character and feeds the resulting output to the exclusive-OR logic 440. The mask generator 404 supplies the base codeword M1 = 0101 0000 1100 0111 1100 0001 1101 1101 to the multiplier 422, the base codeword M2 = 0000 0011 1001 1011 1011 0111 0001 1100 to the multiplier 424, and the base word M4 = 0001 0101 1111 to the multiplier 426. 0010 0110 1100 1010 1100. After which, the multiplier 422 multiplies the base code word M1 by the input bit a6 character-by-character and feeds the resulting output to the exclusive OR logic 440, the multiplier 424 multiplies the base code word M2 by the input bit a7 character-by-character and delivers the resulting the output is the result in the exclusive circuit OR 440 and the multiplier l 426 multiplies the base codeword M4 by the input bit a8 character by character and feeds the resultant output to the exclusive-OR logic 440. Additionally, the mask generator 404 generates another base codeword M8 and supplies the generated base codeword M8 to the multiplier 428. However, since the input bit a9 supplied to the multiplier 428 is 0, the multiplier 428 supplies 0 to the exclusive-OR logic 440 , thus not affecting the result of the Exclusive OR resulting from the logic 440. That is, the value determined as a result of applying the Exclusive OR operation to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, 426 and 428 in the logic circuit 440 is equal to the value determined as a result of applying the operation " Exclusive OR "to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424 and 426. 32 characters coming from the logic circuit 440" Exclusive OR "are supplied to the device 460 punching. At this point, the controller 450 receives the code length information and, based on the code length information, provides a control signal indicating the position of the punch to the punching device 460. Then, the punching device 460 perforates the 6th, 10th, and 11th coded symbols from a total of 32 coded symbols from 0 to 31 in accordance with a control signal received from the controller 450. In other words, the punching device 460 perforates 3 characters out of 32 encoded characters and thus outputs 29 non-perforated encoded characters.

At the third stage, the operation of the encoder is described (4, 1). As shown in Figure 4, in the usual form, the encoder receives one input bit a0, and the remaining input bits a1, a2, a3, a4, a5, a6, a7, a8 and a9 are all filled with zeros. The input bit a0 is supplied to the multiplier 410, the input bit a1 is sent to the multiplier 412, the input bit a2 is sent to the multiplier 414, the input bit a3 is sent to the multiplier 416, the input bit a4 is sent to the multiplier 418, the input bit a5 is sent to the multiplier 420, the input bit a6 to the multiplier 422, input bit a7 to the multiplier 424, input bit a8 to the multiplier 426 and input bit a9 to the multiplier 428. At the same time, the Walsh code generator 400 generates the base code word W1 = 101010101010101011010101010101010100 and feeds the generated base word W1 to the multiplier 410. After that, the multiplier 410 multiplies the input bit a0 by the base code word W1 character but delivers the result obtained at the output 440 to the logic "exclusive OR". The Walsh code generator 400 also creates other base codewords W2, W4, W8 and W16 and feeds them to the multipliers 412, 414, 416 and 418, respectively. The All Units code generator 402 generates a base code word consisting of one units (or the All Units sequence), and feeds the generated one unit code base word to the multiplier 420. The mask generator 404 generates the base code words M1, M2, M4 and M8 and feeds these generated base codewords to multipliers 422, 424, 426 and 428, respectively. However, since the input bits a1, a2, a3, a4, a5, a6, a7, a8 and a9 supplied to the multipliers 412, 414, 416, 418, 420, 422, 424, 426 and 428 are one zeros, then the multipliers 412, 414, 416, 418, 420, 422, 424, 426 and 428 output zeros to the exclusive-OR logic 440, thereby not affecting the result obtained from the exclusive-OR logic 440. That is, the value determined by applying the Exclusive OR operation in the logic circuit 440 to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, 426 and 428 is equal to the value at the output of the multiplier 410. 32 characters, coming from the exclusive-OR logic 440 are supplied to the punch device 460. At this point, the controller 450 receives the code length information and, based on the code length information, provides a control signal indicating the position of the punch to the punching device 460. After which, the punching device 460 perforates the 1st, 3rd, 5th, 7th, 8th, 9th, 10th, 11th, 12th, 13th, 14th, 15th, 16th, 17th, 18th, 19th, 20th, 21st, 22nd, 23rd, 24th, 25th, 26th, 27th the 28th, 29th, 29th, 30th and 31st coded characters from a total of 32 coded characters from 0 to 31 in accordance with a control signal received from controller 450. In other words, device 460 punch punches 28 characters out of 32 coded characters and thus outputs 4 unperforated coded characters.

At the fourth stage, we describe the work of the encoder (28, 9). As shown in FIG. 4, in the normal form, nine input bits a0, a1, a2, a3, a4, a5, a6, a7 and a8 are fed to the encoder, and the remaining input bit a9 is filled with zero. The input bit a0 is supplied to the multiplier 410, the input bit a1 is sent to the multiplier 412, the input bit a2 is sent to the multiplier 414, the input bit a3 is sent to the multiplier 416, the input bit a4 is sent to the multiplier 418, the input bit a5 is sent to the multiplier 420, the input bit a6 to the multiplier 422, input bit a7 to the multiplier 424, input bit a8 to the multiplier 426 and input bit a9 to the multiplier 428. At the same time, the Walsh code generator 400 supplies the base code word W1 = 1010101010101011010101010101010100 to the multiplier 410, the base codeword W2 = 01100110011001101100110011001100 - to the multiplier 412, base codeword W4 = 00011110000111100011110000111100 - to the multiplier 414, baso The codeword W8 = 00000001111111100000001111111100 is multiplied by 416 and the base codeword W16 = 00000000000000010111111111111101 is multiplied by 418. After that, multiplier 410 multiplies the base codeword W1 by the input bit a0 character by character and feeds the resulting output to the OR logic 440 " , the multiplier 412 multiplies the base code word W2 by the input bit a1 character-by-character and feeds the resulting output to the exclusive-OR logic 440, the multiplier 414 multiplies the base code word W4 by the input bit a2 character-by-character and feeds the resulting by into When the result is output to the exclusive-OR logic 440, the multiplier 416 multiplies the base codeword W8 by the input bit a3 character-by-bit and feeds the resulting output to the exclusive-logic logic 440 and the multiplier 418 multiplies the base code-word W16 by the input bit a4 character-by-character and feeds the resulting output to the exclusive-OR logic 440. In addition, the All Units code generator 402 generates a base code word of one units with a length of 32 characters and feeds the generated base code word of one units to a multiplier 420. Then, a multiplier 420 multiplies a code word from one units by an input bit a5 character-by-character and feeds the resulting output to the exclusive-OR logic 440. The mask generator 404 supplies the base codeword M1 = 0101 0000 1100 0111 1100 0001 1101 1101 to the multiplier 422, the base codeword M2 = 0000 0011 1001 1011 1011 0111 0001 1100 to the multiplier 424, and the base word M4 = 0001 0101 1111 to the multiplier 426. 0010 0110 1100 1010 1100. After which, the multiplier 422 multiplies the base code word M1 by the input bit a6 character-by-character and feeds the resulting output to the exclusive OR logic 440, the multiplier 424 multiplies the base code word M2 by the input bit a7 character-by-character and delivers the resulting the output is the result in the exclusive circuit OR 440 and the multiplier l 426 multiplies the base codeword M4 by the input bit a8 character by character and feeds the resultant output to the exclusive-OR logic 440. Next, the mask generator 404 creates another base codeword M8 and feeds the generated base codeword M8 to the multiplier 428. However, since the input bit a9 supplied to the multiplier 428 is 0, the multiplier 428 feeds 0 to the exclusive-logic circuit 440 ", thus not affecting the resultant exclusive OR result of the logic 440. That is, the value determined as a result of applying the Exclusive OR operation to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, 426 and 428 in the logic circuit 440 is equal to the value determined as a result of applying the operation " Exclusive OR "to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424 and 426. 32 characters coming from the logic circuit 440" Exclusive OR "are supplied to the device 460 punching. At this point, the controller 450 receives the code length information and, based on the code length information, provides a control signal indicating the position of the punch to the punching device 460. Then, the punching device 460 perforates the 6th, 10th, 11th and 30th encoded characters from a total of 32 encoded characters from 0 to 31 in accordance with a control signal received from controller 450. Others in words, the punching device 460 perforates 4 characters of 32 encoded characters and thus outputs 28 unperforated encoded characters.

At the fifth stage, the operation of the encoder is described (5, 1). As shown in Figure 4, in the usual form, the encoder receives one input bit a0, and the remaining input bits a1, a2, a3, a4, a5, a6, a7, a8 and a9 are all filled with zeros. The input bit a0 is supplied to the multiplier 410, the input bit a1 is sent to the multiplier 412, the input bit a2 is sent to the multiplier 414, the input bit a3 is sent to the multiplier 416, the input bit a4 is sent to the multiplier 418, the input bit a5 is sent to the multiplier 420, the input bit a6 to the multiplier 422, input bit a7 to the multiplier 424, input bit a8 to the multiplier 426 and input bit a9 to the multiplier 428. At the same time, the Walsh code generator 400 generates the base code word W1 = 101010101010101011010101010101010100 and feeds the generated base word W1 to the multiplier 410. After that, the multiplier 410 multiplies the input bit a0 by the base code word W1 pos mvolno and delivers the result obtained at the output 440 to the logic "exclusive OR". Also, the Walsh code generator 400 generates other base codewords W2, W4, W8 and W16 and feeds them to the multipliers 412, 414, 416 and 418, respectively. The All Units code generator 402 generates a basic code word consisting of one units (or the All Units sequence) and supplies the generated basic one code word to the multiplier 420. The mask generator 404 also generates basic code words M1, M2, M4 and M8 and feeds these generated base codewords to multipliers 422, 424, 426 and 428, respectively. However, since the input bits a1, a2, a3, a4, a5, a6, a7, a8 and a9 supplied to the multipliers 412, 414, 416, 418, 420, 422, 424, 426 and 428 are one zeros, then multipliers 412, 414, 416, 418, 420, 422, 424, 426, and 428 output zeros to the exclusive-OR logic 440, thereby not affecting the result obtained from the exclusive-OR logic 440. That is, the value determined by applying the Exclusive OR operation in the logic circuit 440 to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, 426 and 428 is equal to the value at the output of the multiplier 410. 32 characters, coming from the exclusive-OR logic 440 are supplied to the punch device 460. At this point, the controller 450 receives the code length information and, based on the code length information, provides a control signal indicating the position of the punch to the punching device 460. After which, the punching device 460 perforates the 1st, 3rd, 5th, 7th, 9th, 10th, 11th, 12th, 13th, 14th, 15th, 16th, 17th, 18th, 19th, 20th, 21st, 22nd, 23rd, 24th, 25th, 26th, 27th, 28th the 29th, 30th, 30th and 31st coded characters from a total of 32 coded characters from 0 to 31 in accordance with a control signal received from the controller 450. In other words, the punch device 460 punches 27 characters of 32 encoded characters and thus outputs 5 non-perforated encoded characters.

At the sixth stage, the operation of the encoder is described (27, 9). As shown in FIG. 4, in the normal form, nine input bits a0, a1, a2, a3, a4, a5, a6, a7 and a8 are fed to the encoder, and the remaining input bit a9 is filled with zero. The input bit a0 is supplied to the multiplier 410, the input bit a1 is sent to the multiplier 412, the input bit a2 is sent to the multiplier 414, the input bit a3 is sent to the multiplier 416, the input bit a4 is sent to the multiplier 418, the input bit a5 is sent to the multiplier 420, the input bit a6 to the multiplier 422, input bit a7 to the multiplier 424, input bit a8 to the multiplier 426 and input bit a9 to the multiplier 428. At the same time, the Walsh code generator 400 supplies the base code word W1 = 1010101010101011010101010101010100 to the multiplier 410, the base codeword W2 = 01100110011001101100110011001100 - to the multiplier 412, base codeword W4 = 00011110000111100011110000111100 - to the multiplier 414, bases The codeword W8 = 00000001111111100000001111111100 is multiplied by the multiplier 416 and the base codeword W16 = 0000000000000001011111111111111101 is multiplied by the multiplier 418. After that, the multiplier 410 multiplies the base codeword W1 by the input bit a0 character by character and feeds the resulting output to the OR logic 440 " , the multiplier 412 multiplies the base code word W2 by the input bit a1 character-by-character and feeds the resulting output to the exclusive-OR logic 440, the multiplier 414 multiplies the base code word W4 by the input bit a2 character-by-character and feeds the resulting by into While the result is in the exclusive-OR logic 440, the multiplier 416 multiplies the base codeword W8 by the input bit a3 character-by-bit and feeds the resulting output into the exclusive-logic logic 440 and the multiplier 418 multiplies the base codeword W16 by the input bit-by-character a4 and feeds the resulting output to the exclusive-OR logic 440. In addition, the All Units code generator 402 creates a base code word of one units with a length of 32 characters and feeds the generated base code word of one units to a multiplier 420. Then, a multiplier 420 multiplies a code word from one units by an input bit a5 character-by-character and feeds the resulting output to the exclusive-OR logic 440. The mask generator 404 supplies the base codeword M1 = 0101 0000 1100 0111 1100 0001 1101 1101 to the multiplier 422, the base codeword M2 = 0000 0011 1001 1011 1011 0111 0001 1100 to the multiplier 424, and the base word M4 = 0001 0101 1111 to the multiplier 426. 0010 0110 1100 1010 1100. After which, the multiplier 422 multiplies the base code word M1 by the input bit a6 character-by-character and feeds the resulting output to the exclusive OR logic 440, the multiplier 424 multiplies the base code word M2 by the input bit a7 character-by-character and delivers the resulting the output is the result in the exclusive circuit OR 440 and the multiplier l 426 multiplies the base codeword M4 by the input bit a8 character by character and feeds the resultant output to the exclusive-OR logic 440. Also, the mask generator 404 creates another base codeword M8 and supplies the generated base codeword M8 to the multiplier 428. However, since the input bit a9 supplied to the multiplier 428 is 0, the multiplier 428 supplies 0 to the exclusive-OR logic 440 , thus not affecting the result of the Exclusive OR resulting from the logic 440. That is, the value determined as a result of applying the Exclusive OR operation to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, 426 and 428 in the logic circuit 440 is equal to the value determined as a result of applying the operation An exclusive OR to the output values of the multipliers 410, 412, 414, 416, 418, 420, 422, 424, and 426. 32 characters from the exclusive OR logic 440 are provided to the punch device 460. At this point, the controller 450 receives the code length information and, based on the code length information, provides a control signal indicating the position of the punch to the punching device 460. Then, the punching device 460 perforates the 0th, 2nd, 8th, 19th and 20th coded characters from a total of 32 coded characters from 0 to 31 in accordance with a control signal received from controller 450. In other words, punching device 460 perforates 5 characters from 32 encoded characters and thus outputs 27 unperforated encoded characters.

Table 5 shows the punching patterns, using which all the encoders shown in Table 1 can be implemented using the encoder shown in Figure 4. The punching patterns shown in Table 5 are used in the punching device 460 shown in FIG. 4 to generate the code (n, k) (where n = 3, 4, ..., 14, 18, 19, ..., 29 and k = 1, 2, 3, 4, 6, 7, 8, 9).

In table 5, “0” represents the position at which the encoded character is perforated, and “1” represents the position at which the encoded character is not perforated. Using the punching schemes shown in Table 5, the symbols of the first encoded TFCI and the second encoded TFCI can be calculated even for cases where the ratio of the number of information bits of the first TFCI and the number of information bits of the second TFCI is 2: 8, 3: 7, 4: 6, 6: 4, 7: 3, 8: 2 and 9: 1. Based on a consideration of the punching patterns shown in Table 5 and the previous description for the case where the ratio of the number of information bits of the first TFCI to the number of information bits of the second TFCI is 1: 9, the operation of encoders 200 and 205 should become more obvious.

After the operations described above, encoded characters coming from encoders 200 and 205 are composed (or time-multiplexed) using a linker (or multiplexer) 210 generating a 32-character multiplexed signal.

The following describes a method of arranging the symbols of the first encoded TFCI and symbols of the second encoded TFCI using the encoder 210 of the encoded symbols. The encoder symbol compiler 210 composes the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator coming from encoders 200 and 205 so that the encoded TFCI symbols are distributed in the radio frame as evenly as possible. That is, the encoder symbol composer 210 converts information bits a _k into encoded bits b ₁ , as described in the prior art. Of the encoded symbols obtained by encoding information bits a _k , the xth encoded symbol of the encoded symbols obtained by encoding the bits of the first TFCI is denoted as c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ , where x is an integer, including 0, and the yth encoded character from the encoded characters obtained by encoding the bits of the second TFCI pointer is denoted as c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ , where y is an integer, including 0. The sum of the x value of the last character from c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and the values of the last character from c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ must always be 32. In addition, the sum of the encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and coded characters c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ is 32. Thus, the encoder 210 linker performs the function of converting encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ to bits b ₁ . Before transmission in a real radio frame, bits b _{1 are} converted to bits d _m for the corresponding cases A1, A2, A3 and A4.

In the case of conditions A2, A3 and A4, all 32 bits of b ₁ are transmitted accordingly. However, in the case of condition A1, bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ) are not transmitted, so you must choose one of the encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ to map them to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₃ ). Rules for displaying encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ in bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ) are given below.

Rule 1: the last encoded characters from the characters of the first encoded TFCI indicator and the characters of the second encoded TFCI indicator are mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ).

Rule 2: arbitrary encoded characters from the symbols of the first encoded TFCI and symbols of the second encoded TFCI are mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ).

Rule 3: two arbitrary coded characters coming from an encoder with an increased coding rate are mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ).

Rule 4: two arbitrary coded characters coming from an encoder with a high coding rate are mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ).

Rule 5: two arbitrary encoded characters coming from an encoder other than an encoder with an increased encoding rate are mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ).

When applying Rule 1, Rule 2, Rule 3, Rule 4 and Rule 5, the following shall be taken into account. Namely: when one or two coded characters from coded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ each of the codes is not transmitted, it must be taken into account: (1) how the efficiency of the code used for the first TFCI or the second TFCI will change; (2) the reliability (or effectiveness) of which of the TFCIs, the first TFCI or the second TFCI, should be increased; (3) which encoded characters from encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ coming from the respective encoders should be mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ) in order to minimize the degradation of code efficiency; and (4) which of the TFCIs, the first TFCI or the second TFCI, should undergo changes during transmission.

Upon further consideration of Rule 1, Rule 2, Rule 3, and Rule 5, it will be assumed that in the HSM method, the ratio of the number of information bits of the first TFCI to the number of information bits of the second TFCI is 3: 7. In addition, when considering Rule 4, it will be assumed that the ratio of the number of information bits of the first TFCI to the number of information bits of the second TFCI is 3: 7 for case A1.

Consider Rule 1 using an example. In accordance with the ratio of the information bits of the first TFCI and the second TFCI, there is a code (9, 3) and a code (23, 7) or a code (11, 3) and a code (21, 7). Code (9, 3) and code (23, 7) are used to increase the coding efficiency of the second TFCI, and code (11, 3) and code (21, 7) are used to increase the coding efficiency of the first TFCI. When Rule 1 is applied, the last encoded character of the code is not transmitted (9, 3), as a result, the real encoding speed for the code (9, 3) becomes (8, 3); the last encoded character of the code is not transmitted (23, 7), as a result, the real encoding speed for the code (23, 7) becomes equal to (22, 7); the last encoded character of the code is not transmitted (11, 3), as a result, the real encoding speed for the code (11, 3) becomes equal to (10, 3); and the last encoded character of the code is not transmitted (21, 7), as a result, the real encoding speed for the code (21, 7) becomes equal to (20, 7). In Rule 1, the encoders map the last encoded characters they created into bits d ₃₀ (b ₃₀ ) and d ₃₁ (d ₃₁ ), thereby simplifying the conversion. However, in the case of condition A1, the real coding rates of the first TFCI and the second TFCI are reduced, resulting in a decrease in the coding efficiency of the first TFCI and the second TFCI.

Consider Rule 2 using an example. In accordance with the ratio of the information bits of the first TFCI and the second TFCI, there is a code (9, 3) and a code (23, 7) or a code (11, 3) and a code (21, 7). When Rule 2 is applied, no arbitrary coded code symbol is transmitted (9, 3), as a result, the real encoding speed for the code (9, 3) becomes equal to (8, 3); no arbitrary coded code symbol is transmitted (23, 7), as a result, the real encoding speed for the code (23, 7) becomes equal to (22, 7); no arbitrary coded code symbol is transmitted (11, 3), as a result, the actual encoding speed for the code (11, 3) becomes equal to (10, 3); no arbitrary coded code symbol is transmitted (21.7), as a result, the real coding rate for the code (21, 7) becomes equal to (20, 7). Arbitrary coded characters can be selected from these 4 codes in such a way that the real efficiency of the codes does not decrease despite the decrease in real coding rates for the corresponding codes. However, the performance of some codes may decrease regardless of the selected arbitrary encoded characters. Rule 2 is more complicated than Rule 1 in the way of converting coded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ . However, in the case of condition A1, it is possible to maintain the efficiency of the codes of the first TFCI and the second TFCI, despite the decrease in the real coding rate in the encoders for the first TFCI and the second TFCI.

Consider Rule 3 using an example. In accordance with the ratio of the information bits of the first TFCI and the second TFCI, there is a code (9, 3) and a code (23, 7) or a code (11, 3) and a code (21, 7). When Rule 3 is applied, 2 arbitrary coded code symbols are not transmitted (23, 7), as a result, the real encoding speed for the code (23, 7) becomes equal to (21, 7); 2 arbitrary encoded code symbols are not transmitted (11, 3), as a result, the real encoding speed for the code (11, 3) becomes equal to (9, 3). Arbitrary coded characters can be selected so that the real code efficiencies do not decrease despite the reduction in real coding rates for the corresponding codes. However, most codes are less efficient. In the case of Rule 3, the actual coding rate of the corresponding codes becomes (9, 3) or (21, 7), thus, the efficiency of the TFCI codewords is observed at the real data rate for condition A1. However, an increase in the number of coded TFCI symbols causes a decrease in code efficiency, for which the number of coded symbols has increased despite the intention to increase the efficiency of the code of the first TFCI or the code of the second TFCI. In the case of Rule 3, you can search for arbitrary characters that do not reduce the effectiveness of the codes. Like Rule 2, Rule 3 is also characterized by a complex way of conversion. To simplify the conversion method, the last two of the encoded characters coming from the encoder generating the increased number of encoded characters are mapped to bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ).

Consider Rule 4 using an example. In accordance with the ratio of the information bits of the first TFCI and the second TFCI, there is a code (9, 3) and a code (23, 7) or a code (11, 3) and a code (21, 7). Code (9, 3) and code (23, 7) are used to increase the coding rate of the first TFCI, and code (11, 3) and code (21, 7) are used to increase the coding rate of the second TFCI. When Rule 4 is applied, the last two coded characters of the code are not transmitted (23, 7), as a result, the real coding rate for the code (23, 7) becomes equal to (21, 7); and the coding rate for the code (9, 3) remains unchanged; the last two encoded characters of the code are not transmitted (21, 7), as a result, the real encoding speed for the code (21, 7) becomes equal to (19, 7); and the coding rate for the code (11, 3) remains unchanged. When Rule 4 is applied, bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ) display the last two characters or two arbitrary characters coming from the corresponding encoders, creating a large number of code words. When Rule 4 is applied, two coded characters of a code having a longer codeword are not transmitted, as a result of which the efficiency of a code having a longer codeword is reduced, but the efficiency of a code having a shorter codeword is preserved.

Consider Rule 5 using an example. If it is assumed that the ratio of the number of information bits of the first TFCI and the number of information bits of the second TFCI is 3: 7, and the efficiency of the codeword transmitting the second TFCI is increased, then there are codes (9, 3) and (23, 7). When Rule 5 is applied, in order to transmit the second TFCI with high reliability, two arbitrary coded code symbols are displayed in bits d ₃₀ (b ₃₀ ) and d ₃₁ (b ₃₁ ), as a result of which the real encoding speed becomes ( 7, 3). When Rule 5 is applied, the encoder performance for the first TFCI is reduced, but the encoded characters for the second TFCI are “intact”, so that the second TFCI codeword can be safely transmitted.

In the above description, Rules 1, Rules 2, Rules 3 and Rules 4 bits c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ are mapped to bits b ₁ only if condition A1 is present. However, when conditions A2, A3 and A4 are met, all of the 32 encoded characters are transmitted, or these 32 encoded characters are transmitted in a repeating manner, so no separate conversion rule is required, and the unchanged conversion rules applicable to the case of condition A1 can be used. Moreover. Rule 1, Rule 2, Rule 3, Rule 4 and Rule 5 may be applied appropriately in accordance with the circumstances.

Further, an example of a method for converting c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ to bits b ₁ . In the example below, the method used for Rule 1 and the method of arranging the symbols of the first encoded TFCI and symbols of the second encoded TFCI as evenly as possible in order to reduce transmission time can also be applied to another conversion method. In the case of condition A1, the last coded characters from the number c are displayed in b ₃₀ or b ₃₁ $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ .

Of the encoders 16 of the present invention, encoders that increase the coding rate for the encoder of the first TFCI or for the encoder of the second TFCI having a 1/3 coding rate are designed to provide optimal performance at a 1/3 coding rate.

Before describing how to convert encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ in coded bits b ₁ we denote the number of characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ the first encoded TFCI pointer as n (where n = x + 1), and the number of characters c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ the second encoded TFCI pointer as m (where m = y + 1). For convenience, we assume that n is equal to or less than m, and the sum of n and m is 32. Therefore, if n = 4, 7, 10, 13, and 16, then m = 28, 25, 22, 19, and 16, respectively. The values of n and m are defined as follows:

In Equation (1), n denotes the total number of characters of the first encoded TFCI, ai denotes the character indices of the first encoded TFCI, with 0≤i≤n-1 (or x). Indexes are assigned in order of formation. Equation (1) gives the positions of bits b ₁ to which the symbols of the first encoded TFCI pointer should be mapped. In Equation (1), [x] means an integer obtained by rounding a given value of x.

In Equation (2), n is the total number of characters of the first encoded TFCI, m is the total number of characters of the second encoded TFCI, and i is the character indices of the second encoded TFCI, with 0≤i≤m-1 (or y). Indexes are assigned in order of formation. Equation (2) gives the positions of bits b ₁ to which the symbols of the second coded TFCI pointer should be mapped. In Equation (2); x; means an integer less than or equal to the given value of x.

The symbols of the first encoded TFCI indicator are displayed (composed) in accordance with Equation (1), and the symbols of the second encoded TFCI indicator are displayed in accordance with Equation (2). Regarding the sequence of coded symbols, either the symbols of the first encoded TFCI or the symbols of the second encoded TFCI may be arranged first. Otherwise, the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator may be arranged at the same time.

If the number of characters of the first encoded TFCI is greater than the number of characters of the second encoded TFCI (n> m), Equation (2) is used to display the characters of the first encoded TFCI and Equation (1) is used to display the characters of the second encoded TFCI.

Table 6 shows the coded symbols generated according to Equation (1) and Equation (2). In Table 6, “0” indicates the position where the c characters are transmitted $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ the first encoded TFCI, and "1" indicates the position where the c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ second encoded TFCI pointer.

Table 6 is an example of the arrangement of the symbols of the first encoded TFCI and symbols of the second encoded TFCI. In order to select positions for transmitting encoded characters created in accordance with Table 6 over the physical channel, various methods are used for conditions A1, A2, A3 and A4. In the case of condition A1, the encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ mapped to bit b ₃₀ or bit b ₃₁ are punched, and then 30 bits b _{1 are} converted (displayed) before being transferred to bits d _m . In the case of condition A2, 32 bits b ₁ converted to condition A1 are repeated 3 times in succession, bits b ₀ to b _{23 are} repeated again and then converted before transmission to a total number of bits d _m equal to 120. In case of condition A3 32 bits b ₁ arranged for condition A1 are displayed before being transmitted at the position of the transmitted bits d _m . In the case of condition A4, 32 bits b ₁ , converted for condition A1, are repeated 4 times, then they are displayed before transmission at the position of 128 transmitted bits d _m .

FIG. 6 is a detailed block diagram of a coded symbol linker 210 shown in FIG. 2. Referring to FIG. 6, the reference numeral 601 indicates the characters c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ the second TFCI encoded pointer coming from the encoder 200 shown in FIG. 2, and c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ the first TFCI encoded pointer coming from encoder 205. Storage devices 603 and 613 are devices designed to store encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ and implemented using storage devices (memory). However, when modifying the hardware structure, the symbols 601 of the second TFCI encoded indicator and the symbols 611 of the first TFCI encoded indicator can be sent directly to the switch 620 without storing the encoded symbols in storage devices. The switch 620 alternately connects the storage devices 603 and 613 according to the received code selection information. Coded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ coming from storage devices 603 and 613 are stored in the permanent storage device 621. The controller 670 composes the received encoded symbols c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ in accordance with Table 6. The layout of characters can be implemented either hardware or software. The switch 630 forwards the bits b ₁ stored in the storage device 621 to the output node or the repeater 640 in accordance with the information on the number of TFCI encoded symbols, i.e. bit information d _m . Namely: in the case of conditions A1 or A3, when the number of bits d _m is 30 or 32, the switch 630 sends bits b ₁ from the storage device 621 to the output node. In the case of conditions A2 or A4, when the number of bits d _m is 120 or 128, the switch 630 sends the bits b ₁ from the storage device 621 to the repeater 640. The repeater 640 repeats the bits b ₁ received from the switch 630 a predetermined number of times to obtain bits d _m , for conditions A2 or A4. Under conditions A2 and A4, repeater 640 is turned on. Repeater 640 may also be implemented programmatically in controller 670.

B ₁ bits arranged by encoder 210 in accordance with Table 6 are provided to multiplexer 220, where they are time-multiplexed with physical information, such as TPC command bits and pilot bits transmitted over the DPCCH, and with the DPDCH. Multiplexer 220 generates a DPCH signal, the structure of which is depicted in FIG. Figure 5 shows the structure of the DPCH signal transmitted from the Node B to the user equipment.

Referring to FIG. 5, reference numeral 510 denotes a structure of a radio frame consisting of 15 time slots (slots). Reference numeral 520 denotes a time slot structure for a downlink channel in which a DPDCH channel signal and a DPCCH channel signal are separated in time. That is, the time interval (slot) consists of two data fields 501 and 507 forming the DPDCH channel, as well as a TPC command field 503, a TFCI indicator field 505, and a pilot signal field 509 forming the DPCCH channel. The TPC command field 503 is used to transmit the TPC command for the uplink channel from the user equipment to Node B, and the pilot signal field 509 is used to evaluate the change in the uplink channel and the signal strength by the user equipment. Further, the TFCI indicator field 505 is used to transmit the dm symbols of the TFCI encoded indicator received to the user equipment from the encoder symbol composer 210.

The DPCH channel created by the multiplexer 220 is supplied to the expander 230, and at the same time, an expansion code for channel separation is supplied from the spreading code generator 235 to the expander 230. Expander 230 expands the DPCH bandwidth character-by-character with the spreading code and outputs the expanded DPCH signal bitwise. The expanded DPCH signal is supplied to the scrambler 240, and at the same time, a scrambling code is supplied from the scrambler code generator 245 to the scrambler 240. The scrambler 240 encrypts the extended DPCH channel signal with a scrambling code.

2. The second embodiment of the transmitter

13 is a structural diagram of a transmitter according to a second embodiment of the present invention. As shown in FIG. 13, encoder 1303 and encoder 1313 encode TFCI information bits for a DSCH (information bits of a second TFCI indicator) and TFCI information bits for a DCH (information bits of a first TFCI indicator), respectively. Encoder 1303 and encoder 1313 are identical in structure to the encoder shown in FIG. 4, except that there is no punching device and controller. 32 encoded symbols coming from encoder 1303 are supplied to the symbol storage device 1305 of the second TFCI encoded indicator, and 32 encoded symbols coming from encoder 1313 are supplied to the symbol storage device 1315 of the first TFCI encoded indicator. The symbol storage device 1315 of the first TFCI encoded pointer and the symbol storage device 1305 of the second TFCI encoded pointer can share the same memory device. In this case, the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator should be logically recognizable. The symbol storage device 1305 of the second TFCI encoded pointer and the symbol storage device 1315 of the first TFCI encoded pointer provide encoded symbols from the number of 32 encoded symbols stored in them to the linker 1350, selected in accordance with the encoded symbol selection information of the second TFCI indicator and encoded selection information 1333 the symbols of the first TFCI indicator received from the controller 1330. Information 1331 selection of encoded symbols of the second indicator TFCI and information 1333 selection of encoded SIM tin TFCI first pointer is the same information as the puncturing scheme given in Table 5, and used to select the required coded symbols from the 32 coded symbols instead of puncturing the coded symbols according to a puncturing scheme. From the symbol storage device 1305 of the second TFCI encoded pointer and the symbol storage device 1315 of the first TFCI encoded pointer, c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ and c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ . The symbol composer 1350 composes the received symbols of the second TFCI encoded indicator and the symbols of the first TFCI encoded indicator in the form shown in Table 6 according to the encoded symbol arrangement information 1335 received from the controller 1330. As a result, the linker 1350 outputs bits b ₁ . The controller 1330 shown in FIG. 13 controls the character storage devices 1305 and 1315 and the character builder 1350 in accordance with the character punching pattern shown in Table 5 and the character patterning shown in Table 6 to obtain the same result, as for the encoder and character selector shown in Figures 4, 6 and 8.

On Fig shows a detailed structural diagram of the linker 1350 encoded characters. As shown in FIG. 19, a coded symbol composer consists of a storage device 1901, a controller 1910, and a switch. A storage device 1901 (i.e., a device designed to store the characters of the first encoded TFCI and symbols of the second encoded TFCI in the form shown in Table 6) composes the symbols of the first encoded TFCI and symbols of the second encoded TFCI under the control of the controller 1910, and then sequentially outputs bits b ₁ . A controller 1910 for supplying the symbols of the first encoded TFCI and symbols of the second encoded TFCI to the storage device 1901 controls the switch and also controls the storage device 1901 to rearrange the symbols of the first encoded TFCI and the symbols of the second encoded TFCI to the form shown in Table 6. The controller 1910 shown in FIG. 19 may be implemented in software. In this case, the software can serve as an address controller. Otherwise, the symbol composer 1350, the symbol storage device 1315 of the first TFCI encoded indicator, and the symbol storage device 1305 of the second TFCI encoded indicator can be implemented either in the same memory device or in different memory devices. However, in a software implementation, the controller 1330 manages the memory addresses of the symbol mapper 1350, the symbol storage device 1315 of the first TFCI encoded indicator, and the symbol storage device 1305 of the second TFCI encoded indicator, thereby performing the functions of the encoders and symbol mapper programmatically.

3. The third embodiment of the transmitter

Figure 3 shows a block diagram of a transmitter according to a third embodiment of the present invention. The transmitter encodes the bits of the first TFCI and the bits of the second TFCI using one encoder.

As shown in FIG. 3, bits 301 of the second TFCI and bits 303 of the first TFCI are provided to selector 310.

The selector 310 selectively feeds to the encoder 311 bits 301 of the second TFCI indicator or bits 303 of the first TFCI indicator in accordance with the selection information of the TFCI indicator received from the controller 330. An exemplary detailed block diagram of the selector 310 is shown in FIG. 7. As shown in FIG. 7, bits 301 of the second TFCI are supplied to storage device 703, and bits 303 of the first TFCI are supplied to storage device 713. Storage devices 703 and 713 (that is, devices designed to store bits 301 of the second TFCI and bits 303 of the first TFCI indicator) may be implemented using storage devices. However, when modifying the hardware structure, it is possible to directly feed bits 301 of the second TFCI and bits 303 of the first TFCI to the switch 720 without using storage devices. The switch 720 alternately connects the storage devices 703 and 713 according to the received code selection information. The bits of the second TFCI pointer and the bits of the first TFCI pointer coming from switch 720 are provided to encoder 311. Selector 310 may also be implemented in software.

Encoder 311 has the structure shown in FIG. 4 and encodes TFCI bits from selector 310 in accordance with code length information received from controller 330. Controller 330 may also be implemented in software.

Coded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ or c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ coming from the encoder 311, served in the linker 312 characters, where they are arranged in the form shown in Table 6. The internal structure of the linker 312 characters shown in Fig.

As shown in FIG. 8, the storage device 801 composes the received TFCI encoded symbols into the form shown in Table 6 under the control of the controller 810. Of the encoded symbols c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ or c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ first received TFCI encoded symbols are stored in the storage device 801 until the layout of the other TFCI encoded symbols is completed. Storage device 801 provides bits b ₁ to switch 803. The switch 803 provides unmodified TFCI encoded symbols from the storage device 801 or sends the TFCI encoded symbols to the repeater 805 in accordance with the information on the number of transmissions of the encoded TFCI symbols. The repeater 805 repeats the encoded symbols coming from the switch 803 with such a multiplicity that their number is equal to the number of encoded symbols d _{m of} the TFCI pointers, which should be transmitted over the physical channel. To perform this operation, the repeater 805 may also be implemented in software. Repeater 805 can be implemented either as an internal unit of controller 810, or as a separate unit.

The encoded symbols d _{m of} the TFCIs coming from the symbol composer 312 are supplied to a multiplexer 313, where they are time-multiplexed with physical information, such as the TPC command and pilot bits transmitted on the DPCCH and the DPDCH. The multiplexed DPCH signal has the structure shown in FIG. 5.

The signal of the DPCH channel is supplied to the expander 314 and at the same time, an extension code generated by the extension code generator 316 is supplied to the expander 314. Expander 314 expands the DPCH signal bandwidth character by character with the spreading code for channel separation and outputs the expanded DPCH signal bitwise. The expanded DPCH signal is supplied to the scrambler 315, and at the same time, a scrambling code is received from the scrambler code generator 317 to the scrambler 315. The scrambler 315 encrypts the extended DPCH signal with a scrambling code.

4. The fourth embodiment of the transmitter

FIG. 14 is a structural diagram of a transmitter according to a fourth embodiment of the present invention. The transmitter shown in FIG. 14 differs from the transmitter shown in FIG. 13 in that the information bits of the first TFCI and the information bits of the second TFCI are sequentially encoded using one encoder. As shown in FIG. 14, information bits of a first TFCI indicator or information bits of a second TFCI indicator are supplied to encoder 1403, where they are encoded and then supplied to encoded symbol storage device 1405. The encoded symbol storage device 1405 selects the encoded symbols in accordance with the encoded symbol selection information 1401 (i.e., the punching pattern shown in Table 5) received from the controller 1430 and supplies the selected encoded symbols to the code selector 1450 (or code composer) . The encoded symbol storage device 1405 may directly feed selected symbols of a first encoded TFCI indicator or symbols of a second encoded TFCI indicator to a code composer 1450. Otherwise, the encoder 1403 provides other encoded symbols of the TFCI pointer, and the encoded symbol storage device 1405 selects the symbols of the already stored TFCI encoded pointer in accordance with the encoded symbol selection information 1401 from the controller 1430, and provides two types of encoded TFCI symbols to the linker 1450 code. The code selector 1450 shown in FIG. 14 converts the encoded characters c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ taken in the form shown in Table 6, in bits b ₁ . In addition, a coded character storage device, a code composer, and a controller may be implemented in software.

5. The fifth embodiment of the transmitter

15 is a structural diagram of a transmitter according to a fifth embodiment of the present invention. Unlike other transmitters, the transmitter shown in FIG. 15 simultaneously encodes TFCIs and character arrangements.

The operation of this transmitter is described with reference to an example in which the bits of the second TFCI are encoded at a speed of (4, 1), the bits of the first TFCI are encoded at a speed of (28, 9), and the encoded characters are compiled into bits b ₁ .

As shown in FIG. 15, the base codeword storage device 1501 stores the base codewords W1, W2, W4, W8, W16, M1, M2, M4, M8 and the “All Units” sequence used in the encoder shown in FIG. 4 . In the base codeword storage device 1501, the base codewords 32 characters long are arranged in horizontal rows, with the characters of the corresponding base codewords arranged in vertical columns. The controller 1510 receives the information bits 1511 of the second TFCI indicator, the information bits 1513 of the first TFCI indicator, information 1515 about the selection of symbols of the encoded TFCI indicators and information 1517 about the character layout of the encoded TFCI indicators, controls the base code word storage device 1501 to generate the code (4, 1) and code (28, 9) and composes the codes in order to reduce the transmission time.

If the information bit 1511 of the second TFCI is designated as a $\genfrac{}{}{0ex}{}{\text{2}}{\text{0}}$ , and information bits 1513 of the first TFCI pointer to designate as a $\genfrac{}{}{0ex}{}{\text{1}}{\text{0}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{1}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{3}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{4}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{5}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{6}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{7}}$ and a $\genfrac{}{}{0ex}{}{\text{1}}{\text{8}}$ , then the controller 1510 repeats the operation 4 times generating 7 symbols of the first encoded TFCI and 1 symbol of the second encoded TFCI according to the information 1517 about the layout of the encoded TFCI symbols shown in Table 6, i.e., c $\genfrac{}{}{0ex}{}{\text{1}}{\text{0}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{1}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{3}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{4}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{5}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{6}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{7}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{8}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{9}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{10}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{eleven}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{12}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{thirteen}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{14}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{fifteen}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{16}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{17}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{18}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{19}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{20}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{21}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{22}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{23}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{24}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{25}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{26}}$ , c $\genfrac{}{}{0ex}{}{\text{1}}{\text{27}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{0}}$ , c $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ , c $\genfrac{}{}{0ex}{}{\text{2}}{\text{2}}$ , c $\genfrac{}{}{0ex}{}{\text{2}}{\text{3}}$ .

For the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator, different base codewords are used in accordance with the received TFCI information bits a $\genfrac{}{}{0ex}{}{\text{1}}{\text{0}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{1}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{3}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{4}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{5}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{6}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{7}}$ , a $\genfrac{}{}{0ex}{}{\text{1}}{\text{8}}$ and a $\genfrac{}{}{0ex}{}{\text{2}}{\text{0}}$ . The use of the selected base codewords is determined in accordance with the meaning of the information bits: “0” or “1”, and the characters are selected according to the punching pattern shown in Table 5.

For the characters of the first encoded TFCI, nine input bits of the first TFCI are received, so the base code generator 1501 generates the base code words W1, W2, W4, W8, W16, the sequence "All units", M1, M2 and M4. For the symbols of the second encoded TFCI, one input bit of the second TFCI is received, therefore, the base codeword generator 1501 generates only the base codeword W1. The symbols of the first TFCI encoded pointer have a punch pattern {1,1,1,1,1,1,0,0,1,1,1,0,0,1,0,1,1,1,1,1,1,1,1 , 1,1,1,1,1,1,1,1,1,1,1,1}, and the symbols of the second TFCI encoded pointer have a punch pattern {1,0,1,0,1,0,1,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}.

To generate the symbols of the second TFCI encoded indicator, the base codeword storage device 1501 selects the 0th, 2nd, 4th and 6th symbols of the base codeword W1. To generate the characters of the first TFCI encoded pointer, the base codeword storage device 1501 applies the exclusive OR operation to the base codewords W1, W2, W4, W8, W16, the All Units sequence, M1, M2, and M4, then selects the characters of the resulting as a result of the code word, except for the 6th, 10th, 11th and 13th.

The operation of the encoder for the TFCI pointers and the character builder shown in FIG. 15 is described using an example of simultaneously generating code (4, 1) and code (28, 9). In addition, another method for generating various types of codewords includes a process for selecting the type of base codeword to be used according to the number of bits of the input code and determining the order of generation of the encoded characters using the encoded character arrangement shown in Table 6. This method also includes applying the operation "Exclusive OR" to the basic code words in accordance with the order and values of the bits of the input code and the selection of encoded characters in accordance with the punching pattern, when shown in Table 5. The coded symbol storage device 1530 stores values coming from the base codeword storage device 1501. Like the transmitter shown in FIGS. 13 and 14, the transmitter shown in FIG. 15 can also be implemented in software.

6. The first embodiment of the receiver

Fig. 9, in accordance with one embodiment of the present invention, is a block diagram of a receiver corresponding to the transmitters shown in Figs. 3 and 4. As shown in Fig. 9, a downlink DPCH signal is supplied to the descrambling device 940, and at the same time, a scrambling code generated by the scrambling code generator 945 is supplied to the descrambling device 940. The descrambling device 940 decrypts the downlink DPCH channel signal using the scrambling code. The descrambled downlink DPCH signal is supplied to the convolution device 930, and at the same time, an expansion code generated by the spread code generator 935 is supplied to the convolution device 930. The convolution device 930 convolves the descrambled downlink DPCH signal symbol by symbol using the spreading code.

The symbols of the convolutional DPCH channel signal are supplied to the demultiplexer 920, where they are demultiplexed (separated) into TFCI encoded symbols and other signals, such as the DPDCH channel, TPC command bits, and pilot bits. TFCI coded symbols are provided to coded symbol rearrangement apparatus 910. The coded symbol rearrangement device 910 splits the TFCI coded symbols into coded symbols for the DSCH channel (information symbols of the second TFCI indicator) and encoded symbols for the DCH channel (information symbols of the first TFCI indicator) in accordance with the code length information and position information. The code length information is code length control information based on the ratio of the number of TFCI bits for the DSCH and the number of TFCI bits for the DCH. The position information is information indicating the positions of the encoded symbols for the DSCH channel and the positions of the encoded symbols for the DCH channel, shown in Table 6. The symbols of the second encoded TFCI pointer and the symbols of the first encoded TFCI pointer, separated by the encoded symbol remap apparatus 910, are supplied to the first decoder 900 and a second decoder 905, respectively. The decoders 900 and 905 determine the corresponding codes according to the code length information and decode the symbols of the second encoded TFCI indicator and the symbols of the first encoded TFCI indicator using certain codes, respectively. That is, the first decoder 900 decodes the symbols of the second encoded pointer. TFCI both outputs the bits of the second TFCI indicator (TFCI bits for the DSCH channel), and the second decoder 905 decodes the symbols of the first encoded TFCI indicator and outputs the bits of the first TFCI indicator (TFCI bits for the DCH channel).

On figa and 18B shows a detailed structural diagram of a device 910 rearrangement of coded symbols, corresponding to various embodiments of the present invention. As shown in FIG. 18A, a coded symbol rearrangement device consists of a storage device 1801, a controller 1810, and a switch. A storage device 1801, that is, a device for storing TFCI encoded symbols received from the demultiplexer 920, separates the symbols of the first encoded TFCI and the symbols of the second encoded TFCI under the control of the controller 1810. The controller 1810 controls the storage device 1801 and the switch so that decoders 905 and 900 were supplied, respectively, the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator. Otherwise, if one decoder is used, the controller 1810 separately. provides two types of TFCI encoded symbols to one decoder. Controller 1810 may be implemented in software. In this case, the software can serve as an address controller.

As shown in FIG. 18B, the coded symbol rearrangement device consists of a storage device 1821, a controller 1820, a mask generator 1830, a multiplier 1815, and a multiplier 1817. The storage device 1821 operates similarly to the storage device 1801 shown in FIG. 18A. A controller 1820 controls the storage device 1821 to provide TFCI encoded symbols from the demultiplexer 920 to the first multiplier 1815 and the second multiplier 1817. In addition, the controller 1820 controls the mask generator 1830 to create masks to separate the characters of the first TFCI encoded pointer and the symbols of the second encoded pointer TFCI The masks generated by the mask generator 1830 are supplied to the first multiplier 1815 and the second multiplier 1817. The first multiplier 1815 multiplies the encoded TFCI symbols coming from the storage device 1821 by the corresponding mask and outputs the characters of the first TFCI encoded pointer. The second multiplier 1817 multiplies the encoded TFCI symbols coming from the storage device 1821 by the corresponding mask and outputs the symbols of the second encoded TFCI. The mask generator 1830 either stores a character mapping pattern for the characters of the first encoded TFCI and symbols of the second encoded TFCI shown in Table 6 as a mask, or generates masks using Equations (1) and (2). Masks are used to separate the TFCI encoded symbols coming from demultiplexer 920 into the symbols of the first encoded TFCI and symbols of the second encoded TFCI. If each of the multipliers 1815 and 1817 can output two types of TFCI encoded symbols, then only one of these two multipliers is used to separate the symbols of the first encoded TFCI and the symbols of the second encoded TFCI.

FIG. 11 shows a detailed block diagram of the decoders 900 and 905 shown in FIG. 9. As shown in FIG. 11, the received symbols r (t) are supplied to the zero insertion device 1100, and at the same time, code length information is supplied to the controller 1130. The controller 1130, based on the code length information, determines the punching positions and provides control information for the specific punching positions to the zero insertion device 1100. The code length information indicates the code length or coding rate used in the encoder, and the control information indicates the punching position. Punch positions are the positions of characters deleted to obtain the desired length of the set of encoded characters corresponding to the number of bits received from the encoder. Table 7 shows the punch positions stored along with the code lengths.

Table 7 implies that the code length information indicates the coding rate used in the encoder. Since the coding rate (k, n) indicates that n input bits are encoded into k characters, the received characters have a coding length k. In addition, F_n in Table 7 represents n perforation positions. As can be seen from Table 7, the control information (punching position) allows the device 1100 insert zeros to save the number (32) of the displayed characters, regardless of the code length of the received characters.

As shown in Table 7, the controller 1130 outputs information about 29 punch positions for the coding rate (3, 1), information about 28 punch positions for the coding speed (4, 1), information about 27 punch positions for the coding speed (5, 1) , information on 26 punching positions for coding speed (6, 2), information on 25 punching positions for coding speed (7, 2), information on 24 punching positions for coding speed (8, 2), information on 23 punching positions for speed coding (9, 3), information about 22 punching positions for coding speed (10, 3), information on 21 punching positions for coding speed (11, 3), information on 20 punching positions for coding speed (12, 4), information about 19 punching positions for coding speed (13, 4), information on 18 punching positions for coding speed (14, 4), information on 14 punching positions for coding speed (18, 6), information on 13 punching positions for coding speed (19, 6), information on 12 punch positions for coding speed I (20, 6), information on 11 punching positions for coding speed (21, 7), information on 10 punching positions for coding speed (22, 7), information on 9 punching positions for coding speed (23, 7), information about 8 punching positions for coding speed (24, 8), information on 7 punching positions for coding speed (25, 8), information about 6 punching positions for coding speed (26, 8), information about 5 punching positions for coding speed ( 27, 9), information on 4 punching positions for coming soon five coding (28, 9) and information on 3 puncturing positions for a coding rate (29, 9). For appropriate cases, the punching positions are identical to those specified in the description of the encoder.

The zero insertion device 1100 inserts zeros at the punch position for received characters in accordance with the control information, and then outputs a character stream with a length of 32 characters. The symbol stream is supplied to the Hadamard inverse fast transform device 1120 and multipliers 1102, 1104 and 1106. The symbol stream supplied to the multipliers 1102, 1104 and 1106 is multiplied by the masking functions M1, M2 and M15, respectively, created by the mask generator 1110. Symbols output from multipliers 1102, 1104, and 1106 are provided to switches 1152, 1154, and 1156, respectively. At the same time, the controller 1130 supplies switching switches 1152, 1154, and 1156 with switching control information indicating the use / non-use of masking functions based on the code length information. For example, since the encoders (3, 1), (4, 1), (5, 1), (6, 2), (7, 2), (8, 2), (9, 3), (10, 3), (11, 3), (12, 4), (13, 4), (14, 4), (18, 6), (19, 6) and (20, 6) do not use masking functions, switches 1152, 1154, and 1156 are open in accordance with switching control information. However, since the encoders (21, 7), (22, 7) and (23, 7) use the same basic masking function, only the switch 1152 is closed. With this method, the controller 1130 controls the switches 1152, 1154 and 1156 in accordance with the number of functions masking used based on coding rate. Then, each of the inverse fast Hadamard transform devices 1120, 1122, 1124, and 1126 perform inverse fast Hadamard transform for 32 characters received from the zero insertion device 1100, and correlations between these characters and all Walsh codes that can be used in the transmitter are calculated. Next, the inverse fast Hadamard transform apparatuses determine the largest correlation of all correlations and the index of the Walsh code having the largest correlation. Thus, each of the devices 1120, 1122, 1124, and 1126 supplies the correlation comparator 1140 with the index of the masking function times the received signal, the highest correlation value, and the index of the Walsh code that has the highest correlation. Since the signal supplied to the inverse fast Hadamard transform device 1120 is not multiplied by any of the masking functions, the identifier of the masking function becomes "0". The correlation comparator 1140 determines the largest correlation by comparing the correlations from the Hadamard inverse fast transform devices, and combines the index of the masking function having the largest correlation with the Walsh code index.

7. The second embodiment of the receiver

Figure 10 in accordance with another embodiment of the present invention shows a block diagram of a receiver corresponding to the transmitters depicted in figure 3 and 4. As shown in figure 10, the signal channel DPCH downlink is supplied to the device 1040 descrambling and in the same time, a scrambling code generated by the scrambling code generator 1045 is supplied to the descrambling device 1040. The descrambling device 1040 decrypts the downlink DPCH signal using the scrambling code. The descrambled downlink DPCH signal is supplied to the convolution device 1030, and at the same time, an expansion code generated by the spread code generator 1035 is supplied to the convolution device 1030. The convolution device 1030 convolves the descrambled downlink DPCH signal symbol by symbol using the spreading code.

The symbols of the convolutional DPCH channel signal are supplied to the demultiplexer 1020, where they are demultiplexed (separated) into TFCI encoded symbols and other signals, such as the DPDCH channel signal, TPC command bits, and pilot bits. TFCI coded symbols are provided to coded symbol rearrangement apparatus 1010. The coded symbol remover 1010 splits the TFCI coded symbols into coded symbols for the DSCH (information symbols of the second TFCI indicator) and encoded symbols for the DCH channel (information symbols of the first TFCI indicator) according to the code length information and position information. The code length information is code length control information based on the ratio of the number of TFCI bits for the DSCH and the number of TFCI bits for the DCH. The position information is information indicating the positions of the encoded symbols for the DSCH channel and the positions of the encoded symbols for the DCH channel, shown in Table 6.

The coded symbol rearrangement device 1010 has any of the structures depicted in FIGS. 18A and 18B. When using any of the structures shown in FIGS. 18A and 18B, the encoded symbol rearrangement apparatus 1010 must individually sequentially output the symbols of the first encoded TFCI and the symbols of the second encoded TFCI. The separated characters of the second encoded TFCI indicator and the symbols of the first encoded TFCI indicator are sequentially supplied to the decoder 1000. The decoder 1000 decodes the symbols of the first encoded TFCI indicator or the symbols of the second encoded TFCI indicator using a code corresponding to the control information (code length information) for a given code length. Thus, the decoder 1000 outputs the bits of the first TFCI or bits of the second TFCI. The decoder 1000 performs the same function as the decoder shown in Fig.11.

In addition, the present invention provides a decoder capable of decoding for corresponding information bit ratios, which corresponds to an encoder for encoding codes of various lengths. Now we describe in detail the operation of the decoder corresponding to one of the embodiments of the present invention. When operating as a decoder corresponding to encoders (6, 2), (7, 2) and (8, 2), this decoder uses Hadamard reverse fast conversion devices for a Walsh encoder with a length of 4. When working as a decoder corresponding to encoders (9, 3), (10, 3) and (11, 3), this decoder uses Hadamard inverse fast conversion devices for a Walsh encoder with a length of 8. When working as a decoder corresponding to encoders (12, 4), (13 , 4) and (14, 4), this decoder uses inverse fast conversion devices damar for a Walsh encoder with a length of 16. When working as a decoder corresponding to an encoder (16, 5), this decoder uses Hadamard inverse fast conversion devices for a Walsh encoder with a length of 16. When working as a decoder corresponding to encoders (18, 6 ), (19, 6), (20, 6), (21, 7), (22, 7), (23, 7), (24, 8), (25, 8), (26, 8), (27, 9), (28, 9), (29, 9) and (32, 10), this decoder uses Hadamard inverse fast conversion devices for a Walsh encoder with a length of 32. For this operation, the decoder must contain an inverse fast execution structureHadamard transforms capable of supporting variable length codes. Thus, the present invention provides a decoder comprising an inverse fast Hadamard transform structure capable of supporting variable length codes.

8. The functioning of the embodiments of the invention

The operation of the encoder, decoder, character mapper, and character mapper will be described with reference to FIGS. 16 and 17.

On Fig shows a diagram of the operation of the encoder and linker encoded characters located in the transmitter, corresponding to one embodiment of the present invention. Referring to FIG. 16, at step 1601, the transmitter decides to encode the bits of the first TFCI pointer (TFCI information bits for the DCH channel) and the bits of the second TFCI pointer (TFCI information bits for the DSCH channel) in HSM mode (hard split mode). At step 1602, the encoder receives the bits of the first TFCI and bits of the second TFCI. In step 1603, the encoder encodes the bits of the first TFCI indicator (32 encoded symbols) and the bits of the second TFCI indicator (32 encoded symbols) in a manner consistent with the present invention. In step 1604, the encoded symbol composer selects encoded symbols having optimal efficiency from the symbols of the first encoded TFCI indicator according to the code selection scheme, and also selects encoded symbols having optimal efficiency from the symbols of the second encoded TFCI indicator according to the code selection scheme. The code selection patterns are identical to the punching patterns shown in Table 5. At step 1605, the encoded character composer composes the selected characters of the first encoded TFCI and the selected characters of the second encoded TFCI in accordance with the character arrangement to obtain optimal time diversity. The character layout template is shown in Table 6. As described in relation to FIG. 15, the operations of steps 1603, 1604 and 1605 can be performed in one process. After step 1605, at step 1606, bits b _{1 are} finally determined, which completes the encoding and character composition process.

On Fig depicts the operation of the decoder and the device rearrangement of coded symbols located in the receiver corresponding to one embodiment of the present invention. Referring to FIG. 17, at step 1701, the receiver receives TFCI encoded symbols transmitted in the TFCI field contained in the DPCCH of the downlink DPCH. At step 1702, the decoder inserts zeros at the symbol positions of the second TFCI encoded indicator included in the received TFCI encoded symbols, according to the symbol positions of the second TFCI encoded indicator, and also creates a first TFCI codeword containing 32 encoded symbols. Next, the decoder inserts zeros at the symbol positions of the first TFCI encoded indicator included in the received TFCI encoded symbols, according to the symbol positions of the first TFCI encoded indicator, and also creates a second TFCI codeword containing 32 encoded symbols. As described with respect to FIGS. 18A and 18B, it is possible to separate the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator using a mask. Information on the positions of the symbols of the first encoded TFCI and symbols of the second encoded TFCI is identical to the template used in step 1604 of FIG. 16. The reason for inserting zeros at the positions of unperforated or unselected characters is the need to ensure the correct operation of the decoder. At step 1703, the decoder calculates correlations for the generated first TFCI codeword and the second TFCI codeword. At step 1704, the decoder outputs the values or indices of the first TFCI codeword and the second TFCI codeword having maximum correlation. At step 1705, the decoder ends the decoding process of the first TFCI codeword and the second TFCI codeword.

The preceding description is for a decoding method, a conversion method c $\genfrac{}{}{0ex}{}{\text{1}}{\text{x}}$ and c $\genfrac{}{}{0ex}{}{\text{2}}{\text{y}}$ to bits b ₁ and a method for converting bits b ₁ to d _m bits for the case where the sum of the information bits of the first TFCI and information bits of the second TFCI in HSM mode is 10. In addition, a description is given of a transceiver, encoder and decoder. Typically, if the sum of the information bits of the first TFCI and the information bits of the second TFCI is less than 10, then the LSM mode is used and the HSM mode is not used. That is, the HSM mode is used only if both the number of information bits of the first TFCI and the number of information bits of the second TFCI are less than 5. Usually, only the encoder is used in HSM (16, 5). Therefore, the HSM mode is not used when the number of information bits of the first TFCI is greater than 5 or the number of information bits of the second TFCI is greater than 5. However, if a new encoder capable of creating 24 types of codes in accordance with the present invention is used, there is no restriction on the number of TFCI information bits , thus allowing the reliable transmission of TFCI information bits. That is, it is possible to determine the codes by which TFCI information bits are to be encoded. Accordingly, it is possible to separately transmit the code of the first TFCI indicator or the code of the second TFCI indicator, or simultaneously transmit the code of the first TFCI indicator and the code of the second TFCI indicator, ensuring reliable transmission.

A detailed description of the present invention will be given for the case where the encoder has the structure shown in Figure 4 and uses the punching pattern shown in Table 4. This invention can also be applied to another case where the encoder has a different structure and uses a different punching pattern.

Example 1. The ratio of the number of information bits of the first TFCI pointer and the number of information bits of the second TFCI pointer is 2: 6

When the ratio of the number of information bits of the first TFCI to the number of information bits of the second TFCI is 2: 6, the normal HSM method can encode the information bits of the first TFCI before transmitting, but it cannot encode the information bits of the second TFCI. However, when using the encoder of the present invention, the information bits of the first TFCI are encoded into 6 characters, 7 characters or 8 characters, and the information bits of the second TFCI are encoded into 18 characters, 19 characters or 20 characters. The sum of the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator encoded by the encoder of the present invention becomes at least 24 and at most 28. When this sum is less than 32, which is the base number of encoded symbols, the easiest way to process these symbols is to transmit only 24 characters or 28 characters in intermittent mode (DTX). This method contributes to simplification, but when it is used in the DTX period, other information cannot be transmitted, which causes excessive consumption of resources. In addition to this, it is not possible to improve the coding efficiency of the information bits of the TFCI pen pointer and the information bits of the second TFCI pointer due to intermittent transmission of encoded symbols.

In Example 1, the encoding method can be changed by prioritizing the first TFCI to improve reliability or efficiency, prioritizing the second TFCI to improve reliability or efficiency, or by increasing the efficiency of both the first TFCI and the second TFCI.

If the first TFCI is prioritized in improving reliability or efficiency, the information bits of the second TFCI are encoded using an encoder (18, 6), encoder (19, 6) or encoder (20, 6), and the information bits of the first TFCI are encoded using encoder (14, 4), encoder (13, 4) or encoder (12, 4). In addition, there is another way of encoding the information bits of the first TFCI using an encoder (6, 2), an encoder (7, 2) or an encoder (8, 2), and then repeatedly transmitting the bits of the first encoded TFCI, thereby increasing reliability or efficiency. In a method of increasing the efficiency or reliability of the code of the first TFCI pointer by encoding the information bits of the first TFCI pointer using an encoder (14, 4), encoder (13, 4) or encoder (12, 4) before encoding in 2 bits, different from 2 real information bits, zeros are inserted. After repeating the first TFCI, the sum of the characters of the repeated first coded TFCI and the characters of the second coded TFCI may exceed 32. If the sum of the characters of the first coded TFCI and the characters of the second coded TFCI exceeds 32, the system is incompatible with the 3GPP standard, which increases the complexity of the hardware funds. Conversely, if the sum of the symbols of the first encoded TFCI and symbols of the second encoded TFCI is less than 32, as in Example 1, there are less restrictions on the choice of code compared to the case when the sum of the information bits of the first TFCI and the information bits of the second TFCI is 10 That is, when the sum of the information bits of the first TFCI and the information bits of the second TFCI is 10, you must select codes in which the sum of the encoded characters is 32. However, if the sum of the encoded characters is less than 3 2, although the maximum coding rate is used for the information bits shown in Example 1, the coding rate of the TFCI information bits can be set so that the efficiency increases under conditions when the sum of the encoded symbols becomes 32.

At the same time, if Example 1 sets the priority of the second TFCI pointer in improving reliability or efficiency, the information bits of the first TFCI pointer are encoded using an encoder (6, 2), encoder (7, 2) or encoder (8, 2), and the information bits of the second TFCI are encoded using an encoder (26, 8), an encoder (25, 8), or an encoder (24, 8). Otherwise, it is possible to encode information bits using an encoder (20, 6), an encoder (19, 6), or an encoder (18, 6), and subsequently repeatedly transmit the encoded bits to increase, thus, reliability or efficiency. After repeating the second TFCI, the sum of the characters of the first coded TFCI and the characters of the repeated second coded TFCI may exceed 32. However, if the sum of the characters of the first coded TFCI and the characters of the second coded TFCI is greater than 32, the system is not compatible with the 3GPP standard.

A way to increase the reliability or efficiency of both the first TFCI and the second TFCI in Example 1 is to increase the number of information bits of the first TFCI to 3 before encoding, and the number of information bits of the second TFCI to 7 before the coding. That is, before transmitting the information bits of the first pointer TFCIs are encoded using an encoder (9, 3), encoder (10, 3) or encoder (11, 3), and information bits of the second TFCI pointer are encoded using an encoder (23, 7), encoder (22, 7) or encoder ( 21, 7). This method can only be used if the sum of the encoded characters does not exceed 32. When the sum of the encoded characters exceeds 32, the above problem occurs. Another way is to encode the information bits of the first TFCI with an encoder (6, 2), encoder (7, 2) or an encoder (8, 2), and the information bits of the second TFCI with an encoder (18, 6), encoder (19 , 6) or the encoder (20, 6), and then repeatedly transmit the encoded bits. The sum of the transmitted encoded bits in a repeatable manner should not exceed 32. There are 3 types of encoders for encoding information bits of the first TFCI, and there are also 3 types of encoders for encoding information bits of the second TFCI. Of these encoders, the encoder having the best performance is selected. As for the number of characters repeated by the encoders, the characters of the selected encoder are retransmitted with much greater multiplicity.

Example 2. The ratio of the information bits of the first TFCI to the number of information bits of the second TFCI is 3: 4

When the ratio of the number of information bits of the first TFCI to the number of information bits of the second TFCI is 3: 4, i.e., if both the number of information bits of the first TFCI and the number of information bits of the second TFCI are less than 5, the usual HSM method (16 , 5) encodes before transmitting the information bits of the first TFCI and the information bits of the second TFCI individually or sequentially. However, when using the encoder of the present invention, the information bits of the first TFCI are encoded into 9 characters, 10 characters or 11 characters, and the information bits of the second TFCI are encoded into 12 characters, 13 characters or 14 characters. The sum of the characters of the first encoded TFCI and the characters of the second encoded TFCI encoded with the encoder of the present invention becomes a maximum of 25. When this sum is less than 32, which is the base number of encoded characters, the simplest way to process these characters is to transmit only 21 characters or 24 characters in intermittent mode (DTX). This method contributes to simplification, but when it is used in the DTX period, other information cannot be transmitted, which causes excessive consumption of resources. In addition to this, it is not possible to improve the coding efficiency of the information bits of the first TFCI and information bits of the second TFCI due to intermittent transmission of encoded symbols.

In Example 2, the coding method can be changed by prioritizing the first TFCI to improve reliability or efficiency, prioritizing the second TFCI to improve reliability or efficiency, or by increasing the efficiency of both the first TFCI and the second TFCI.

If the first TFCI is prioritized in improving reliability or efficiency, the information bits of the second TFCI are encoded using an encoder (12, 4), encoder (13, 4) or encoder (14, 4), and the information bits of the first TFCI are encoded using encoder (20, 6), encoder (19, 6) or encoder (18, 6). In addition, there is another way to encode the information bits of the first TFCI using an encoder (9, 3), an encoder (10, 3) or an encoder (11, 3) and then repeatedly transmitting the bits of the first TFCI encoded, thereby increasing the reliability or efficiency. In a method of increasing the efficiency or reliability of the code of the first TFCI pointer by encoding the information bits of the first TFCI pointer using an encoder (20, 6), encoder (19, 6) or encoder (18, 6) before encoding in 3 bits that differ from 3 real information bits, zeros are inserted. After repeating the first TFCI, the sum of the characters of the repeated first coded TFCI and the characters of the second coded TFCI may exceed 32. If the sum of the characters of the first coded TFCI and the characters of the second coded TFCI exceeds 32, the system is incompatible with the 3GPP standard, which increases the complexity of the hardware funds. Conversely, if the sum of the symbols of the first encoded TFCI and symbols of the second encoded TFCI is less than 32, as in Example 2, there are less restrictions on the choice of code compared to the case when the sum of the information bits of the first TFCI and the information bits of the second TFCI is 10 That is, when the sum of the information bits of the first TFCI and the information bits of the second TFCI is 10, you must select codes in which the sum of the encoded characters is 32. However, if the sum of the encoded characters is less than 3 2, although the maximum coding rate is used for the information bits shown in Example 2, the coding rate of the TFCI information bits can be set so that the efficiency increases under conditions when the sum of the encoded symbols becomes 32.

At the same time, if Example 2 sets the priority of the second TFCI pointer in improving reliability or efficiency, the information bits of the first TFCI pointer are encoded using an encoder (9, 3), encoder (10, 3) or encoder (11, 3), and the information bits of the second TFCI are encoded using an encoder (23, 7), an encoder (22, 7), or an encoder (21, 7). Otherwise, it is possible to encode information bits using an encoder (14, 4), an encoder (13, 4) or an encoder (12, 4), and subsequently repeatedly transmit the encoded bits to increase, thus, reliability or efficiency. After repeating the second TFCI, the sum of the characters of the first coded TFCI and the characters of the repeated second coded TFCI may exceed 32. However, if the sum of the characters of the first coded TFCI and the characters of the second coded TFCI is greater than 32, the system is not compatible with the 3GPP standard.

And finally, a way to increase the reliability or efficiency of both the first TFCI and the second TFCI in Example 2 is to increase the number of information bits of the first TFCI and information bits of the second TFCI so that the sum of the information bits of the first TFCI and the information bits of the second TFCI has become equal to 10, and the use of an encoder suitable for encoding an increased number of information bits. For example, before transmission, you can use the method of encoding the information bits of the first TFCI pointer using an encoder (14, 4), the encoder (13, 4) or the encoder (12, 4), and the information bits of the second TFCI pointer using the encoder (18, 6 ), encoder (19, 6) or encoder (20, 6). This method can only be used when the sum of the information bits of the first TFCI and the information bits of the second TFCI does not exceed 10, and the sum of the encoded symbols does not exceed 32. If the sum of the encoded symbols exceeds 32, the above problem occurs. Another way is to encode the information bits of the first TFCI pointer using an encoder (9, 3), encoder (10, 3) or encoder (11, 3), and the information bits of the second TFCI pointer - using an encoder (12, 4), encoder. (13, 4) or encoder (14, 4) and subsequent repeated transmission of the encoded bits. The sum of the repeatedly transmitted coded bits should not exceed 32. There are 3 types of encoders for encoding the information bits of the first TFCI, and there are also 3 types of encoders for encoding the information bits of the second TFCI. Of these encoders, the encoder having the best performance is selected. As for the number of characters repeated by the encoders, the characters of the selected encoder are retransmitted with much greater multiplicity. In addition to the described, a coding rate change method and a multiple transmission method for transmitting information bits of the first TFCI and information bits of the second TFCI with high reliability or efficiency can be combined.

The criteria for determining the code selection method for the HSM mode described for Example 1 and Example 2 are summarized below.

Criterion 1: The number of information bits of the first TFCI or information bits of the second TFCI exceeds 5 bits

- If the priority of the first TFCI is set, the transmitter fixes the encoder for the second TFCI, and then during the transfer changes the coding rate of the first TFCI or encodes the first TFCI taking into account the number of real information bits, and then transmits the encoded bits repeatedly.

- If the priority of the second TFCI indicator is set, the transmitter fixes the encoder for the first TFCI indicator, and then during the transmission changes the coding rate of the second TFCI indicator or encodes the second TFCI indicator taking into account the number of real information bits, and then transmits the encoded bits repeatedly.

- If the priority of both the first TFCI indicator and the second TFCI indicator is set, the transmitter performs encoding with a change in the coding rates of the first TFCI indicator and the second TFCI indicator or performs encoding taking into account the number of real information bits with subsequent repeated transmission of the encoded bits. You can combine the method of changing the coding rate and the method of repeated transmission.

Criterion 2: The number of information bits of the first TFCI indicator or the number of information bits of the second TFCI indicator does not exceed 5 bits

Before transmitting, the transmitter encodes the information bits of the first TFCI and the information bits of the second TFCI using an encoder (16, 5).

- The rest is similar to that described in Criterion 1.

A code selection method based on the above criteria and using the punching pattern shown in Table 5 and the coding speed shown in Table 1 are described below with reference to FIG. As shown in FIG. 12, the need to transmit the first TFCI (first information bits) and second TFCI (second information bits) arises at step 1201. That is, when the Node B is required to transmit the DSCH to the user equipment, the transmitter receives the pointer TFCI for DSCH and TFCI for DCH. At 1202, it is determined whether the sum of the first information bits and the second information bits is 10. If the sum of the first information bits and the second information bits is 10, then the transmitter determines at 1208 a code to be used for the first information bits and the second information bits.

The code selection process in step 1208 will be described for the case where the ratio of the first information bits to the second information bits is 3: 7. In this case, the encoder for the first information bits is an encoder (9, 3), an encoder (10, 3) or an encoder (11, 3), and the encoder for the second information bits is an encoder (23, 7), encoder (22, 7) or encoder (21, 7). The sum of the coded bits should be 32. The criterion for choosing three types of coding rates in accordance with the types of information bits is: (1) prioritization of the first information bits to add 2 additional characters, (2) priority of the second information bits to add 2 additional characters characters or (3) adding one additional character to both the first information bits and the second information bits. After determining at step 1208 the coding rate to be used for the first information bits and second information bits, at step 1209, the transmitter encodes the first information bits and second information bits with a given determined coding rate. At step 1210, the transmitter multiplexes the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator.

However, if it is determined in step 1202 that the sum of the first information bits and the second information bits is less than 10, then in step 1203, the transmitter determines whether the number of the first information bits or the second information bits exceeds 5. If the number of the first information bits or the number of second information bits exceeds 5, the transmitter proceeds to step 1204. However, if both the number of first information bits and the number of second information bits does not exceed 5, the transmitter proceeds to step 1221. At step 1221, the transmitter determines using whether encoder (16, 5) to encode the first information bits and second information bits. If the transmitter decides not to use the encoder (16, 5), it proceeds to step 1206. Otherwise, if the transmitter decides to use the encoder (16, 5), it proceeds to step 1209. At step 1204, the transmitter decides whether to use the DTX mode when transmitting the first information bits or the second information bits. If the transmitter decides to use the DTX mode, it proceeds to step 1208. Otherwise, if the transmitter decides not to use the DTX mode, it proceeds to step 1205.

The execution of step 1208 will be described for the ratio of the first information bits and the second information bits equal to 3: 4. In this case, the encoder for the first information bits is the encoder selected from the encoder (9, 3), the encoder (10, 3) and the encoder (11, 3), and the encoder for the second information bits is the encoder selected from the encoder (12, 4 ), encoder (13, 4) and encoder (14, 4). At 1208, if the DTX mode is used in the case where the number of first information bits and the number of second information bits each do not exceed 5, then there are no restrictions on the choice of encoders, but the sum of the encoded characters should not exceed 32.

At step 1205, the transmitter decides whether to increase the reliability or efficiency of both the first TFCI and the second TFCI before transmitting. If the transmitter has decided to increase the reliability or efficiency of both the first TFCI and the second TFCI before transmitting, at step 1207, it selects one of the following: a method for increasing the coding rate, a method for repeating transmission, or a method obtained by combining these two methods. At 1208, the transmitter determines the code to be used for the first TFCI and the second TFCI in accordance with the method selected at 1207. At 1209, the transmitter encodes the information bits of the first TFCI and the information bits of the second TFCI using the selected method, and then, in step 1210, the symbols of the first encoded TFCI and the symbols of the second encoded TFCI are multiplexed. If at step 1207 the transmitter decided to increase the reliability or efficiency of the first TFCI and second TFCI before transmitting by using the multiple transmission method, then at step 1209, the transmitter repeats the characters of the first encoded TFCI and the symbols of the second encoded TFCI, and then multiplexes at 1210 them. Otherwise, the transmitter repeats the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator encoded in step 1209, in step 1210.

If at step 1205 the transmitter decided to increase the reliability or efficiency of either the first TFCI or the second TFCI before transmitting, then the transmitter at step 1206 chooses which priority to set: the first TFCI or the second TFCI. The transmitter sets the priority of the first TFCI, if the information bits of the first TFCI should be transmitted with high reliability, regardless of the number of these bits. The transmitter sets the priority of the second TFCI, if the information bits of the second TFCI must be transmitted with high reliability as a preparation before a situation arises where Node Bs other than Node B receiving the DSCH cannot transmit information bits of the second TFCI for DSCH, when the user equipment is in the soft handoff area. In addition, the transmitter sets the priority of the second TFCI, if the information bits of the second TFCI should be transmitted with high reliability, regardless of the number of these bits. If, at step 1206, the transmitter decided before transmitting to increase the reliability or efficiency of either the first TFCI or the second TFCI, then at step 1207, the transmitter determines how to increase reliability or efficiency of either the first TFCI or the second TFCI before using the method of increasing speed encoding, a repeating transmission method, or a method obtained by combining these two methods. At 1208, the transmitter determines the code to be used for the first TFCI and the second TFCI according to the method determined at 1207. At 1209, the transmitter encodes the information bits of the first TFCI and the information bits of the second TFCI using this specific method, and then at 1210, multiplexes the symbols of the first encoded TFCI indicator and the symbols of the second encoded TFCI indicator. If the transmitter in step 1207 decided to increase the reliability or efficiency of either the first TFCI or the second TFCI by using a method of increasing the coding rate, then in step 1210, the transmitter multiplexes the symbols of the first encoded TFCI and the symbols of the second encoded TFCI, encoded in 1209. If, at step 1207, the transmitter decided before transmitting to increase the reliability or efficiency of either the first TFCI or the second TFCI by using a non-uniform After transmitting, then at step 1209, the transmitter repeats the symbols of the first encoded TFCI and symbols of the second encoded TFCI, and then multiplexes them at 1210. Otherwise, the transmitter repeats the symbols of the first encoded TFCI and second encoded TFCI, encoded at 1209, at step 1210.

As described above, in the embodiment of the present invention, it is possible to encode / decode various types of TFCI bits using a single encoder / decoder block diagram. In addition, in this embodiment, TFCI symbols encoded using various coding techniques are multiplexed so that TFCI symbols are evenly distributed before transmission. For the case of 10 input information bits, TFCI coding is performed at a ratio selected from the following: 1: 9, 2: 8, 3: 7, 4: 6, 5: 5, 6: 4, 7: 3, 8: 2 and 9: 1, depending on the type and characteristics of the data transmitted on the DSCH and DCH, which contributes to the flexibility of the HSM mode, which is superior to the LSM mode in terms of signaling and time delay. In addition, the encoder encodes the TFCI bits for the DCH channel and the TFCI bits for the DSCH channel, and then stores the encoded TFCI symbols for the DCH channel and the encoded TFCI symbols for the DSCH channel in the storage device, thereby providing fast information processing.

Although the invention has been considered and described with reference to a specific preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (22)

1. A method for displaying the first TFCI encoded (transport format combining indicator, FFAT) symbols and second encoded TFCI symbols in a frame in a transmitter of a mobile communication system, for encoding k first TFCI bits and (10-k) second TFCI bits, wherein the sum of the first encoded TFCI symbols and the second encoded TFCI symbols is thirty-two, and this method comprises the steps of: multiplying said first and second encoded TFCI symbols such that the first encoded TFCI symbols and the second encoded TFCI c the characters are evenly distributed in accordance with the transmission mode and the data rate of the frame and thirty-two encoded characters are output; and displaying thirty-two multiplexed encoded symbols per frame, observing the number of encoded symbols that can be displayed in one frame, determined in accordance with the transmission mode and the data rate of the frame. 2. The method according to claim 1, characterized in that the said first encoded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{1}}{\text{i}}$ multiplex in position b, calculated by the formula:

where n represents the total number of said first coded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said first encoded TFCI symbols. 3. The method according to claim 1, characterized in that the said second encoded TFCI symbols are multiplexed at position b, calculated by the formula:

where n represents the total number of said first coded TFCI symbols; m represents the total number of said second encoded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said second encoded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ . 4. The method according to claim 1, characterized in that if said number of encoded symbols that can be displayed in one frame is thirty, then thirty encoded symbols are displayed in said frame, excluding one arbitrary symbol from said first encoded TFCI symbols and one arbitrary symbol of said second encoded TFCI symbols. 5. The method according to claim 4, characterized in that said one arbitrary symbol from said first encoded TFCI symbols is the last encoded symbol from these first encoded TFCI symbols, and said one arbitrary symbol from said second encoded TFCI symbols is the last encoded character of these second encoded TFCI characters. 6. The method according to claim 1, characterized in that if the said number of encoded characters that can be displayed in one frame is thirty, then thirty encoded characters are displayed in the said frame, excluding two arbitrary coded characters from the first coded TFCI- characters or two arbitrary coded characters from said second coded TFCI characters. 7. The method according to claim 1, characterized in that if the said number of encoded symbols that can be displayed in one frame is one hundred and twenty, then the thirty-two multiplexed encoded symbols are repeated three times, the first twenty-four encoded symbols of the thirty two multiplexed encoded characters are repeated again, and then displayed in the said frame. 8. The method according to claim 1, characterized in that if said number of encoded symbols that can be displayed in one frame is thirty-two, then said thirty-two multiplexed encoded symbols are displayed in said frame. 9. The method according to claim 1, characterized in that if the said number of encoded characters that can be displayed in one frame is one hundred twenty-eight, then the thirty-two multiplexed encoded characters are repeated four times and then displayed in the said frame. 10. Device for transmitting first TFCI bits (transport format combining indicator, FFEP) and second TFCI bits in a frame in a transmitting device of a mobile communication system, comprising at least one encoder designed to encode k first TFCI bits with a first coding rate for the purpose of outputting (3k + 1) the first encoded TFCI symbols and encoding (10-k) the second TFCI bits with a second encoding rate to output (31-3k) the second encoded TFCI symbols; a coded symbol composer for multiplexing coded symbols such that said first encoded TFCI symbols and said second encoded TFCI symbols are evenly distributed in accordance with a transmission mode and a data rate of a frame, and for outputting said multiplexed encoded symbols in accordance with a number encoded characters that can be transmitted in a single frame. 11. The device of claim 10, further comprising a selector for selecting said first TFCI bits and said second TFCI bits in accordance with the k value and supplying the selected TFCI bits to the encoder. 12. The device according to claim 10, characterized in that said encoded symbol mapper multiplexes encoded symbols such that said first encoded TFCI symbols c $\genfrac{}{}{0ex}{}{\text{1}}{\text{i}}$ are displayed at position b, calculated by the formula

where n represents the total number of said first coded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said first encoded TFCI symbols. 13. The device according to claim 10, characterized in that said encoded symbol mapper multiplexes the encoded symbols such that said second encoded symbols $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ are displayed at position b, calculated by the formula:

where n represents the total number of said first coded TFCI symbols; m represents the total number of said second encoded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said second encoded TFCI symbols. 14. A method for transmitting first TFCI bits (transport format combining indicator, FFEP) and second TFCI bits in a frame in a transmitter of a mobile communication system, comprising the steps of: encode k first TFCI bits with a first coding rate for output (3k + 1 ) the first encoded TFCI characters; encode (10-k) second TFCI bits with a second coding rate to output (31-3k) second encoded TFCI symbols; multiplexing said first and second encoded TFCI symbols such that said first encoded TFCI symbols and said second encoded TFCI symbols are uniformly distributed according to a transmission mode and a frame data rate; and outputting the multiplexed encoded symbols in accordance with the number of encoded symbols that can be transmitted in one frame. 15. The method according to 14, characterized in that the said first encoded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{1}}{\text{i}}$ output at position b, calculated by the formula:

where n represents the total number of said first coded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said first encoded TFCI symbols. 16. The method according to 14, characterized in that the said second encoded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ output at position b, calculated by the formula:

where n represents the total number of said first coded TFCI symbols; m represents the total number of said second encoded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said second encoded TFCI symbols. 17. A device for decoding k first TFCI bits and (10-k) second TFCI bits in a receiver of a mobile communication system for receiving (3k-1) first encoded TFCI symbols for a DCH (dedicated channel, VC) and (31-3k) second encoded TFCI symbols for a DSCH channel (common downlink channel, OKNLS), and comprising a coded symbol rearrangement apparatus for partitioning for reconfiguring said first encoded TFCI symbols and second encoded TFCI symbols transmitted via DPCH (dedicated physical channel), in accordance with the value of k; and at least one decoder for decoding said first encoded TFCI symbols to output said k first TFCI bits and decoded said second TFCI symbols to output said (10-k) second TFCI bits. 18. The device according to 17, characterized in that the said device for rearranging the encoded symbols allocates the aforementioned first encoded TFCI symbols c $\genfrac{}{}{0ex}{}{\text{1}}{\text{i}}$ located at positions b calculated by the following formula from encoded symbols obtained by multiplexing said first encoded TFCI symbols and said second encoded TFCI symbols:

where n represents the total number of said first coded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said first encoded TFCI symbols. 19. The device according to 17, characterized in that the said device for rearranging the encoded symbols selects said second encoded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ located at positions b calculated by the following formula from encoded symbols obtained by multiplexing said first encoded TFCI symbols and said second encoded TFCI symbols:

where n represents the total number of said first coded TFCI symbols; m represents the total number of said second encoded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said second encoded TFCI symbols. 20. A method for decoding k first TFCI bits and (10-k) second TFCI bits in a receiver of a mobile communication system for receiving (3k-1) first encoded TFCI symbols for a DCH (dedicated channel, VC) and ( 31-3k) second encoded TFCI symbols for a DSCH (common downlink channel, OKNLS), and comprising the steps of: separating said first encoded TFCI symbols and said second encoded TFCI symbols transmitted on a DPCH (dedicated) physical channel, VFC) in accordance with the value k; decoding said first coded TFCI symbols to output said k first TFCI bits; and decoding said second encoded TFCI symbols to output said (10-k) second TFCI bits. 21. The method according to claim 20, characterized in that said first coded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{1}}{\text{i}}$ located at positions b calculated by the following formula are extracted from the coded symbols obtained by multiplexing said first encoded TFCI symbols and said second encoded TFCI symbols:

where n represents the total number of said first coded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said first encoded TFCI symbols. 22. The method according to claim 20, characterized in that the said second encoded TFCI symbols with $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ located at positions b calculated by the following formula are extracted from the coded symbols obtained by multiplexing said first encoded TFCI symbols and said second encoded TFCI symbols:

where n represents the total number of said first coded TFCI symbols; m represents the total number of said second encoded TFCI symbols; i represents an index indicating an arbitrary encoded symbol of said second encoded TFCI symbols.

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