RU2276835C1 - Error detection device - Google Patents

Abstract

FIELD: radio-metering technology.

SUBSTANCE: proposed device that can be used for separation of erroneous characters from data sequence has first modulo two adder 1, second modulo two adder 2, third modulo two adder 3, first comparator 4, first flip-flop 5, second flip-flop 6, third flip-flop 7, first counter 8, second counter 9, shift register 10, and fourth flip-flop 11.

EFFECT: simplified design, enhanced reliability and speed, enlarged frequency range of device.

1 cl, 2 dwg

Description

The invention relates to radio measurement technology and can be used in error analyzers (devices for measuring the fidelity of information transmission in digital paths) for monitoring communication channels.

The error detector solves the following problems:

a) the formation of an internal test sequence;

b) synchronization of the internal test sequence with the input external test sequence;

c) isolating errors from the input test sequence by comparing the input external and internal test sequences;

d) counting the number of errors by the error counter.

The test sequence is fed to the control object, from which it is sent to the error analyzer, to check the quality of the control object. As a test sequence, the most often used pseudo-random sequence (PSP) of maximum length (M-sequence).

Known devices for detecting errors [1], which use the systematic properties of M-sequences, which allow sufficiently accurate measurement of the number of errors. The entire operation of such devices with each attempt to enter the synchronization mode can be divided into three stages: setting the initial state, recording information and checking for the absence of false synchronization. Upon a successful attempt to enter the synchronization mode, the device begins its main work - detecting and analyzing the error stream. By determining the fact of false synchronization of the device and prohibiting its operation (prohibiting error counting) for the time required for resynchronization, the measurement accuracy is increased, since it prohibits the registration of errors, which may include errors that appear at the input of the error counter as a result false sync devices and missing in the input sequence. The time required to verify the absence of false synchronization and (if necessary) re-synchronization of the device is 3n clock intervals, where n is the number of bits (length) of the shift register into which the input information is recorded.

, так как если на этапах записи информации или проверки отсутствия ложной синхронизации во входной внешней М-последовательности будет присутствовать хотя бы одна ошибка (в каком-либо из n битов информации), то такие устройства (детекторы ошибок) будут возвращаться в исходное начальное состояние, при этом подсчет ошибок производиться не будет.The disadvantage of such devices is the lack of noise immunity - the inability to synchronize when receiving an input external M-sequence with a maximum time-average error rate

, since if at the stages of recording information or checking the absence of false synchronization in the input external M-sequence there will be at least one error (in any of the n bits of information), such devices (error detectors) will return to their original initial state, no errors will be counted.

As a prototype adopted more noise-resistant and accurate circuit device for detecting errors, described in [2].

This circuit contains the first 1, second 2, third 3, fourth 14 adders modulo two (SMD), comparator 4, first 5, second 6, third 7, fourth 8, fifth 15 triggers, first 9, second 10, third 13, fourth 16 counters, element "And" 11, shift register (PC) 12.

After turning on the device, the synchronization pulse (initial installation) sets the triggers 6, 7 and 8, counters 9, 13, 16 to the initial state, at which the log level is set at the output of the counters 9, 16, the direct output of trigger 7. "0", and on the direct output of the trigger level 8 log. "1". At the same time, at the output of trigger 6 and counter 13, the log level is set to “0”, which allows counter 9 to count cycles. The counter module of the counter 16, equal to the number (m), and the counter module of the counter 13, equal to the number (1 + α), are pre-set by the control signals at the corresponding inputs of the device. Comparator 4 starts comparing the input external SRP and the internal SRP formed at the output of the SMD3. In this case, the error pulses from the output of the comparator 4 pass to the error counter 13 and to the circuit "And" 11. The circuit "And" 11 is opened by the levels "log.1" from the inverse output of the trigger 7 and the direct output of the trigger 8. Therefore, the error pulses will affect PC12 through SMD14 until counter 9 counts the number of clock pulses to n. If in this case error-free information is recorded in PC12, i.e. The error detector PC will go into synchronism with the PC of the “transmitter”, then in the next step, when the inverse output of trigger 7 is set to “log.0” and the clock count C16 will be enabled, and the error count C13, and the circuit “And” 11 will be closed, counter 13 for the number of clock periods m, with the correct choice of m and (1 + α), does not count up its counter module (1 + α) (with the expected distribution of errors in the input SRP). An impulse will appear at the output of counter 16, which will set “log.0” at the direct output of trigger 8, which will close the “And” 11 circuit and resolve the error count C10, i.e. The third phase of synchronization will end happily.

If at the second synchronization stage in PC12 at least one error is recorded that is accepted in the input memory bandwidth, then at the third synchronization stage C13, for the number of clock periods m will have time to calculate (1 + α) to its account module and a positive pulse at its output will establish the circuit devices in the initial state.

This process is repeated until the error detector PC12 becomes in synchronism with the shift register of the “transmitter”. After that, the device begins to work as an error detector of the input external memory bandwidth.

If during the normal functioning of the device a malfunction occurs in the shift register 12, pulses will appear at the output of the SMD2, which, acting on the input of "setting logical zero" of the second trigger, will set "log.0" at its output, the first counter will start working and the device will go back to the second stage of work during synchronization - recording information, then to the third stage, etc. until the device is automatically resynchronized.

The high noise immunity of this device allows it to be used in the analysis of an external input SRP that has passed the object of control, and in cases where instead of the device [1] other methods of analysis of the test SRP are required, for example, measuring the signal delay time in the control object. But this circuit of the error detection device [2] is complicated due to the hardware of the verification steps for the absence of false synchronization and disconnection of the feedback circuit (the effect of the error signal on the internal memory generator), which reduces its reliability, narrows the range of operating frequencies due to the long transit time and signal processing in the device.

The technical problem to which this invention is directed is to simplify the circuit, increase reliability, speed, expand the operating frequency range of the device for detecting errors.

The essence of the invention lies in the fact that in a device containing a serially connected comparator, the first trigger, the first adder modulo two, the second adder modulo two, the output of which is the installation input of the device, the second trigger by the R-input, the first counter, the second input of which is the device’s clock pulse input, and the third trigger with a C-input, the R-input of which is connected to the output of the second trigger, the second input of the first counter is connected to the C-input of the fourth trigger, whose D-input is an information input device, and the output is connected to the second input of the first adder modulo two and the first input of a comparator, the other input of which is connected to the second input of the second adder modulo two and to the output of the third adder modulo two, the first, second and third inputs of which are connected respectively the first, second, and third output of the shift register, the second counter, the first input of which is connected to the output of the comparator and is the output of the device, the output of the fourth trigger is connected to the input of the shift register, the second input of the second counter connected to the inverse output of the third trigger, the direct output of which is connected to the S-input of the second trigger, and the output of the second counter is the information output of the device.

Figure 1 presents the structural diagram of the prototype, where indicated:

1 - the first adder modulo two (SMD);

2 - second SMD;

3 - third SMD;

4 - a comparator;

5 - the first trigger;

6 - second trigger;

7 - the third trigger;

8 - the fourth trigger;

9 - the first counter;

10 - second counter;

11 - the element "And";

12 - shift register (PC);

13 - the third counter;

14 - fourth SMD;

15 - fifth trigger;

16 - the fourth trigger.

Figure 2 presents the structural diagram of the inventive device, where indicated:

1 - the first adder modulo two (SMD);

2 - second SMD;

3 - third SMD;

4 - a comparator;

5 - the first trigger;

6 - second trigger;

7 - the third trigger;

8 - the first counter (cycles modulo n + 1);

9 - second counter (errors);

10 - shift register (PC);

11 - the fourth trigger.

Designation of trigger inputs:

R - input setting logical zero;

C - counting (clock) input;

D - information input;

S - input setting logical units.

The device (Fig. 2) contains series-connected SMD1, SMD2, the output of which is the installation input of the device, and the second input SMD2 is connected to the output of SMD3 and one of the inputs of the comparator 4, the output of which through trigger 5 is connected to the first input of SMD1, the trigger is connected in series 6, the R-input of which is connected to the installation input of the device, the counter 8, the second input of which is the input of the clock pulses of the device, and trigger 7 C-input, the R-input of which is connected to the output of the trigger 6; counter 9, the first input of which is connected to the output of the comparator 4 and is the error output of the device, the second input is the inverse output of the trigger 7, the non-inverse output of which is connected to the S-input of the trigger 6, and the output of the counter 9 is the information output of the device; shift register (PC) 10, the input of which is connected to the output of the trigger 11, the other input of the comparator 4 and the second input SMD1, the first, second and third outputs PC10 are connected respectively to the first, second and third inputs SMD3; D-input of the trigger 11 is the information input of the device, and the C-input is connected to the clock input of the device.

, необходимо количество ошибок, подсчитанное счетчиком ошибок, поделить на увеличенное на единицу число точек подключения СМД3 к PC10, что может быть выполнено автоматически в блоке 9 или внешней аппаратурой. Таким образом, устройство начинает работать как детектор ошибок входной внешней ПСП после этапов начальной установки и записи входной информации в PC10.The operation of the error detector is as follows. After turning on the device, the synchronization impulse (initial installation) sets triggers 6 and 7, counter 8 to its initial state, at which the output “counter 0” sets the level “log.0” at the direct output of the trigger 7, and the level “log” is set at the inverse output of the trigger 7. one". At the same time, at the output of trigger 6, the level “log.0” will be set, which allows the counter 8 to count cycles. Comparator 4 starts comparing the input external SRP and the internal SRP formed at the output of the SMD3. In this case, the error pulses from the output of the comparator 4 pass to the error counter 9, the count of which is prohibited by the level “log.1” from the inverse output of the trigger 7 until the clock counter 8 counts to its account module (n + 1). After that, the signal from the output of the clock counter 8 trigger 7 is set to the state "log.1". In this case, the level “log.0” from the inverted output of trigger 7 resolves the error count to counter 9. As noted below, to correctly determine the number of errors in the received sequence with single errors (error interval ≥n · T _t ) and error rate

, the number of errors calculated by the error counter must be divided by the number of connection points for SMD3 to PC10 increased by one, which can be performed automatically in block 9 or with external equipment. Thus, the device begins to work as an error detector of the input external memory bandwidth after the steps of initial installation and recording of input information in PC10.

The functions and operation of SMD2, comparator 4 and trigger 5 are similar to the functions and work in the prototype.

The inventive structure of the error detector allows you to abandon the control of the phase shift of the internal SRP, formed at the output of the SMD3 selected error pulses. Comparison of the generated internal and received external memory bandwidth and the allocation of error pulses is carried out by the comparator. In this case, the formation of the internal memory bandwidth is performed by a filter on the shift register 10 and SMD3, the connection points of which to PC10 are the same as in the generator of the transmitting part of the control system, which generates a test signal in the form of the memory bandwidth.

Obviously, it is necessary to count the number of errors in the input SRP that has passed the test object through a time interval equal to n · T _t , where n is the length (number of bits) of PC10; T _t - the period of the clock frequency after turning on the device and the arrival of the installation pulse, since PC10 must be filled with input information. It is obvious that if PC10 is filled with the correct information, then the correct bit of the internal memory bandwidth appears at the output of the SMD3. If an error is recorded as part of the input information in PC10, then an SMD3 output generates an error bit of the internal memory bandwidth at the moment when the “error” enters the PC10 trigger, to which the SMD3 is connected. Thus, for the correct determination of the number of errors in the input external SRP for a certain time interval in the case when the error coefficient of this sequence is K _OSH. ≤1 / n and single errors (with an interval between errors greater than or equal to n · T _t ), which is performed in most modern communication channels, divide the rather total number of errors, calculated by the error counter 9, by the number of connection points SMD3 to PC10 increased by one. The increase in unit number, which is divided by the number of errors calculated by the error counter, is caused by the fact that at the output of the comparator 4 there is still an error when it is written to the fourth trigger (figure 2) (after the error arrives at the information input of the device). In the clock intervals, where the internal and external memory bandwidth coincide at the output of the comparator, there is a "log.0". If the bits of the internal and external memory bandwidth do not match, “log.1” is issued to the output of the comparator during the period of clock pulses.

The practical implementation of the blocks of the proposed device can be performed on the following mass-produced circuits:

- blocks 1, 2, 3, 4 - on two-input EXCLUSIVE OR elements that are part of microcircuits, for example, K555LP5, KM555LP5, where conclusions 1 and 2, 4 and 5, 9 and 10, 12 and 13 are inputs, and 3, 6, 8, 11 outputs, respectively (for clock frequencies of bandwidth less than 10 MHz) [3], 100LP107, 500LP107 (for clock frequencies of bandwidth less than 100 MHz) [4]. The presence of the connections of the outputs of bits PC12 with the group of inputs SMD3 is determined by the type of characteristic polynomial of the particular received M-sequence;

- вывод 6 (11) должен быть подан уровень "лог.0" [4];- blocks 5, 10, 11 - on the D-flip-flops of the KM555TM2 chip (two D-flip-flops in one housing). At the same time, inputs D involved in the device diagram are output 2 (12), R is output 1 (13); C - pin 3 (11), direct output - pin 5 (9) of the microcircuit. [3] On the D-flip-flops of the K500TM131 chip (two D-flip-flops in one housing). At the same time, inputs D involved in the device diagram are output 7 (10), R is output 4 (13); C - pin 9, direct output - pin 2 (15). In this case, the input

- pin 6 (11) should be given the level of "log.0"[4];

- blocks 6, 7 - on j-flip-flops of K555TV9 chip (two j-k flip-flops in one case);

- blocks 8, 9 - on K155IE2 microcircuits (binary decimal 4-bit counter). Involved according to the device diagram, the counter input of clock or error pulses (input 1) is input C1 (pin 14 of the microcircuit), the general reset input with stopping the count (input 2) is inputs & R0 (pin 2 and 3 of the microcircuit) connected together. In this case, the output Q0 (terminal 12) is connected to the input C2 (terminal 1) of the microcircuit. To increase the capacity of the counter to the required number of microcircuits, K155IE2 are connected in series, while the output Q3 (terminal 11) of the previous microcircuit is connected to the input C1 (terminal 14) of the subsequent one [3, 4].

The device is powered from a +5 V source for K155 and K555 series microcircuits and from a source - 5.2 V for 100, K500 series microcircuits. At the same time, the findings of 7 K555LP5, KM555LP5, KM555TM2 microcircuits, the output of 8 K555TV9 microcircuits, the output of 10 K155IE2 microcircuits are connected to the device case, and the outputs of 14 K555LP5, KM555LP5, KM555TM2 microcircuits, the output of 16 K55V9 K55V9 K55V9 microcircuit chips is connected to the device .

Conclusions 1, 16 of 100LP107, 500LP107, K500LS118, K500LS119, K500TM131 microcircuits are connected to the device case, and terminal 8 of these microcircuits connect to the 5.2 V bus.

Information sources

1. USSR author's certificate No. 1251335 class. N 04 B 3/46, 1985 V.S. Balan, M.S. Grossman. Device for detecting errors.

2. Application for the invention of the USSR No. 4832472/09 (059243) from 05/29/90, MK. 5 H 04 V 3/46. Device for detecting errors. K.G. Kiryanov, V.V. Akulov, A.S. Mednov, AS No. 1709542 - prototype.

3. Integrated circuits. Directory. Ed. V.V. Tarabrina. M .: Energoatomizdat, 1985

4. Analog and digital integrated circuits. Reference manual. Ed. S.V.Yakubovsky. M .: "Radio and communications", 1985

Claims (1)

A device for detecting errors, comprising a comparator in series, a first trigger, a first adder modulo two, a second adder modulo two, the output of which is the installation input of the device, the second trigger with an R input, the first counter, the second input of which is the input of the device’s clock pulses, and the third trigger with a C-input, the R-input of which is connected to the output of the second trigger, the second input of the first counter is connected to the C-input of the fourth trigger, the D-input of which is the information input of the device, the stroke is connected to the second input of the first adder modulo two and the first input of the comparator, the other input of which is connected to the second input of the second adder modulo two and to the output of the third adder modulo two, the first, second and third inputs of which are connected respectively to the first, second and the third outputs of the shift register, the second counter, the first input of which is connected to the output of the comparator and is the error output of the device, characterized in that the output of the fourth trigger is connected to the input of the shift register, the second input of the second Meters withstand connected to the inverted output of the third flip-flop, a direct output of which is connected to the S-input of the second flip-flop, and the output of the second counter is a data output device.

Images