RU2119242C1 - Digital transversal filter - Google Patents

Abstract

FIELD: radio engineering; signal filtering and generating devices. SUBSTANCE: filter has delay line whose outputs are connected to inputs of at least two similar code converters, at least two similar accumulators, at least two single time-step delay cells, at least two similar multipliers, weight coefficient adder, and output-signal adder-shaper. Outputs of each code converter are connected to first input of respective accumulator; output of each accumulator is connected to first input of respective multiplier. Output of weight coefficient shaper is connected to second input of respective multiplier; output of each multiplier is connected to respective input of output-signal adder-shaper. Filter is characterized in provision for eliminating sampling error accumulation and lagging during change-over of weight coefficients as well as in reduced number of bits and multiplying operations using fractional factors required for its functioning. EFFECT: reduced filtering error and hardware cost for implementing the filter. 1 dwg

Description

 The invention relates to radio engineering and can be used in devices for filtering and generating signals.

где
U_вх,U_вых - соответственно входной и выходной процессы ТФ;
n - отсчеты времени;
N - длительность импульсной характеристики ТФ, определяющая длительность переходного процесса;
h(i) - отсчеты импульсной характеристики ТФ.When solving many applied problems, the problem of linear filtering with a limited duration of the transition process arises. The best solution to this problem are transverse filters (TF), which are most easily implemented digitally. Digital TFs provide the calculation of discrete convolution:

Where
U _in , U _out - respectively, the input and output processes of TF;
n are time readings;
N is the duration of the impulse response of the TF, which determines the duration of the transient process;
h (i) - readings of the impulse response of the TF.

 Analogues of the proposed solution are transverse filters that implement the layout (1) using N delay elements, N multipliers and an N-input adder-driver of the output signal [US patent N 4322696 MKI 3 H 03 H 15/02, G 11 C 19/28, 27/02, and USSR copyright certificate N 10413698, MKI 4 H 03 H 15/00]. When solving the problem of increasing the accuracy of filtering, the problem of filtering signals with changing weight coefficients corresponding to a change in signal parameters appears. For this, a weight former is introduced [US Pat. No. 4,326,696]. In addition, there is a problem of implementing an N-input adder. In the USSR author's certificate N 1045384, a pyramidal scheme for implementing an N-input adder consisting of a set of I-input adders, I <N., was proposed.

раз, а при коррелированной - до N раз. Для того, чтобы ошибка квантования при N-кратном накоплении не превышала ошибки квантования при однократном умножении, необходимо увеличение количества r младших двоичных разрядов умножителей и сумматора

в зависимости от степени корреляции ошибок квантования. Так, например, при N ≈ 10² требуемое увеличение младших разрядов умножителей и сумматора

, что может быть существенным ограничением при аппаратурной реализации свертки (1).So, the main disadvantage of the analogues to the proposed solution is the complexity of the hardware implementation, which requires N delay cells, N multipliers, a pyramid-implemented N-input adder, a weight generator with N outputs. In addition, due to quantization errors during N-fold summation, the mean square error of the quantization will increase. For example, with an uncorrelated quantization error, an increase in the mean square error will occur in

times, and when correlated - up to N times. In order for the quantization error during N-fold accumulation not to exceed the quantization error during a single multiplication, it is necessary to increase the number r of the least significant bits of the multipliers and the adder

depending on the degree of correlation of quantization errors. So, for example, at N ≈ 10 ^{2 the} required increase in the least significant bits of the multipliers and the adder

, which can be a significant limitation in the hardware implementation of convolution (1).

Данный ТФ выбран за прототип.The closest to the claimed invention in terms of essential features is TF, in which the filtering result (1) is calculated recursively [USSR copyright certificate N 1345314, MKI 4 H 03 H 15/00]:
U _o (n) = U _o (n-1) + Δ (n), (3)
Where
Δ (n) is the increment of the filtering result at the nth sample,

This TF is selected for the prototype.

Convolution (3) corresponds to convolution (2), if the weighting coefficients h ^* (i) of the impulse response are formed in the form
h ^* (i) = h (i) - h (i-1). (5)
The above TF includes a delay line whose outputs are connected to the inputs of the code converter, the output of the code converter is connected to the first input of the accumulator adder, its output is connected to the input of the delay cell per clock, and the output of this cell is connected to the second input of the accumulator adder. The code converter generates a convolution Δ (n) (4) using the values of the signals U _in (ni) from the output of the delay line, and the accumulator-accumulator implements accumulation (3).

где m - количество экстраполируемых отсчетов.The application of the technical solution of the prototype for computing discrete convolution (3) will require fewer delay cells, as well as multipliers and adders, compared with the number of the same operations when calculating convolution (1). So, for example, consider the use of the technical solution of the prototype for the implementation of the trajectory filter with impulse response
h (i, m) = h ₁ (i) + h ₂ (i, m), (6)
Where

where m is the number of extrapolated samples.

 Using [Kuzmin S.Z. Fundamentals of designing systems for digital processing of radar information. - M.: Radio and Communications, 1986, - p. 150 - 153] it can be shown that the filter with the impulse response (6) is inferior to the optimal trajectory filter that is difficult to implement: no more than 10% for the fluctuation error and 0% for the dynamic error. Therefore, the filter with impulse response (6) is very effective, which determines the particular interest in the implementation of this filter.

Для реализации свертки (4) с импульсной характеристикой (11) с учетом выражений (12) и (13) потребуется две ячейки линии задержки с задержкой на N/2 тактов, реализуемые в преобразователе кодов три умножителя с коэффициентами

и трехвходовый сумматор, а также сумматор-накопитель (3).Taking into account expression (5), the impulse response h (i, m) (6) corresponds to the impulse response
h ^* (i, m) = h $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ (i, m) + h $\genfrac{}{}{0ex}{}{\text{*}}{\text{2}}$ (i, m), (11)
Where

To implement convolution (4) with impulse response (11), taking into account expressions (12) and (13), two delay line cells with a delay of N / 2 clock cycles are required, three multipliers with coefficients implemented in the code converter

and a three-input adder, as well as an accumulator-accumulator (3).

The operation of multiplying L-bit numbers requires L additions of L-bit numbers and L shifts of binary digits. Usually L ≈ 10 ¹ , therefore, the multiplication of L-bit numbers requires an order of magnitude more computational operations than the addition of L-bit numbers. In this regard, the gain R of the prototype in comparison with analogues in the number of computational costs for the implementation of the filter is determined by the gain in the number of multiplications
R ≈ N / 3. (fourteen)
However, as in the analogue, an increase in the number of least significant bits (2) is required due to the accumulation of the quantization error.

In addition, in the TF of the prototype, in contrast to the TF of the analogue, it is not possible to instantly switch the weight coefficients h (i, m). The need for this, for example, may be due to a change in the number of extrapolated samples m (9) during the transition from the smoothing mode to the signal extrapolation mode. Instant switching of weights h $\genfrac{}{}{0ex}{}{\text{*}}{\text{2}}$ (i) (9) in the prototype will lead to a corresponding change in the weight coefficients h (i, m) (6) only after N time samples.

 The task to which the claimed invention is directed is to increase the accuracy of filtration and reduce hardware costs for the implementation of the filter.

 The solution to this problem is achieved by using a digital transverse filter, including a delay line, the outputs of which are connected to the inputs of the first code converter, the output of the first code converter is connected to the first input of the first accumulative adder, its output is connected to the input of the first delay cell per clock, and the output this cell is connected to the second input of the first accumulative adder. Unlike the prototype, an additional weighting factor shaper, an adder-shaper of the output signal, at least two similar multipliers and at least one code converter, similar to the first, and at least one cumulative adder, and at least one delay cell per clock are additionally introduced, while the outputs of the delay line are connected to the corresponding input of each code converter, the output of each code converter is connected to the first input of the corresponding accumulative adder, the output of each adder connected to the input of the corresponding delay cell per cycle and with the first input of the corresponding multiplier, the output of each delay cell per cycle is connected to the second input of the corresponding accumulative adder, the output of the weighting factor generator is connected to the second input of the corresponding multiplier, and the output of each multiplier is connected to the corresponding input of the adder - driver output signal.

 Representation of the filter in the form of at least two parallel-connected filters and the introduction of a multiplier at the output of the accumulative adder reduce the number of fractional weight coefficients that are not a multiple of an integer on the base of two, which avoids the accumulation of quantization errors and, therefore, reduces the required number of bits of multipliers and adders by value (2). Reducing the required number of fractional weighting factors and discharges allows you to get a gain in filtering accuracy and hardware costs.

For example, a TF with an impulse response h (i, m) (6) when using the proposed solution is presented in the form of two parallel-connected filters that implement respectively the impulse responses h ₁ (i, m) and h ₂ (i, m). The scheme of this TF is presented in the drawing. The digital TF contains a delay line 1 with two delay cells of N / 2 cycles each, code converters 2 and 3, accumulator accumulators 4 and 5 with the corresponding delay cells per cycle 6 and 7, weight generator 8, multipliers 9, 10, and the adder output driver 11.

Поэтому на выходе преобразователя 2 формируется сигнал (4)
Δ $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ (n) = U_вх(n)-U_вх(n-N). (16)
Этот сигнал поступает на первый вход сумматора-накопителя 4, а на второй вход этого сумматора поступает задержанный на такт ячейкой 6 выходной сигнал U $\genfrac{}{}{0ex}{}{\text{*}}{\text{вых}}$ (n-1) сумматора 4. Поэтому текущее значение выходного сигнала сумматора 4 реализует накопление (3)

С выхода накопительного сумматора 4 сигнал поступает на первый вход умножителя 9. На втором входе умножителя 9 установлен весовой коэффициент (8)

В итоге на выходе умножителя 9 с учетом выражений (16) и (17) формируется сигнал

Вследствие того, что умножение на дробный коэффициент ¹/N (8) осуществляется лишь после формирования суммы (18), ошибка квантования, обусловленная умножением на этот дробный коэффициент, не накапливается.This TF works as follows. The digital input signal _Rin U (n) is input to delay line 1. On the first and the third output of the delay line receives signals _Rin respectively U (n) and U _Rin (nN) to the first and the second input of the first inverter 2. This converter performs convolution ( 4) incoming signals with impulse response

Therefore, a signal (4) is generated at the output of converter 2
Δ $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ (n) = U _in (n) -U _in (nN). (sixteen)
This signal is fed to the first input of the accumulator-accumulator 4, and the output signal U, delayed by the clock cell 6, is supplied to the second input of the adder 4 $\genfrac{}{}{0ex}{}{\text{*}}{\text{out}}$ (n-1) of the adder 4. Therefore, the current value of the output signal of the adder 4 implements the accumulation (3)

From the output of the accumulative adder 4, the signal is supplied to the first input of the multiplier 9. At the second input of the multiplier 9, a weight coefficient (8) is set

As a result, at the output of the multiplier 9, taking into account expressions (16) and (17), a signal is formed

Due to the fact that multiplication by the fractional coefficient ¹ / N (8) is carried out only after the sum (18) is formed, the quantization error due to multiplication by this fractional coefficient does not accumulate.

Умножение на "-2" реализуется сдвигом разрядной сетки, что осуществляется даже быстрее, чем операция сложение. Весовой коэффициент, устанавливаемый на втором входе умножителя 10, равен

(10). В итоге на выходе второго умножителя 10 формируется результат

Как и в первом случае (18), исключается накопление ошибки квантования вследствие умножения на дробный коэффициент

после накопления суммы в больших круглых скобках (20).The second parallel filter works similarly. Moreover, its impulse response, implemented in the Converter 3, is determined by the expression

Multiplication by "-2" is realized by shifting the bit grid, which is even faster than the addition operation. The weight coefficient installed at the second input of the multiplier 10 is equal to

(ten). As a result, the output of the second multiplier 10 produces the result

As in the first case (18), the accumulation of quantization errors due to multiplication by a fractional coefficient is excluded

after the accumulation of the amount in large parentheses (20).

который равен свертке (1) с импульсной характеристикой (6).And at the output of the adder-shaper 11 of the output signal, the result is a filter

which is equal to convolution (1) with impulse response (6).

 When forming the filtering result (18), (20), (21), the gain in the number of computational costs is determined by the number of fractional weighting coefficients and amounts to R≈N / 2. The gain in the number of required bits (2) compared with the prototype is due to the absence of fractional coefficients in the converter multipliers in the proposed solution (15), (19) compared with the prototype (12), (13). The final gain in the number of hardware costs of the proposed solution in relation to the prototype will be approximately two to three times. With equal hardware costs, the application of the proposed solution will improve the filtering accuracy due to the reduction of quantization error. Another reason for increasing the filtering accuracy is the lack of inertia when switching the weight coefficients (15) and (19), which is unattainable in the prototype.

 The constructive implementation of delay cells per cycle 6 and 7 is determined by the implementation of TF. For example, if a TF is implemented on discrete elements, then cells can be structurally executed on an accumulator-accumulator (as in the prototype), and if a TF is implemented in a special processor, then the cells can be executed separately as RAM elements.

 The proposed implementation of the TF will be no less effective with a larger number of filters connected in parallel. For example, if filtering the trajectory, not two, but three or more polynomial components of the trajectory will be taken into account. In addition, the proposed solution is effective in the implementation of other types of impulse response. For example, when implementing bandpass filters, presented as a superposition of low-pass filters with a rectangular impulse response, etc.

 Thus, the proposed digital transverse filter allows to reduce the filtering error due to the elimination of the accumulation of quantization errors, the lack of inertia when switching the weight coefficients, as well as to reduce the hardware costs of filter implementation due to the reduction in the required number of bits and multiplications by fractional coefficients.

Claims (1)

 A digital transverse filter, including a delay line, the outputs of which are connected to the inputs of the first code converter, the output of the first code converter is connected to the first input of the first accumulative adder, characterized in that the weight former, the adder-former of the output signal, at least two similar multipliers, are introduced at least one code converter, similar to the first code converter, the inputs of which are connected to the corresponding outputs of the delay line, and at least one kopitelnogo adder, the output of each inverter connected to the input codes corresponding cumulative adder, the outputs of which are connected to first inputs of respective multipliers whose second inputs are connected to the output of the weighting coefficients, and outputs - to the corresponding input of the adder-driver output signal.