RU2110890C1 - Device for detecting signals with programmed operating frequency variation - Google Patents

Abstract

FIELD: radio engineering (radio communications). SUBSTANCE: device has reference-frequency unit and N signal-processing channels connected through storage units to signal maximum selector unit; newly introduced in device are pulse distributor and controlled divider. Device functions to concurrently detect signal with programmed operating frequency variation and to determine its time position. Device uses locking to universal time labels thereby narrowing range of time uncertainty of probable signal position. Signal retrieval is effected by step-by-step scanning of uncertainty region using serial-and-parallel method. During signal processing, functional is computed as sum of readings modified in two categories basing on use of sign function and excess of average read off on viewing interval. Decision on signal detection is taken by results of comparison with threshold value. Position of maximal sum of values exceeding average is assumed as synchronous position. EFFECT: improved noise immunity and enlarged functional capabilities. 3 cl, 18 dwg

Description

 The invention relates to radio engineering, and in particular to radio communication technology, and can be used as part of a connected radio receiving devices for receiving and demodulating signals with software tuning of the operating frequency (MHF).

 Known signal detection devices: A.S. USSR N 566218; A.S. USSR N 717674; A.S. USSR N 800925; A.S. USSR N 800927; A.S. USSR N 809017; A.S. USSR N 907487; A.S. USSR N 987543. In the known devices, the detection problem is solved by calculating the likelihood ratio and comparing it with a certain threshold level. To ensure high noise immunity, they use nonparametric signal processing, namely ranking statistics are used, however, these devices cannot be directly used in short-wavelength connected radio receivers operating in the frequency hopping signal reception mode, which is due to insufficient detector capabilities: firstly, they are not calculated to detect signals having the structure of a time-frequency matrix, and secondly, the synchronization problem is not solved in them.

 The closest technical solution to the claimed is a quasi-optimal incoherent signal detector with frequency hopping, which is selected as a prototype [1].

 The well-known quasi-optimal incoherent signal detector with frequency hopping contains an adder, a threshold block, a switch, a drive block, a block for selecting the maximum signal, N parallel channels (N parallel processing paths), each of which includes a series-connected multiplier (frequency converters), a bandpass filter, and an envelope detector and a quadrator, the signal inputs of all channels are combined and are the signal input of the device, the other inputs of all the multipliers are connected to the voltages of the reference frequencies, the outputs are qua tors all N channels are connected through a switch to the series-connected storage unit and the block selecting signal maximum, first and second outputs of which are connected to respective inputs of the adder, the adder output being coupled to a threshold input unit, whose output is the output of the detector.

 A disadvantage of the known device is the lack of noise immunity under the influence of a wide range of interference, since statistics based on the use of the true values of the received voltage, rather than robust, are used to make a decision on signal detection. In addition, the prototype, like all of the above analogues, does not solve the synchronization problem. The known detection device assumes that the number of channels (paths) of signal processing with frequency hopping is equal to the total number of frequencies used for operation (see AS USSR N 1569998). As a result, an increase in the number of operating frequencies used, which is necessary to increase the noise immunity, will complicate the device.

 The aim of the invention is to develop a detection device that provides higher noise immunity and having great functionality.

This goal is achieved by the fact that in the known device for detecting signals with frequency hopping, containing a block of reference frequencies having N frequency outputs, a drive unit, a block for selecting the maximum signal and N parallel processing paths (where N ≥ 2), each of which contains a series-connected converter frequency bandpass filter and envelope detector, and the signal inputs of all frequency converters are combined and are the signal input of the device, the inputs of the heterodyne voltage of the frequency converters are connected They are connected to the corresponding frequency outputs of the reference frequency block, the outputs of each of the N processing paths are connected to the corresponding information inputs of the drive block, the information outputs of which are connected to the inputs of the signal maximum selection block, an additional pulse distributor and a controlled divider with inputs “Synchronization” and “Installation” are introduced , the last of which is connected to the Start inputs of the reference frequency block and the pulse distributor. The outputs "Clock frequency" and "Reference clock frequency" of the controlled divider are connected to the same inputs of the pulse distributor. The input T _and and the interrupt input τ _e of the reference frequency block are paired with the inputs T _and and τ _e of the signal maximum selection block and are connected respectively to the pulse outputs with a duration T _and and τ _{e of} the pulse distributor. The “Start” input of each of the processing paths is combined with the corresponding “Record” input of the drive unit and connected to the corresponding “Start” output is pulse distributors. N outputs "Resolution" of the pulse distributor are connected to the corresponding N inputs "Resolution" of the drive unit. The output of the pulse distributor "Beginning of the step" is connected to the corresponding interruption input "Beginning of the step" of the signal maximum selection block, the outputs are "Synchronization is", "End of the step" and M outputs "Hypothesis number" which are connected to the corresponding inputs of the controlled divider (where M - 2 , 3, ...,). The N data readiness inputs of the signal maximum selection block are connected to the corresponding outputs of the drive block. The input "Address tracking pulse" of the drive unit is connected to the output of the unit of the maximum signal selection of the same name.

The pulse distributor contains a counter divider into R, N two-input AND elements, N inverters, N differentiating circuits, two-input OR element, N-input OR element and delay element. The inputs of N inverters and N differentiating circuits are paired and connected respectively with 1, ..., N outputs of the counter-divider by R. The output of the first differentiating circuit is connected to the input of the delay element, the output of which is connected to the first input of the N-input element OR, outputs the remaining differentiating chains are connected to the corresponding (N-1) inputs of the N-input OR element. The (N + 1) -th output of the counter-divider on R is connected to the first input of the two-input OR element, the output of which is connected to the input "Zeroing" of the counter-divider on R. The outputs of N inverters are connected respectively to the first inputs of N elements AND, the second inputs of which are interconnected and are the input "Clock frequency" of the pulse distributor. The outputs of all elements And are the first group of N outputs "Start" pulse distributor. The "counting" input of the counter-divider on R is the input "Reference clock frequency" of the pulse distributor. The outputs of N inverters form a second group of N outputs "Resolution" of the pulse distributor. The second input of the two-input OR element is the "Start" input of the pulse distributor. The output of the first differentiating chain and the output of the N-input OR element are respectively pulse outputs of duration T _and and τ _{e of} the pulse distributor.

 The controlled divider contains a reference oscillator, first, second and third frequency dividers, a divider counter, a first decoder, a second decoder, a reverse counter, a step counter, a timer, five two-input elements AND, two two-input elements OR, two inverters, two differentiating circuits, a delay element , TB trigger and RS trigger. The output of the reference regenerator is connected to the input of the first frequency divider, the counting input of the counter-divider is combined with the first input of the first And element and connected to the output of the first frequency divider. The output of the counter-divider is connected to the counting input of the reverse counter, the outputs of which 1, ..., G are connected respectively to the inputs of the first decoder. The second input of the first element And is combined with the input of the first inverter and connected to the output of the first decoder. The enable input of the counter-divider is connected to the output of the first inverter. The inputs of the second and third frequency dividers are combined and connected to the output of the first element I. The output of the upper frequency of the third divider is connected to the first input of the second element And, the second input of which is connected to the output of the third element And, the first input of which receives voltage from the output of the TB trigger. The counting input of the TB trigger is connected to the output of the step counter, the control input of which is combined with the first input of the first OR element and connected to the output of the first differentiating chain. The input of the first differentiating chain is combined with the first input of the fifth And element and is connected to the output of the RS trigger. The counting input of the counter with the output is combined with the second input of the first OR element and connected to the output of the fifth element I. The output of the first OR element is connected to the installation input of the timer, the counting input of which is combined with the first input of the fourth AND element and connected to the lower frequency output of the third frequency divider. The timer outputs are connected to the inputs of the second decoder. The second input of the fourth AND element is combined with the input of the second inverter, the timer enable input, the input of the second differentiator circuit and connected to the output of the second decoder, the outputs of the second and fourth AND elements are connected respectively to the inputs of the second OR element. The output of the second differentiating circuit is connected to the input of the delay element. The “Resolution” input of the reverse counter is combined with the R-input of the RS-trigger and is the “Synchronization is” input of the controlled divider. The second input of the fifth AND element is the “End of step” input of the controlled divider. The S-input of the RS-trigger is the "Synchronization" input of the controlled divider. The resetting input of the reversing counter is combined with the setting input of the TB-trigger, resetting the input of the step counter and is the “Setting” input of the controlled divider. The inputs 1, ..., M of the reverse counter are the inputs of the corresponding bits "Hypothesis number" of the controlled divider. The output of the delay element is the output of the Begin Beginning signal of the controlled divider. The output of the second frequency divider is the "Clock frequency" output of the controlled divider. The output of the second OR element is the reference clock frequency output.

 The proposed technical solution is based on the joint implementation of the search, detection and estimation of the time parameter of the signal with frequency hopping.

 The essence of the proposal to reduce the number of signal processing paths with frequency hopping compared to the prototype is based on the implementation of the timing of the operation of the block of reference frequencies to the signals of the single time service. This allows you to significantly limit the area of temporal uncertainty of the possible position of the signal to be detected (for example, with manual binding this area can reach one to two seconds). The blocks introduced into the inventive device allow serial-parallel signal search in the uncertainty zone, as a result, the detection problem is solved using the same number of processing paths that are used for demodulation.

.The essence of the proposal to improve the noise immunity of the claimed device compared to the prototype is based on the use of nonparametric signal processing in it. So, to make a decision about the presence or absence of a signal in one or another element of the zone of time uncertainty, sign-rank statistics are used. When analyzing one element of the time uncertainty zone, the estimation time is chosen so that the random process observed in each frequency processing path can be considered stationary. The separation between the frequencies is taken so that the interference in different paths can be considered independent. Then, after taking sufficiently frequent samples of the detected voltage in each processing path, summing them and dividing by the number of taken samples, one can determine for each of the paths its average value of the processed voltage. For example, let a sample X1 be formed for the first frequency path from the voltage detected during time T, consisting of m samples and having the form x ₁₁ , x ₁₂ , ..., x _1m , where the first index is the sample number and the second is the sample number in her. Then, the average voltage value of the taken samples in the first sample is μ ₁ = (1 / m) • (x ₁₁ + ... + x _1m ). Further, for each processing path, a modified sample is introduced in which the true values of the taken samples are replaced by the truncated ones. Truncated sample values are obtained using the sign function

.

Under conditions of only interference, the probability of exceeding by any sample the average value in its processing path for interference with an arbitrary symmetric probability density function will be 1/2. After summing the values of the samples of the modified samples for all processing paths during the analysis of one uncertainty section, we obtain the sum of the first samples S ₁ , the sum of the second samples S _2, and so on.

.

.

Where
K is the number of samples formed during the analysis of one uncertainty plot.

 In the absence of a signal, the values of each of the sums will be approximately the same, since the interference operating in different paths is statistically independent. When a useful signal appears at the input of the device, the readings at certain moments at different frequencies will already be dependent. Those sums that correspond in time to the simultaneous presence of the signal and interference will be much larger than those where the signal is absent. By choosing a threshold level in a certain way, it is possible to provide a stable value of the probability of false alarm for a wider class of interference than Gaussian.

 The essence of the proposal for assessing the true temporal position of the detected signal with frequency hopping is as follows. After the signal is detected, the decision on its most probable position in the analyzed time uncertainty section is made using the true values of the taken samples in all processing paths stored in memory. To do this, in those modified amounts in which the threshold level was exceeded, the truncated values of the samples are replaced by the excess of the true value over the average, they are summed up and the values of the sums are compared with each other. The temporary position for which the value of the sum of the samples is the largest, and is the most accurate temporary position of the signal with frequency hopping.

 With such a combination of essential features, the proposed device, along with solving the problem of detecting signals with frequency hopping, additionally solves the synchronization problem, determining the position of the signal with frequency hopping on the time axis with the required accuracy and having less than the processing paths in the prototype .

 Figure 1 shows a device for detecting signals with frequency hopping; in FIG. 2 - pulse distributor (RI) 5; in FIG. 3 - counter divisor by "R" 5.1; in FIG. 4 - controlled divider 6; in FIG. 5 - step counter 6.20; in FIG. 6 and 7 are timing diagrams of signals explaining the principle of operation of the inventive device; in FIG. 8 - block reference frequencies 1; in FIG. 9 is a block diagram of a microcontroller program that implements the function of a pseudo-random codeword sensor 1.4; in FIG. 10 - block pulse shaping recording 1.3; in FIG. 11 - drive unit 3; in FIG. 12 is a diagram of memory blocks 3.1 (3.2, ..., 3.N); in FIG. 13 - bidirectional bus amplifier 3.1.2 - 3.1.5; in FIG. 14 - random access memory (RAM) 3.1.1; in FIG. 15 - block selection of the maximum signal 4; in FIG. 16-18 is a block diagram of the microcontroller program in the block for selecting the maximum signal 4.

The device for detecting signals with frequency hopping, shown in figure 1, contains a block of reference frequencies (BOC) 1, a block of drives 3, a block for selecting the maximum signal (BVMS) 4, a pulse distributor (RI) 5, a controlled divider (UD) 6 and N paths processing from 2 ₁ to 2 _N , in each of the processing paths 2 ₁ , ..., 2 _N there is a frequency converter (IF) 2.1, a bandpass filter (PF) 2.2, an envelope detector (DO) 2.3. BOSCH 1 has inputs "Start", "Input time", "T _and ", "Interrupt τ _e " and N frequency outputs. The “Time input” input is used to enter information about the current time, the “Start” input is the time start input, the inputs T _and and interrupts τ _{e are} connected respectively to the outputs T _and and τ _e RI 5. Frequency outputs VOCH 1 from 1st to The nth are connected to the heterodyne inputs of the inverter 2.1, respectively, from the 1st to the Nth of all processing paths. The first inputs of the inverter 2.1 of all processing paths are interconnected and are the signal input of the device. In each processing path, the output of the inverter 2.1 is connected to the input of PF 2.2, the output of PF 2.2 is connected to the first input of DO 2.3. The outputs UP to 2.3 of all N processing paths using information buses are connected to the corresponding information inputs of the drive unit 3. Each of the N inputs of the “Record” of drive unit 3 is combined with the “Start” input up to 2.3 of the corresponding processing path and is connected to the corresponding output “Start” of the RI 5. The "Resolution" inputs of the drive unit 3 are connected to the corresponding "Permission" RI outputs 5. The "Address Tracking Impulse" (ISA) input of the drive unit 3 is connected to the corresponding VVMS output 4. The output address-information bus (ШАИ ) drive unit 3 is connected to the VVMS SHAI 4. N data readiness outputs 3 of the drive unit 3 are connected respectively to the N data readiness inputs of the VVMS 4. interrupt inputs T _and and τ _{e of the} BVMS 4 are connected to the corresponding outputs of RI 5, the interrupt input " The beginning of the step "is connected to the corresponding output of the UD 6. The outputs of the BVMS 4" End of the step "," There is synchronization ", as well as the outputs from the 1st to the Mth digits" Hypothesis number "are connected to the inputs of the same name UD 6, which also has Synchronization input and Installation input. The input "Installation" UD 6 is connected to the inputs "Start" BOCH 1 and RI 5. The outputs UD 6 "Clock frequency" and "Reference clock frequency" are connected to the corresponding inputs of RI 5.

 Figure 2 shows a diagram of RI 5, intended for the formation of control signals in the operating time of the blocks included in the device for detecting signals with frequency hopping.

RI 5 contains a counter divider by R 5.1, a two-input logic element OR 5.2, N two-input elements AND 5.3 ₁ - 5.3 _N , N inverters 5.4 ₁ - 5.4 _N differentiating circuits 5.5 ₁ - 5.5 _N , a delay element 5.6 and an N-input element OR 5.7. The “Start” input RI 5 is the second input of the OR element 5.2, the input “Reference clock frequency” is the counting input of the counter-divider 5.1 by R, the input “Clock frequency” is connected to the combined second inputs of N elements AND 5.3. The outputs of RI T _and and τ _e are the outputs of the first differential. chain 5.5 ₁ and element OR 5.7, respectively. N outputs RI 5 "Resolution" are the outputs of N inverters 5.4 ₁ - 5.4 _N. N outputs "Start" are the outputs of N elements AND 5.3 ₁ - 5.3 _N. Inputs diff. chains 5.5 ₁ - 5.5 _N are paired and connected to the N outputs of the counter-divider on R 5.1, the (N + 1) -th output of which is connected to the first input of the OR gate 5.2. The input of zeroing the counter-divider on R 5.1 is connected to the output of the OR element 5.2. Output Dif. chain 5.5 _{1 is} connected to the first input of the OR element 5.7 through the delay element 5.6, the outputs of the remaining differential. circuits 5.5 ₂ - 5.5 _{N are} connected directly to the corresponding inputs of the element OR 5.7. The outputs of the inverters 5.4 ₁ - 5.4 _{N are} connected to the first inputs of N elements AND 5.3 ₁ - 5.3 _N.

Schemes of differentiating circuits 5.5 ₁ - 5.5 _{N are} known (Titz U. and Shenk K. Semiconductor circuitry.-M.: Mir. 1982, p. 146, Fig. 11.16.)
Delay schemes are known (Frolkina V.T. Pulse devices. M.: Mashinostroenie, 1966, p. 42). Delay element 5.6 may be performed on an RC circuit.

 The counter divider on R 5.1 is designed to generate reference signals in RI 5.

 Schemes of counters-dividers are known and described (Shilo V.L. Popular digital microcircuits. Handbook. M.: Radio and Communications, 1987, pp. 239-241, Fig. 2.40). In particular, as shown in FIG. 3 for R-30, such a scheme can be implemented on the chip 564 IE 9.

The counter circuit of the divider on R 5.1 contains two counters (5.1 ₁ and 5.1 ₂ ), the counter input of the counter 5.1 ₁ is the counter input of the counter-divider on R 5.1. The zeroing inputs of both counters (R inputs) are combined and are the “Zeroing” input of the divisor counter on R 5.1. The output of the 5th digit of the counter 5.1 _{1 is} connected to the counter input of the counter 5.1 ₂ , (N + 1), the outputs of which are the outputs of the counter-divider to R 5.1.

 In FIG. 4 shows a designation of the UD 6 intended for performing time offsets (within the uncertainty region) of all control signals in the detection device with frequency hopping signals.

 UD 6 contains a reference generator (OG) 6.1, three frequency dividers 6.2-6.4, five two-input logic elements AND (6.5-6.9), a counter-divider 6.10, a reverse counter 6.11, a decoder 6.12, a TV trigger 6.13, two inverters 6.14 and 6.15 , timer 6.16 with decoder 6.17, two differentiating chains (differential chains) 6.18 and 6.19, step counter 6.20, two logical elements OR 6.21 and 6.22, delay element 6.23 and RS-trigger 6.24.

 The input UD 6 "Installation" is connected to the zeroing inputs of the reverse counter 6.11, step counter 6.20 and the installation input of the TV trigger 6.13. Inputs UD 6 1st, 2nd, ..., Mth category "Hypothesis number" are connected respectively to the inputs "1st category", "2nd category", ..., "Mth category "reverse counter 6.11. The input "End of step" UD 6 is connected to the second input of the fifth element And 6.9. The input UD 6 "Synchronization is" is connected to the R-input of the RS-trigger 6.24 and the input "Resolution" of the reverse counter 6.11. The input UD 6 "Synchronization" is connected to the S-input of the RS-trigger 6.24. The output of UD 6 "Clock frequency" is the output of the second frequency divider 6.3. The output of UD 6 "Reference clock frequency" is the output of the second clock element OR 6.22, and the output "Beginning of the step" is the output of the delay element 6.23.

 The output of the reference generator 6.1 through the first frequency divider 6.2 is connected to the first input of the first element And 6.5 and the counting input of the counter-divider 6.10, the output of which is connected to the counting input of the reverse counter 6.11. G outputs of the reverse counter 6.11 are connected to the inputs of the first decoder 6.11, the output of which is connected to the second input of the first AND 6.5 element directly and to the "Resolution" input of the counter-divider 6.10 through the first inverter 6.14. The output of the first element And 6.5 is connected to the inputs of the second and third frequency divider 6.3 and 6.4. The “Upper frequency” output of the third frequency divider 6.4 is connected to the first input of the second And 6.6 element, and the “Lower part” output is connected to the first input of the fourth And 6.7 element and the counting input of timer 6.16. The outputs of the second and third elements And 6.6 and 6.7 through the second element OR 6.22 connected to the output of the UD 6 "Reference clock frequency". The output of the RS-trigger 6.24 is connected directly to the first input of the fifth AND 6.9 element, and to the control input of the step counter 6.20 and the first input of the first OR 6.21 element through the first differential circuit 6.19. The output of the fifth element And 6.9 is connected to the counting input of the counter of steps 6.20 and the second input of the first element OR 6.21, the output of which is connected to the installation input of the timer 6.16. The output of the step counter 6.20 is connected to the counting input of the trigger 6.13, the output of which is connected to the first input of the third element And 6.8. The outputs of timer 6.16 are connected to the second decoder 6.17, the output of which through the second inverter 6.15 is connected to the second input of the third element And 6.8 and directly connected to the input "Resolution" of timer 6.16, the second input of the fourth element And 6.7 and the input of the second differential. circuit 6.18, the output of which is connected to the input of the delay element 6.23.

 Figure 5 shows a diagram of the counter of steps 6.20, designed to count the steps in the area of uncertainty in the process of searching for a signal with frequency hopping.

 The step counter 6.20 contains a counter up to 2 6.20.1, an RS-trigger 6.20.2, a delay element 6.20.3, a counter up to L / 2 6.20.4, a two-input element AND 6.20.5, four logic elements OR 6.20.6 - 6.20.9. The input of zeroing of the counter of steps 6.20 is the first input of the OR element 6.20.7. The input through which signals from the And 6.9 element can be received in UD 6 is the counter output of the counter to L / 2 6.20.4. The input S of the RS-trigger 6.20.2 is the control input of the trigger of steps 6.20 and is connected (in UD 6) to the differential. chains 6.19. The output of the step counter 6.20 is the output of the OR element 6.20.6, also connected to the 2nd input of the OR element 6.20.7. The first input of the OR element 6.20.6 is connected to the L-th output of the counter up to 2 6.20.1, and the second input is connected to the output of the AND 6.20.5 element. The zeroing inputs of the counters 6.20.1 and 6.20.4 are combined and connected to the 1st input of the OR element 6.20.8 and the output of the OR element 6.20.7. The "Resolution" counter input to L / 2 6.20.4 is connected to the output of the OR 6.20.9 element, the first input of which is combined with the second input And 6.20.5 and connected to the first output of the RS-trigger 6.20.2. The second input of the OR element 6.20.9 is combined with the input "Resolution" of the counter up to 2 6.2-0.1 and connected to the 2nd output of the RS-trigger 6.20.2. The output L / 2 of the counter to L / 2 6.20.4 is connected to the counter input of the counter up to 2 6.20.1, the first input of the AND 6.20.5 element and the input of the delay element 6.20.3, the output of which is connected to the second input of the OR element 6.20. eight. The output of the OR 6.20.8 element is connected to the R-input of the RS-trigger 6.20.2.

 Reference generators are known (Pavlov KM Radio receivers of HF communication: Textbook for technical schools of communication. M: Communication, 1980, p. 83, Fig. 2.30).

 Frequency dividers 6.2, 6.3, 6.4 and 6.10 can be performed on the counting dividers described in the book Shilo V. L. Popular digital circuits. Directory. -M. : Radio and communications, 1987, p. 240-242. In particular, they can be implemented, for example, on 564 IE 10 chips. A timer 6.16 can be implemented on the same circuits.

 The reversible counter 6.11 is described in the same book on p. 242-245 and can be implemented on the 564 IE 11 chip.

 Decoders 6.12 and 6.17 are described in the book Shilo V.L. Popular digital circuits. Directory. -M. : Radio and communications, 1987, p. 261-264 and can be implemented on the chip 564 ID 1. Triggers TV and RS are considered in the same place on page. 62-66.

In FIG. Figure 8 shows the circuit of BOC 1, which is designed to generate heterodyne voltages for the inverter 2.1 processing paths 2 ₁ .

BOSCH 1 contains N frequency synthesizers (1.1-1 to 1.1-N), N buffer resistors (1.2-1 to 1.2-N), a recording pulse shaping unit (BFIZ) 1.3, and a pseudo-random codeword (DPC) sensor 1.4, and reference generator (OG) 1.5. The “Start” input of DPKS 1.4 is connected to the “Installation” input of the device as a whole. The inputs of the I / O circuits of DPKS 1.4, namely, “Request”, inputs 12-15 of “Register-1” and inputs 12 and 14 of “Register-2” form the circuit “Input time” in BOC 1. Address-information outputs of DPKS 1.4 form address information bus (SHAI). Inputs DPKS 1.4 - Pr. 11 and input 15 "Register-2" are respectively the input "Interrupt τ _e " and the input "T _and " BOC 1 and are connected to the corresponding outputs of RI 5. N frequency outputs BOC 1 are outputs of the corresponding N frequency synthesizers 1.1-1, 1.1- 2, ..., 1.1-N. The control input of each of the N synthesizers 1.1 is connected to the input of the corresponding buffer register 1.2, the inputs of which are interconnected and connected to the address-information bus DPKS 1.4. The reference inputs of all synthesizers are connected to the exhaust 1.5 output. The "Record" inputs of each of the buffer registers 1.2-1, ..., 1.2-N are connected respectively to the outputs 1-1, ..., 1-N of the recording pulse shaping unit 1.3, the information inputs of which are connected to the address-information bus of the DPKS 1.4. The ISA input and the “Record” input of the recording pulse shaping unit (BFIZ) 1.3 are connected to the outputs of the same type DPKS 1.4, and the DPKS 1.4 input “Resolution” is connected to the same output of the recording pulse forming unit 1.3.

 The schemes and principles of operation of frequency synthesizers are known and described, for example, in the book "Digital Radio Receiving Systems: Reference Book / M.I. Zhodzishsky et al. / Edited by M.I. Zhodzishsky.-M.: Radio and Communications, 1990, p. 72, Fig. 37. In the particular case, frequency synthesizers 1.1-1, ..., 1.1-N can be implemented, for example, on synthesizers manufactured at the Russian Institute of Powerful Radio Engineering, the decimal circuit number is EP.2.329.008.EZ.

 Buffer registers 1.2-1, ..., 1.2-N are information storage registers, which are considered in many sources. For example, in the reference book "The use of integrated circuits in electronic computing". M.: Radio and communications, 1987. Similar registers are described on p. 109, fig. 5.44. In particular, buffer registers 1.2, ..., 1.2-N can be implemented on D-triggers. Description of D-flip-flops is given in the book Shilo V.L. Popular digital circuits. Directory. M .: Radio and communications, 1987, p. 72-73. In particular, D-flip-flops made on 133TM chips can be used.

 Block recording pulse formation (BFIZ) 1.3 is designed to control the process of writing code words to the buffer registers 1.2-1, ..., 1.2-N.

 In FIG. 10 shows the BFIZ scheme 1.3, which contains a decoder 1.3.1 for decrypting the address, a two-input element AND 1.3.2, a delay element 1.3.3 and N D-triggers 1.3.4 from the 1st to the Nth. Three information inputs of the decoder 12.3.1 are connected to three corresponding bits of the SHAI DPKS 1.4, the fourth information input is the input of the ISA. Six digits of the ShAI (at N-6) are connected to the D-inputs of each of the D-triggers 1.3.4. The “Record” input of the recording pulse shaping unit 1.3 is connected to the first input of the AND 1.3.2 element and the input of the delay element 1.3.3, the output of which is the “Resolution” output. The outputs of all D-flip-flops 1.3.4 form the outputs 1-1,1-2, ..., 1-N of the recording pulse generation block 1.3. The output of the decoder 1.3.1 is connected to the second input of the AND 1.3.2 element, the output of which is connected to the counting inputs of all D-triggers 1.3.4 combined together. Inputs S and R of all D-flip-flops are combined and logic level “1” is applied to them.

 The decoder 1.3.1 can be implemented on the chip 134ID6, which is described in the book Shilov V.L. Popular digital circuits. Directory. M .: Radio and communications, 1987, p. 261-263. D-trigger circuits are considered there on p. 72-73. In particular, D-flip-flops made on 1333TM2 microcircuits can be used.

 DPKS 1.4 is designed to generate code words for controlling the frequencies of synthesizers 1-1,1-2, ..., 1-N, as well as control signals for the operation of BFIZ 1.3.

 DPKS 1.4 can be implemented on a computer, for example, on the MK-31 microcontroller, which is built on the basis of the K586BE1 single-chip microcomputer at the Russian Institute of Powerful Radio Engineering.

 The block diagram of the DPSC program is shown in FIG. nine.

 Frequency converters 2.1 in each processing path are made according to a double balance circuit and are described in the book of N. Gonorovsky. Radio engineering circuits and signals, part II. M .: Sov. Radio, 1967, p. 149, fig. 4.19.

 Band-pass filters 2.2. - Electromechanical filters of the type FEM 5 - 041 - 301.63 - 0.26C - 3B.

 Envelope detectors (DO) 2.3 - synchronous envelope detectors with digital output, made according to the USSR copyright certificate N 1.706.005.

 Drive block 3 is designed to store samples taken on the observation interval.

 In FIG. 11 shows a diagram of a drive unit 3, which contains N identical memory units 3.1, ..., 3.N. N information inputs of the drive unit 3 are information inputs of N memory blocks 3.1, ..., 3, N. N inputs "Record" and N inputs "Resolution" are the corresponding inputs of each of the N memory blocks. The input "Address Tracking Impulse" (ISA) of drive unit 3 is common to all memory units 3.1, ..., 3.N. The information outputs of all memory blocks 3.1, ..., 3.N are connected to a common address-information bus (ШАИ), which is the output of the drive unit 3. In addition, each of the N memory blocks 3.1, ..., 3.N has an output "Data Availability". These outputs form the corresponding group of N outputs of the drive unit 3.

The memory unit 3.1 is designed to store samples of one processing path 2 _i .

 In FIG. 12 is a diagram of a memory block 3.1, which contains RAM 3.1.1, four bi-directional bus amplifiers (LSS) 3.1.2-3.1.5, three inverters 3.1.7, 3.1.8 and 3.1.10, a counter up to "30" 3.1. 9, two decoders 3.1.6 and 3.1.11, storage register 3.1.12, delay element 3.1.13, differentiating circuit 3.1.14 and RS-trigger 3.1.15. The information input of the memory unit 3.1 is the information input of DNSU 3.1.2. The entry input of the memory unit 3.1 is connected to the input of the inverter 3.1.7 and the counter counting input to "30" 3.1.9, the input "Resolution" is connected to the input of the inverter 3.1.8 and the input of the differentiating circuit 3.1.14, the input ISA is the first input of the decoder 3.1 .eleven. The address-information bus for the exchange of information between the drive unit 3 and the signal maximum selection unit 4 is connected to the output of the ДНШУ 3.1.3, the input of the storage register 3.1.12 and the second input of the decoder 3.1.11. The output "Data Availability" is the output of the delay element 3.1.13 and is connected, in addition, to the control input of the DNSSh 3.1.3. The output of the DNSH 3.1.2 is connected to the data input of RAM 3.1.1, the data output of which is connected to the input of the SNL 3.1.3. The output of the inverter 3.1.7 is connected to the write / read input of RAM 3.1.1 and the control inputs of the DNSSh 3.1.2 and 3.1.4. The address inputs of RAM 3.1.1 are connected to the outputs of the DNSH 3.1.4 and 3.1.5. The counter outputs up to "30" 3.1.9 are connected to the inputs of the DNSSh 3.1.4 and the decoder 3.1.6, the output of which is connected through the inverter 3.1.10 to the counter zeroing output to "30" 3.1.9 and to the R-input of the RS flip-flop 3.1 .15 directly. The output of the RS-trigger 3.1.15 is connected to the counter resolution input of the counter to "30" 3.1.9, the S-input of the RS-trigger 3.1.15 is connected to the output of the differentiating circuit 3.1.14. The control input of the DNSSh 3.1.5 is connected to the output of the inverter 3.1.8, and the information inputs of the DNSSh 3.1.5 are connected to the outputs of the storage register 3.1.12, the recording input of which is connected to the output of the decoder 3.1.11 and the input of the delay element 3.21.13.

 In FIG. 13 shows a diagram of the LSS, which is used to connect (disconnect) the data bus or RAM addresses 3.1.1.

 Bidirectional bus amplifiers are described in the book Shilo V.L. Popular digital circuits. Directory. M.: Radio and Communications, 1987, p. 34. In particular, DNSHU 3.1.2-3.1.5 can be performed on K 155 AP 6 microcircuits.

 RAM 3.1.1 is intended for storing and storing samples of the voltage envelope taken in the processing path at the observation interval.

 Schemes for constructing RAM are known and described, see, for example, in the book Large Integrated Circuits of Storage Devices. Handbook / A.Yu. Gordonov et al., Ed. A.Yu. Gordonova and Yu.N. Dyakonova. M .: Radio and communications, 1990, p. 80-85. In particular, as shown in FIG. 6.3, RAM 3.1.1 can be implemented on 564RU2 microcircuits.

 The register of storage of the reference address 3.1.12 is made according to the scheme shown in Fig. 5.44 s 109 in the book The use of integrated circuits in electronic computing, ed. B.N. Fayzulaeva and B.V. Gibberish. M .: Radio and communications, 1987.

 The decoder 3.1.6 is made according to the scheme described in the book Shilo V.L. Popular digital circuits. M .: Radio and Communication, 1987, p. 137, fig. 1.98. In the same book on p. 74 images 1.53 described RS-trigger.

 The differentiation scheme 3.1.14 is described on p. 146, fig. 11.16 in the book by Titz W. and Schenk K. Semiconductor circuitry. M .: Mir, 1982.

 The delay circuit is built on an RS circuit.

 In FIG. Figure 15 shows the BVMS 4, intended for nonparametric processing of samples accumulated over the observation interval and generation of control signals for the search process, as well as for deciding on the detection of a signal from the frequency hopper and issuing control to eliminate the mismatch.

 Block selection of the maximum signal 4 includes a microcontroller MK-31 4.1. and N-input element OR 4.2, the output of which is connected to the input "Answer" MK-31 4.1. The inputs of the OR element 4.2 are the inputs "Data Readiness" from 1 to N of the block for selecting the maximum signal 4. Address-information bus BVMS 4 is the address-information bus MK-31. 4.1.

 In BVMS 4, the MK-31 4.1 microcontroller is designed to process information and control peripheral equipment in real time. As mentioned above, it is based on a single-chip microcomputer K586BE1 at the Russian Institute of Powerful Radio Engineering.

 The block diagram of the work program MK-31 4.1 is presented in FIG. 16-18.

 The inventive device operates as follows.

To carry out synchronization and subsequent transmission of information, a signal in the form of a time-frequency matrix with a program-tunable operating frequency was used. With this signal, over a period of time equal to the duration of each information packet T _and , N elementary pulses are emitted following each other (see Fig. 6a). The duration of each elementary pulse τ _e is N times less than the duration of the information packet T _and , τ _e = T _ω / N. Each elementary pulse is emitted at a new carrier frequency. The nominal frequencies of the carrier frequencies during signal generation are assigned using a sensor that generates code words T _and N before the start of the time interval, each of which is associated with a carrier frequency value. Information signs are laid down in the radiation order of n frequencies assigned for this information package. For example, the sequential radiation of frequencies f ₁ , f ₂ , ..., f _i , ..., f _N corresponds to the transmission of an information unit, when the information zero is emitted, the sequence changes: f _i , f _{i + 1} , ..., f _N , f ₁ , f ₂ , ..., f _i-1 .

 At the reception, N heterodyning voltages are supplied to the N mixers. For proper signal demodulation, a strict correspondence of the frequencies of the heterodyning signals with the pulse frequencies of the received signal is necessary.

 The frequencies of the heterodyning voltages are set in accordance with the codewords generated by the pseudo-random codeword sensor, similar to the sensor on the transmission side.

 Sensors are synchronized using a single time set before the exchange of information. For more accurate synchronization, a sequence of signals is transmitted for some time from the side of the transmitting station, for example, a sequence corresponding to information zeros or information units, or another known in advance on the receiving side. This signal searches for a synchronous position in the receiving device.

 On the transmission, a change in the carrier frequencies of the synchronization signal, carried out in accordance with the code words from the sensor, is performed at time instants that are consistent with the time stamps of a single time and with information packets forming a clock signal. The frequencies for transmitting any information package are selected by the sensor with equal probability for each frequency, and their appearance does not depend on the type of information sequence. Therefore, the signal used in the device has spectral characteristics that are independent of the type of information. This allows, without compromising the secrecy of the system, to create preferable conditions for the synchronization mode, namely, before exchanging information, always transmit a sequence known at the reception, for example, a sequence of information units.

The accuracy of synchronization is set by acceptable asynchronism, at which signal demodulation with the required reliability is still possible, and depends on the duration of the signal element. In the inventive device with a duration of information sending T _and = 20 ms, the number of frequency components N of the signal matrix is selected equal to 6, the duration of the signal element τ _e is equal to 3.3 ms. Permissible asynchronism in this case is taken to be approximately 0.5 ms, which is about 15% of the signal element duration (see, for example, Sviridenko S.S., Fundamentals of synchronization when receiving discrete signals.-M.: Communication, 1974, p. 70 , Fig. 4.8). The presence of such asynchronism did not reduce the noise immunity of the signal transmission system of the structure described above in the HF radio channel in all cases when the probability of error was set at least 10 ^-2 .

 In the inventive device in the synchronization process, a serial-parallel signal search is performed. At each stage, not one, but several hypotheses about the synchronous position are investigated. Processing several hypotheses at once reduces the synchronization time, but tightens the requirements for speed and complexity of the device. The number of hypotheses processed at one stage is selected by compromise and in our case is 30 hypotheses.

 When the transmitted signal consists of a sequence of information packets known at the reception (for example, in our case, a sequence of “units”), the acceptance of the hypothesis about the position of the beginning of the information packet is uniquely determined by the temporal position of the pulse response at the filter output in each channel.

 At any stage of the search, for each hypothesis (from a group of 30 hypotheses studied at this stage), the functional is calculated as the sum of the modified samples taken on the interval of several informational premises, for example, K. The samples are taken at the moments of the expected filter response in each channel. The resulting amount is compared with a certain threshold. The hypothesis in which a threshold is exceeded is accepted as the correct one, and the signal is read as detected. After that, the amounts of excess of the “true” samples over the average are compared, the accumulation of the amounts of excess of the samples over the average is carried out in parallel with the accumulation of the amounts of the modified samples. The synchronous position is the one that is associated with the hypothesis corresponding to the largest amount of excess counts.

The number of parcels during which the samples are summed up and which determines the duration of the search stage t of the _stage , as well as the threshold value are selected taking into account the set probabilities of false alarm and missed targets and the minimum average time allocated for signal detection. In practice, in the short-wave range, this number corresponds to 10-15 informational messages.

 If at the search stage none of the studied 340 hypotheses was accepted, the position of the time sequences is shifted by one step and the group of new hypotheses is considered. When choosing a step, the size of the interval, which can be studied at one stage, and the requirements for the accuracy of determining the synchronous state are taken into account.

In the inventive device, as was said above, the shift between adjacent synchronization positions Δτ _{ac is} chosen to be 0.5 ms, which is the value of unrecoverable asynchronism.

 When determining the interval that can be examined over the duration of each information packet, it is necessary to take into account the time spent on increasing the signal voltage in the channel filter.

In the inventive device at the sending interval T _i = 20 ms, the observation time T _approx. (time for sampling) is 16.5 ms, the rest of the time T _and -T _approx. = T _rise. (20 ms - 16.5 ms) is reserved for increasing the voltage across the filter. The time allotted for the increase in voltage across the filter is used to process the observation results on the previous premise. The number of hypotheses investigated in the sending interval is
T _obs. / Δτ _ac = 16.5 / 0.5 ≈ 30.
Obviously, the step size after the end of the unsuccessful search stage is 16.5 ms. When a signal is detected, the magnitude of the required shift of the distributor depends on the number of the hypothesis (from 1 to 30), for which the maximum sum of “true” samples has been obtained and lies in the range 0.5 - 16.5 ms.

 After turning on the power, a single time is set manually or automatically, if this is provided for by the system where the claimed device is included. The time is entered into the block 1 of the reference frequencies through the input-time circuit of the sensor pseudo-random codewords 1.4 (see Fig. 7), the signal "Installation" sensor pseudo-random codewords 1.4 is set to the position corresponding to the readings of the entered time. At the same time, all nodes of the device requiring zeroing are put in the initial position (pulse distributor 5, controlled divider 6).

 The signal search mode is set according to the "Synchronization" signal, which can be generated either automatically in some external device or by the will of the operator.

 The operation of the device is illustrated by timing diagrams of various signals, which are presented in FIG. 6 and 7.

 The diagrams show the signals at the synchronous position of the device.

In FIG. Figure 6 shows the sequence of signal elements on the transmission side with the number of elements N equal to six for the duration of the information packet T _and . In FIG. 6b shows responses of filters 2.2 in processing paths of 2 _W. In FIG. Figure 6c shows the moments of the change in the frequencies of the heterodyning voltages for the processing paths: at these moments, a new codeword is written to the buffer registers 1.2-i, which controls the frequency of the tunable frequency synthesizer 1.1-i. In FIG. 6d shows the signals that control the operation of the drive unit 3, and the location of the observation intervals T _approx. and processing T _obrab. for each of the processing channels. In FIG. 7a presents pulses that control the operation of detectors 2.3 _i , these pulses start the operation of DO 2.3 _i . In the intervals between the “Start” pulses, the signals from the output of the detector 2.3 _i are recorded in the memory block 3.i of the drive unit 3. FIG. 7b explains how the signals are located on the time axis to control the process of reading samples from the drive unit 3 into the signal maximum 4 selection unit .

In FIG. 7c shows the timestamps: T _u = 20 ms and τ _e = 3.3 ms.

The first label τ _e on the interval T _{and is} delayed relative to the label T _and by t _s ≈ 10-20 μs (see Fig. 2 delay element 5.6) in order to avoid their coincidence when processed by the programs of microcontrollers DPKS 1.4, as well as BVMS 4.

 The search mode is activated by the command "Synchronization", while the following processes occur in the controlled divider 6 (see Fig. 4 and 5). The RS-flip-flop 6.24 is set to the position where the And 6.9 cell is prepared for the “End of step” signal to pass from the signal maximum selection block 4. In addition, along the leading edge of the voltage at the output of the RS-flip-flop 6.24 (through the differentiation circuit 6.19) are set in the initial position, the counter of steps 6.20 and the timer 6.16 (through the element OR 6.21).

 When filling out the step counter 6.20 from the initial position, the first time the steps are counted up to half the volume of the L / 2 counter (see figure 5). Any subsequent (except for the first after the “Synchronization” command) filling of the step counter 6.20 takes place to its full volume L , where L is the number of steps that can be taken when viewing the entire zone of uncertainty. With an accuracy of the time setting of ± 0.5 s, it is necessary to view the uncertainty zone of 1 s.

.The observation interval at one step is 16.5 ms, this interval is examined for 10 informational parcels, after which a “step” is made and the next 16.5 ms interval is studied. When viewing the entire zone of step uncertainty is L

.

 Choose the nearest even number 62, then L2 / 2 = 31. The search process always starts in the direction of accelerating and eliminating the possible lag in the operation of the pulse distributor 5. For this, in the controlled divider 6, the TV trigger 6.13, on the position of which determines the acceleration or deceleration of the pulse distributor 5 after each step, is set to appropriate position.

 So, at the beginning of the search, 31 steps (L / 2) are carried out with the pulse distributor 5 shifting in the direction of accelerating its operation, after which the step counter 6.20 is reset (see Fig. 5) along the chain: the output of the L / 2 counter to L / 2 6.20 .4, elements AND 6.20.5, OR 6.20.6, OR 6.20.7. At the same time, the signal from the output of the step counter 6.20 (see Fig. 4), the TV trigger 6.13 is shifted to a different position, removing control from the circuits that accelerate the pulse distributor 5. Subsequent shifts will be made by slowing down the pulse distributor 5. In addition, in the step counter 6.20 with the delay necessary to complete the zeroing of the counters 6.20.1, 6.20.4 (see delay element 6.20.3 <1 μs), the RS-trigger 6.20.2 is activated, prepares the step counter scheme to the counting mode to L. Moreover, starting from the second filling of the step counter 6.20 , the calculation is performed up to L = 62, after which the direction of the shifts of the pulse distributor 5 again changes. So that part of the device works until the synchronization signal is detected.

So, the device started searching for a signal. At the outputs of BOC 1 there is a successive change in the frequencies of the heterodyning voltages. At each of the outputs, the frequency remains unchanged during the duration of the information packet T _and , at the same time, the frequency changes are shifted relative to each other by a time τ _e equal to the duration of the signal element, see the diagram in FIG. 6s

 The frequency ratings of the heterodyning voltages are assigned in accordance with the program DPKS 1,4 (see Fig.9).

The DPKS 1.4 program begins with the perception of information about the current time, which enters through the I / O circuit of the microcontroller (MK-31) by the "Installation" signal. After receiving information about the current time, the state of the M-sequence registers (organized by software) is recalculated in accordance with the current time. After which the program is ready for the perception of marks T _and On admission tags T _and N of the recording reference frequency codes for the current interval T _and working registers of the processor (in this case N = 6, i.e., six reference frequencies stored codes (code words six). Then, the memory cell in which organized counting the interruptions τ _e (counting up to N = 6), zeroing and resolving interrupts by the labels τ _e (Pr.11 in MK-31). Waiting for the arrival of interrupt τ _e , the machine performs the steps to calculate the new state of the registers of the M-sequence interval T _and the formation and in accordance with this new state of new codewords corresponding values of the reference frequency in the next interval T _u. On admission interrupt label τ _e is incremented by "1" the contents of the memory location where the calculated τ _e interrupts. Then issued for address-data bus address corresponding to the number (in the program is named M) of the received interrupt τ _e . An address tracking pulse (ISA) and a “Write” signal from the DPKS 1.4 are also output, which are fed to the recording pulse generation block 1.3. In response to these signals, in the recording pulse shaping unit 1.3, to which the above signals were currently addressed, a response signal is generated that goes to the “Resolution” input of the DPKS 1.4. The "Resolution" signal is generated on the basis of the "Record" signal by delaying it for a time <1 μs, which is necessary for the nodes to operate in the recording pulse generation block 1.3 (see delay element 1.3.3 in Fig. 10). After receiving this signal, DPCS 1.4 issues a code word from the working register to the SHAI, the number of which corresponds to the interrupt number M _e , so that the word is then recorded in the corresponding buffer register 1.2.1 of the block of reference frequencies 1.

Then in the program it is checked whether the allowed number of interruptions τ _e has passed (it is checked whether M = N, where N = 6). If not, the program returns to calculating the new state of the M-sequence registers. Of course, the time required for these calculations should be less than the duration T _and . If the number of interruptions τ _{e has} reached six (i.e., the equality M = N holds), then the program prohibits these interruptions and returns to waiting for the label T _and . Then everything repeats.

In each processing path 2 _{i of the} claimed device, the input signal after the frequency conversion in the converter 2.1 (based on the currently incoming heterodyne voltage) passes a narrow-band filter 2.2 and is detected in a digital envelope detector 2.3.

The values of the envelope of the signal in each processing path 2 ₁ , ..., 2 _N in the form of a digital code from the output of the detector 2.3 are sent to the information input of the drive unit 3. The moments of the formation of digital samples are set by the signals “Start” of the envelope detector 2.3. The “Trigger” signals are generated in the pulse distributor 5. The diagrams of these signals for each of the processing paths 2 ₁ , ... 2 _{N are} presented in Fig. 7a). During the information transmission (i.e., the duration of the existence of a heterodyne voltage of a single frequency), 30 samples are taken - as many as hypotheses are considered in the observation interval T _approx .

In the observation interval T _obs. in the memory blocks 3.1, ..., 3.N, respectively, for each processing path 2 ₁ , ... 2 _N 30 samples are recorded - according to the number of trigger pulses of the detector 2.3.

 The calculation of the recorded digital values of the processed signal and the formation based on the count of the recording address is carried out in the counter 3.1.9 (see Fig. 12). The count is allowed by the signal from the RS-trigger 3.1.15, which is triggered by a pulse at the output of the differentiating circuit 3.1.14 along the leading edge of the first trigger pulse of detector 2.3 (see the diagram in Fig. 7a)).

 The formation of the digital reference value in DO 2.3 begins on the leading edge of each trigger pulse. The width of the pulses "Start" from the pulse distributor 5 is set greater than the time required for the formation of the digital value in DO 2.3.

 Between the “Start” pulses, digital samples are recorded in RAM 3.1.1. At these times, the digital outputs of the envelope detectors 2.3 are connected via a bi-directional bus amplifier 3.1.2 to the data output bus of RAM 3.1.1. At the same time, the output of the counter 3.1.9, which forms the address of the record, is connected to the address input of RAM 3.1.1 through the DNSSh 3.1.4. After passing 30 counts, the counter 3.1.9 stops and resets. The resolution of the account is removed, since the RS-trigger 3.1.15 is switched by the signal coming from the output of the decoder to thirty 3.1.6.

At the end of the observation interval, N _approx. on the processing interval T _obrab. the samples recorded in the memory blocks 3.1 - 3.N are read in the block for selecting the maximum signal 4 in turn, starting from the processing path 2 ₁ and ending with the processing path 2 _N.

.On Fig shows a block diagram of an algorithm for processing received signals. The program for processing samples begins by interruption "Beginning of a step", received at the input of Pr. 9 of the MK-31 microcontroller 4.1 into the block for selecting the maximum of signal 4 from the controlled divider 6. Upon receipt of the “Beginning of the step” interrupt, the RAM cells of the microcontroller are reset, in which the counting of processing cycles is organized; counting the number of channels processed on one T interval _and (counting up to N = 6); counting K the number of intervals T _and necessary to make a decision about the presence (or absence) of a signal at K = 10. After that, the processing of interrupts by pulses T _and and

.

, которое означает начало интервала обработки, микроконтроллер вырабатывает адрес подлежащего считыванию отсчета: 3 разряда адресного слова содержит номер блока памяти 3.1 в блоке накопителей 3, к которому обращается машина, остальные разряды адресного слова содержат номер отсчета (один из 30-ти). В блоке памяти 3.1 три разряда ШАИ, с помощью которых указывается номер блока памяти, подключены к второму входу дешифратора 3.1.11 (см. фиг.12).At the beginning of each processing interval, the samples are read from the drive unit 3, and the MK-31 4.1 microcontroller completely controls the reading process. By interruption Prv.10

, which means the beginning of the processing interval, the microcontroller generates the address of the sample to be read: 3 bits of the address word contains the number of memory block 3.1 in the drive block 3, which the machine is accessing, the remaining bits of the address word contain the number of the sample (one out of 30). In the memory block 3.1, three bits of the ShAI, with which the number of the memory block is indicated, are connected to the second input of the decoder 3.1.11 (see Fig. 12).

 If the number of this memory block 3.1 corresponds to the code of these 3 digits, then an output is generated at the output of the decoder 3.1.11, by which the contents of the address word are recorded in the storage register 3.1.12, which determines the reference number and is the address for reading the reference value from RAM 3.1.1.

 In the processing interval, bidirectional amplifiers ДНШУ 3.1.3 and 3.1.5 are open, therefore, the address of the readout reading is connected to the address input of RAM 3.1.1. The data output of the RAM 3.1.1 is connected briefly to the address-information buses using the “Data Ready” pulse generated from the signal at the output of the decoder 3.1.11 with a small delay t necessary for the operation of the register 3.1.12. Reading all 30 samples takes about 60 μs, because carried out with the speed of the microcontroller.

In accordance with the processing program for a group of 30 samples belonging to this processing path, the average is calculated. Then the samples are modified into two categories. Each of the 30 samples is compared with the average value obtained for this channel for the observation interval T _approx. . If the count is larger than the average, then two modifications of the count become corresponding to it: the first is equal to “unit”, the other is equal to the excess of this count over the average.

A sample modified to one is added to the sum of samples of the first modification that has an index corresponding to the number of this sample. A count modified to an excess of the average is added to the amount accumulating the excess of the average and having the corresponding index. This procedure is performed for each of the 30 samples in this channel. According to the next interruption of Pr.10 (τ _e ), the MK-31 4.1 microcontroller starts similar processing of 30 samples stored in the next memory block 3. (i = 1).

After adding all the samples to the corresponding amounts in 30 cells of the RAM, the sums of the first, second, ..., thirtieth samples of the first modification for all 6 processing paths (channels) are accumulated - we denote them by Σ $\genfrac{}{}{0ex}{}{\text{1}}{\text{1}}$ , Σ $\genfrac{}{}{0ex}{}{\text{1}}{\text{2}}$ , Σ $\genfrac{}{}{0ex}{}{\text{1}}{\text{3}}$ , ..., Σ $\genfrac{}{}{0ex}{}{\text{1}}{\text{thirty}}$ . .

In the other 30 cells, the sums of samples of the second modification are accumulated - Σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{1}}$ , Σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{2}}$ , Σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{3}}$ , ..., Σ $\genfrac{}{}{0ex}{}{\text{2}}{\text{thirty}}$ .
After the next observation interval, each of the sums will be increased by adding the corresponding samples if they exceeded the average value. Thus, the maximum value of the samples added to the sum after processing the samples on the interval T _and is 6 (according to the number of processing channels) or less if the samples were lower or equal to the average.

After 10 intervals T _and (in our case K = 10), a maximum of 60 terms can be accumulated in each sum. At the end of this accumulation, i.e. upon reaching K of number 10, each of the 30 sums of samples of the first modification is compared with a set threshold. If the threshold is not reached in any of the sums, then in the block 4 for selecting the maximum signal, the signal "End of Step" is generated, it is issued through the MK-31 4.1 I / O circuit to the input of the controlled divider 6, after which the machine returns to waiting for an interrupt by signal "The beginning of the step."

 In the controlled divider 6 (see FIG. 4), the “End of step” signal passes cell AND 6.9, firstly, it increments the state of the step counter 6.20 by one, and secondly, it resets timer 6.16 to “0” (via OR 6.21) . At the same time, the output signal of the decoder 6.17 is also reset, which leads to the closure of the And 6.7 cell and, on the contrary, through the Inverter 6.15, the operation of the And 6.8 cell is allowed, as well as the counting of pulses entering the counting input of the timer 6.16. If at the moment the trigger 6.13 is in the position when there is one at its output connected to the input of the And 6.8 cell, then the voltage from the And 6.8 output opens the passage of the “High frequency” pulses (in our case 3 kHz) through the And 6.6 cell, that is, the frequency of the pulses passing to the pulse distributor 5 through the cell OR 6.22 increases. In normal mode, pulses from AND 6.7 from the output "Low frequency" (in our case 1.5 kHz) of the frequency divider 6.4 pass through the OR 6.22 cell. The timer 6.16 calculates such a number of pulses that provides a phase shift of the pulse distributor 5 by 16.5 ms; it is precisely this number that the decoder 6.17 is configured to. As soon as the decoder 6.17 is triggered, the resolving voltage is removed for the counting pulses to pass to the timer 6.16, the And 6.7 cell opens for the “Lower frequency” (1.5 kHz) pulses to pass through it of the normal operation of the distributor 5 and the And 6.8 and And 6.6 cells are closed, which stops the receipt of pulses "High frequency" (3 kHz) to the cell OR 6.22. In addition, at the output of the element, a delay of 6.23 (the delay is necessary for the operation of the above logical elements and is <1 μs), the signal "Beginning of the step" is generated. As a result, the pulse distributor 5 continues to operate at normal speed, being shifted forward 16.5 ms.

 If at the moment of arrival of the “End of Step” signal, trigger 6.13 was in a position when there was zero voltage on its arm controlling cell And 6.8, then in this case no counting pulses pass to pulse distributor 5 during the operation time of timer 6.16. As a result, the pulse distributor will be delayed (shifted "back") by 16.5 ms. As mentioned above, shifts forward (or backward) are repeated after each arrival of the “End of step” signal, until the entire zone of uncertainty is completed, and the step counter 6.20 counts to L. After that, the trigger 6.13 is flipped to a different position by the output of step counter 6.20. , and therefore, the direction of the shift will be changed at subsequent L steps, etc.

 If at one of the steps of one of the sums accumulating the samples of the first modification, the threshold is reached (see the flowchart of the algorithm in Fig. 16), then the program proceeds to view the sums of samples of the second modification. Of these amounts, the maximum is selected, and the position of the samples that formed this amount is taken as synchronous. The number of this amount is remembered.

 Through the I / O circuits of the MK-31 4.1 microcontroller, “Synchronization is” signals are issued, as well as bits of a code word containing information about the sum number (hypothesis number), the position of which is assumed to be synchronous.

 The detection and synchronization program ends here, the machine can begin to perform other tasks, for example, a demodulation program.

 The signals "Synchronization is" and bits "Hypothesis number" are supplied to the corresponding inputs of the controlled divider 6 (see figure 4). As a result, the operation of the nodes of the controlled divider 6, which provide the shifts of the distributor 5 described above at steps in the uncertainty zone, is prohibited, since the RS-trigger 6.24 signal is set to the position at which the And 6.9 cell is closed and passage to the pulse circuit is prohibited "End of step." In addition, the signal "Synchronization is" affects the input enable recording external information in the reverse counter 6.11. The information inputs of this counter simultaneously receive all bits of the code with the hypothesis number of the synchronous position. As a result, the hypothesis number is entered in the reverse counter 6.11. The decoder 6.12 connected to the output of the reversible counter 6.11 is set to the zero position of the counter. As soon as the hypothesis number of the synchronous position is set in counter 6.11, the decoder 6.12 removes its output voltage. This leads to the fact that, firstly, cell AND 6.5 closes, and, secondly, through the element NOT 6.14, the passage of counting pulses to the counter-divider 6.10 is allowed. During the time that the AND 6.5 cell is closed, pulses do not pass that ensure the operation of the pulse distributor 5, as a result, the pulse distributor is delayed by this time, and all the pulse sequences generated by it are shifted to the settling side. The magnitude of the shift exactly matches the hypothesis number of the synchronous position. This compliance is ensured by the selection of the frequency of the counting pulses and the division ratio of the counter-divider 6.10. Pulses from the output of the counter-divider 6.10 are received at the counting input of the reverse counter 6.11. As soon as the position of the reverse counter 6.11 reaches zero, the decoder 6.12 is activated, the AND 6.5 cell opens and the normal passage of pulses to the distributor 5 is restored again. At the same time, the resolution of the counter-divider 6.10 is removed. All time sequences of the device are set in synchronous position.

Claims (3)

1. A device for detecting signals with software tuning of the operating frequency, comprising a block of reference frequencies, a block of storage devices, a block for selecting the maximum signal and N parallel processing paths (where N≥ 2), each of which contains a frequency converter, a bandpass filter, and an envelope detector, moreover, the signal inputs of all frequency converters are combined and are the signal input of the device, the inputs of the heterodyning voltages of the frequency converters are connected to the corresponding frequency outputs lock of the reference frequencies, the outputs of each of the N processing paths are connected to the corresponding information inputs of the drive unit, the information outputs of which are connected to the inputs of the signal maximum selection unit, characterized in that an additional pulse distributor and a controlled divider with inputs "Synchronization" and "Installation", the last of which is connected to the “Start” inputs of the block of reference frequencies and the pulse distributor, the outputs “Clock frequency” and “Reference clock frequency” of the controlled divider are connected to the corresponding uyuschim input pulse distributor input "T _and" and the interrupt input "τ _e" reference frequency block pairwise combined to inputs "T _{and" i} "τ _e" maximum block selecting signal, and are respectively connected to the outputs of the pulse of duration T _and u τ _e pulse distributor, the “Start” input of each of the processing paths is combined with the corresponding “Record” input of the drive unit and connected to the corresponding “Start” output of the pulse distributor, N outputs “Resolution” of the pulse distributor are connected to the corresponding N inputs “Resolution the drive unit, the output of the controlled divider "Start of step" is connected to the corresponding input of the interrupt "Start of step" of the block for selecting the maximum signal, the outputs are "Synchronization is", "End of step" of which and M outputs "Hypothesis number" are connected to the corresponding inputs of the controlled divider (where M = 2, 3, ...,), N inputs of “Data Readiness” of the signal maximum selection block are connected to the corresponding outputs of the drive block, the “Address Tracking Impulse” input of the drive block is connected to the output of the signal maximum selection block of the same name la further has a reference frequency block input time. 2. The device according to p. 1, characterized in that the pulse distributor contains a counter-divider by R, N two-input elements AND, N inverters, N differentiating circuits, two-input OR element, N-input OR element and delay element, inputs of N inverters and N differentiating chains are pairwise combined and connected respectively to 1, ..., N outputs of a divider counter on R, the output of the first differentiating chain is connected to the input of the delay element, the output of which is connected to the first input of the N-input element OR, the outputs of the remaining differentiating x chains are connected to the corresponding N - 1 inputs of the N-input OR element, the (N + 1) -th output of the counter-divider on R is connected to the first input of the two-input OR element, the output of which is connected to the input "Zeroing" of the counter-divider on R, the outputs of N inverters are connected respectively to the first inputs of N elements And, the second inputs of which are interconnected and are the input "Clock frequency" of the pulse distributor, the outputs of all elements And are the first group of N outputs "Start" pulse distributor, the counting input of the divider counter and R is the input "Reference clock frequency" of the pulse distributor, the outputs of N inverters form the second group of N outputs "Resolution" of the pulse distributor, the second input of the two-input element OR is the input "start" of the pulse distributor, the output of the first differentiating circuit and the output of the N-input element OR are respectively pulse outputs of duration T _and and τ _{e of} the pulse distributor.  3. The device according to claim 1, characterized in that the controlled divider comprises a reference generator, first, second and third frequency dividers, a divider counter, first and second decoders, a reversible counter, a step counter, a timer, five two-input elements And, two two-input OR element, two inverters, two differentiating circuits, delay element, TV-trigger and RS-trigger, the output of the reference generator is connected to the input of the first frequency divider, the counting input of the counter-divider is combined with the first input of the first AND element and connected to the output of the first th frequency divider, the output of the counter-divider is connected to the counting input of the reverse counter, the outputs of which 1,. . ., G are connected respectively to the inputs of the first decoder, the second input of the first element And is combined with the input of the first inverter and connected to the output of the first decoder, the enable input of the counter-divider is connected to the output of the first inverter, the inputs of the second and third frequency dividers are combined and connected to the output of the first element And, the output of the upper frequency of the third divider is connected to the first input of the second element And, the second input of which is connected to the output of the third element And, the first input of which receives voltage from the output of the TV trigger, the counting input of the TV trigger is connected to the output of the step counter, the control input of which is combined with the first input of the first OR element and connected to the output of the first differentiating circuit, the input of the first differentiating chain is combined with the first input of the fifth AND element and connected to the output of the RS trigger the counting input of the step counter is combined with the second input of the first OR element and connected to the output of the fifth AND element, the output of the first OR element is connected to the installation input of the timer, the counting input of which is combined with the first input the fourth element And is connected to the output of the lower frequency of the third frequency divider, the outputs of the timer are connected to the inputs of the second decoder, the second input of the fourth element is combined with the input of the second inverter, allowing the input of the timer, the input of the second differentiator circuit and connected to the output of the second decoder, the outputs of the second and of the fourth AND element, respectively, connected to the inputs of the second OR element, the output of the second differentiating circuit is connected to the input of the delay element, the “Resolution” input of the reverse counter inen with the R-input of the RS-trigger and is the input "Synchronization is" of the controlled divider, the second input of the fifth element And is the input "End of step" of the controlled divider, the S-input of the RS-trigger is the input "Synchronization" of the controlled divider, zeroing the input of the reverse counter combined with the installation input of the TV trigger, zeroing the input of the step counter and is the input "Installation" of the controlled divider, inputs 1 ... M of the reverse counter are inputs of the corresponding bits "Hypothesis number" of the controlled divider, output element Delay is the output signal "Start step" managed divider, the output of the second frequency divider is an output of "clock frequency" managed divider, an output of the second OR output is the reference clock frequency.

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