RU2166772C1 - Detector-measuring instrument of multifrequency signals - Google Patents

Abstract

FIELD: radiolocation. SUBSTANCE: invention is meant for detection of multifrequency radio pulse periodic signals and for measurement of radial velocity of object. It can find use in radar identification systems, in radars controlling air traffic to detect and measure velocity of aircraft. Detector-measuring instrument of multifrequency signals has two frequency channels processing initial readings with the aid of delay units, complex interface, complex multiplication, averaging, computation of modulus, two dividers, two multipliers and adder, circuit computing evaluation of Doppler velocity based on units computing phase and multiplier connected in series, and two circuits of integration of frequency channels on basis of additional adder and additional unit of complex multiplication together with unit of complex interface. EFFECT: increased efficiency of detection and precision of measurement thanks to reduced number of functional transformations. 9 dwg

Description

 The invention relates to the field of radar and is intended to detect multi-frequency radio-pulse periodic signals and measure the radial velocity of the object; It can be used in radar recognition systems, as well as in air traffic control radar stations for detecting and measuring the speed of aircraft.

 Known filter non-tracking multi-channel meter [1], each channel of which contains a matched filter and a detector connected in series, the outputs of the channels are combined by a resolver. However, this device has low detection efficiency and measurement accuracy, as well as the complexity of implementing multi-channel processing.

 Also known is a radar device for detecting a moving target [2], containing sequentially included delay units, a complex number multiplier and a subtractor. However, this device has low accuracy and ambiguity of measurement.

 Closest to the invention is a Doppler signal detector-meter [3], selected as a prototype, comprising a delay unit, the outputs of which are connected to the inputs of the complex conjugation unit (based on an inverter), the outputs of which are connected to the first inputs of the complex multiplication block, the second inputs of which combined with the inputs of the delay unit, which are the inputs of the detector-meter, the outputs of the complex multiplication unit are connected to the inputs of the averaging unit, the outputs of which are connected to the inputs of the unit module and inputs of the phase calculation unit, the output of the module calculation unit is connected to the second input of the threshold unit, the first input of which is connected to the second memory unit, the control input of the key is connected to the output of the threshold unit, which is the first output of the detector-meter, the second output of which is the output of the unit multiplication, the first and second inputs of which are respectively connected to the output of the first memory block and the output of the key. However, this device has low detection efficiency and measurement accuracy due to the presence of a large number of functional transformations associated with signal processing using wobble of the repetition period.

 The problem to be solved in the invention is to increase the detection efficiency and measurement accuracy due to fewer functional transformations when using multi-frequency signal processing together.

 To solve the problem in the detector-meter of multi-frequency signals, containing the I-th channel, the phase calculation unit, the multiplication unit, the first memory unit, the threshold unit, the second memory unit, the key and the clock generator, and the I-th channel consists of a delay unit, a unit complex conjugation, complex multiplication block, averaging block, module calculation block, the 2nd channel is added, an additional complex conjugation block, an additional complex multiplication block, an additional adder, and the 2nd channel h delay block, complex conjugation block, complex multiplication block, averaging block, module calculation block, in addition, two division blocks, two multiplication blocks and an adder are additionally introduced into Channel I, two division blocks, two are added to Channel II multiplication block and adder.

 Additional blocks introduced into the proposed device are known. So, the delay unit, the complex conjugation unit, the complex multiplication unit, the averaging unit, and the module calculation unit, which are components of both the I and II channels, connected together with the threshold block form an invariant system for processing radio signals and are used to detect them. However, the combined use of the I and II channels combined by an additional adder is unknown, and the use of the additionally introduced dividing, multiplication, and adder blocks in each channel providing the Doppler phase-adaptive signal processing signal samples, which provides increased detection efficiency. It is also unknown to use the scheme of combining frequency channels on the basis of additional blocks of complex conjugation and multiplication, in addition, the presence of new connections between the blocks provides increased measurement accuracy due to fewer functional transformations when using joint processing of a multi-frequency signal. Communications between the clock and all blocks of the Doppler phase meter of multi-frequency signals provide consistent processing of the multi-frequency sequence of radio pulses.

 Comparison with the technical characteristics known from published sources of information shows that the claimed solution has novelty and has an inventive step.

 The claimed solution is technical in nature, feasible, reproducible and, therefore, is industrially applicable.

 In FIG. 1 is a structural electrical diagram of a detector-meter of multi-frequency signals; figure 2 - block delay; figure 3 - block complex conjugation; figure 4 - block complex multiplication; in FIG. 5 - averaging unit; figure 6 - unit calculation module; in FIG. 7 - phase calculation unit; in FIG. 8 - character assignment unit; in FIG. 9 shows the detection characteristics of the prototype and the proposed device.

 The multi-frequency signal detector-meter contains two channels (I, II), each of which includes a delay unit 1, complex conjugation unit 2, complex multiplication unit 3, averaging unit 4, module calculation unit 5, while the outputs of the delay unit 1 are connected to the inputs complex conjugation unit 2, the outputs of which are connected to the first inputs of the complex multiplication unit 3, the outputs of which are connected to the inputs of the averaging unit 4, the outputs of which are connected to the inputs of the module calculation unit 5, the inputs of channel I and channel II are the combined inputs of the same name of the delay block 1 and the second inputs of the complex multiplication block 3 of the corresponding channels, the phase calculation block 6, the multiplication block 7, the first memory block 8, the threshold block 9, the second memory block 10, the key 11, the clock generator 12, an additional block 13 complex conjugation, additional complex multiplication unit 14, additional adder 15, the output of the first memory unit 8 is connected to the first input of the multiplication unit 7, the output of which is connected to the input of the key 11, the control input of which is connected to the output of the pores unit 9, the first input of which is connected to the output of the second memory unit 10, the outputs of the additional complex conjugation unit 13 are connected to the first inputs of the additional complex multiplication unit 14, the outputs of which are connected to the inputs of the phase calculation unit 6, the output of which is connected to the second input of the multiplication unit 7 , the output of the additional adder 15 is connected to the second input of the threshold block 9, in addition, the I-th and II-th channels additionally contain two blocks 16, 17 division, two blocks 18, 19 multiplication and the adder 20, while the output of block 5 the calculation of the module is connected to the first inputs of the division blocks 16, 17, the outputs of the averaging block 5 are connected to the same second inputs of the division blocks 16, 17 and 18, 19 of the multiplication, the outputs of the multiplication blocks 18, 19 are connected to the inputs of the adder 20, the first output I of the 1st channel is the output of the adder 20 of the 1st channel, the first output of the 2nd channel is the output of the adder of the 2nd 2nd channel, the outputs of the blocks 16, 17 of the division of the 1st channel are respectively connected to the first inputs of the 18,19 multiplication blocks of the 1st channel and are its second outputs, outputs are Ovs 16, 17 of the division of the second channel are respectively connected to the first inputs of the blocks 18, 19 of the multiplication of the second channel and are its second outputs, the first output of the first and the first output of the second channel are connected to the inputs of the additional adder 15, the second outputs Channel I is connected to the second inputs of the additional complex multiplication block 14, the second outputs of Channel II are connected to the inputs of the additional complex conjugation block 13, the output of the clock generator 12 is connected to the clock inputs of all the blocks of the detector-meter of multi-frequency signals, ervymi and second inputs which are respectively input I-st and the II-th channel, and first and second output - outputs, respectively, the threshold unit 9 and a key 11.

 The delay units 1 of the 1st and 2nd channels contain two delay lines 21 per interval T, the inputs of the delay units are the inputs of the delay line 21, the outputs of which are the outputs of the delay units.

 The blocks 2 complex conjugation of the 1st and 2nd channels and the additional block 13 complex conjugation comprise an inverter 22, the first input of the complex conjugation block is its first output, the second input is the input of the inverter 22, the output of which is the second output of the complex conjugation block.

 The blocks 3 of the complex multiplication of the 1st and 2nd channels and the additional block 14 of the complex multiplication contain two channels (I, II), each of which includes the first multiplier 23, the second multiplier 24 and the adder 25 connected in series, the output of the first multiplier 23 of one channel connected to the second input of the adder 25 of another channel, and the first and second inputs of the complex multiplication block, respectively, are the combined first inputs of the first and second multipliers 23, 24 of each channel, the combined second inputs of the second th multipliers 24 and the combined first inputs of the second multipliers 23 and the output unit are complex multiplication outputs of adders 25 channels.

 Blocks 4 of averaging of the 1st and 2nd channels contain two channels (I, II), each of which consists of N-1 series delay lines 26 for the interval T and N-1 of adders 27, the inputs of the averaging block are the combined inputs of the first the delay line 26 and the first adder 27 of each channel (I, II), and the output of the Kth (K = 2, (Nl)) delay line 26 is connected to the second input of the Kth (K = 2, (N-1)) the adder 27 of each channel (I, II), the outputs of the averaging block are the outputs of the (N-1) -th adder.

 The calculation blocks 5 of the module of the first and second channels contain two multiplication units 28, an adder 29 and a square root extraction unit 30, the inputs of the module calculation unit are the inputs of the multiplication units 28, the outputs of which are connected to the first and second inputs of the adder 29, the output of which connected to the input of the square root extraction unit 30, the output of which is the output of the module calculation unit.

 The phase calculation unit 6 consists of a series-connected divider 31, a functional converter 32, a modular block 33, an adder 34, a character assignment unit 35 and a first key 36, the output of the functional converter 32 is connected to the input of the second key 37, the second input of the adder 34 is connected to the output of the unit 39, the control inputs of the first and second keys 36.37 are connected to the input of the divider 31 corresponding to the input of the real part of the complex number, the first input of the character assignment unit 35 is connected to the input of the divider 31, corresponding m input the imaginary part of a complex number, the outputs of the first and second switches 36,37 are connected to inputs of an adder 37, whose output is the output of the phase computation unit whose inputs are the inputs of the divider 31.

 The character assigning unit 35 comprises multiplication units 40, 43, a memory unit 41 and a limiter 42, the first input of the character assigning unit being the first input of the multiplying unit 40, the second input of which is connected to the output of the memory unit 41, the output of the multiplying unit 40 is connected to the input of the limiter 42 whose output is connected to the first input of the multiplication unit 43, the second input of which is the second input of the character assignment unit, the output of the character assignment unit is the output of the multiplication unit 43.

 The Doppler phase meter of multi-frequency signals operates as follows.

где U^(k) _j - j-й отсчет последовательности комплексных величин в k-м частотном канале;
x^(k) _j и y^(k) _j - соответственно действительная и мнимая части комплексного отсчета;
k - номер частотного канала, причем k = 1,2;
Φ $\genfrac{}{}{0ex}{}{\text{(}}{\text{0}}$ ^k)- начальная фаза в k-м частотном канале;
Φ^(k) - доплеровские сдвиги фаз сигнала за период повторения Т в k-м частотном канале, равный

где F $\genfrac{}{}{0ex}{}{\text{(}}{\text{∂}}$ ^k) - доплеровская частота в k-м канале;
Т - период повторения импульсов;
f^(k) _н - k-я несущая частота, причем f⁽¹⁾ _н больше f_н ⁽²⁾;
v_r - радиальная скорость цели.A multi-frequency signal, consisting of two frequency components, is fed to the input of each frequency channel of the receiver, where amplification stages are successively converted into quadrature phase detectors at a video frequency and, through analog-to-digital converters (the listed blocks in Fig. 1 are not shown), are fed to the inputs of the claimed devices. In this case, the quadrature components of the signal in each frequency channel are described in a single range resolution element by a sequence of complex quantities

where U ^(k) _j is the jth sample of the sequence of complex quantities in the kth frequency channel;
x ^(k) _j and y ^(k) _j are the real and imaginary parts of the complex reference, respectively;
k is the number of the frequency channel, with k = 1.2;
Φ $\genfrac{}{}{0ex}{}{\text{(}}{\text{0}}$ ^k) is the initial phase in the k-th frequency channel;
Φ ^(k) - Doppler phase shifts of the signal during the repetition period T in the k-th frequency channel, equal to

where f $\genfrac{}{}{0ex}{}{\text{(}}{\text{∂}}$ ^k) is the Doppler frequency in the kth channel;
T is the pulse repetition period;
f ^(k) _n is the kth carrier frequency, and f ⁽¹⁾ _{n is} greater than f _n ⁽²⁾ ;
v _r is the radial velocity of the target.

С выходов блоков 3 комплексного умножения отсчеты поступают в блоки 4 усреднения (фиг. 5), осуществляющие с помощью элементов 26 задержки и сумматоров 27 скользящее вдоль азимута суммирование, что приводит к образованию на выходах блоков 4 усреднения величин:

Далее величины a^(k) и b^(k) поступают на входы блоков 5 вычисления модуля (фиг. 6), где в соответствии с его структурой вычисляется модуль входной величины X^(k)

Величины

и X^(k) в соответствующих каналах поступают соответственно на первый и второй входы блоков 16, 17 деления, на основе которых вычисляется величина, равная:

Оценки exp(iΦ^(k)) и величины X^(k) поступают соответственно на первый и второй входы блоков 18, 19 умножения I-го и II-го канала, результаты вычисления с выхода этих блоков поступают на входы сумматора 20. На основе блоков 18, 19 умножения и сумматора 20 I-го канала, блоков 18,19 умножения и сумматора 20 II-го канала при условии, что оценка exp(iΦ^(k)) равна истинному значению exp(iΦ^(k)), реализуется алгоритм:

Отсчеты z⁽¹⁾ и z² (выражение 8) с первых выходов I-го и II-го канала поступают на входы дополнительного сумматора 15, с выхода которого величина, равная
z=z⁽¹⁾+z⁽²⁾≥z₀, (9)
поступает на второй вход порогового блока 9. Если происходит превышение над величиной порога z_o, записанной во втором блоке 10 памяти, то с выхода порогового блока 9, который является первым выходом обнаружителя-измерителя многочастотных сигналов, поступает сигнал, используемый для отсчета других координат, например дальности.The samples U ⁽¹⁾ _j and U ⁽²⁾ _j are respectively received at the inputs of the first and second channels (Fig. 1), where in blocks 1 the delays (Fig. 2) are delayed by the repetition period T. After that, in the blocks 2 complex conjugation (Fig. 3) is a complex conjugation of the delayed reference. Further, in blocks 3 of complex multiplication (Fig. 4), the processing of samples is carried out in accordance with the algorithm

From the outputs of the complex multiplication blocks 3, the readings are sent to the averaging blocks 4 (Fig. 5), which, using the delay elements 26 and the adders 27, carry out summing along the azimuth, which leads to the formation of values averaging at the outputs of the blocks 4:

Next, the values a ^(k) and b ^(k) are supplied to the inputs of the module calculation blocks 5 (Fig. 6), where, in accordance with its structure, the module of the input quantity X ^{(k) is} calculated

Quantities

and X ^(k) in the respective channels respectively enter the first and second inputs of the division blocks 16, 17, on the basis of which a value equal to:

The estimates exp (iΦ ^(k) ) and the quantities X ^(k) are respectively supplied to the first and second inputs of the multiplication blocks 18, 19 of the first and second channels, the calculation results from the output of these blocks go to the inputs of the adder 20. Based on the blocks 18, 19 of multiplication and adder 20 of the I-th channel, blocks of 18.19 multiplication and adder 20 of the II-th channel, provided that the estimate exp (iΦ ^(k) ) is equal to the true value of exp (iΦ ^(k) ), the algorithm is implemented:

The samples z ⁽¹⁾ and z ² (expression 8) from the first outputs of the I and II channels go to the inputs of the additional adder 15, the output of which is equal to
z = z ⁽¹⁾ + z ⁽²⁾ ≥z ₀ , (9)
arrives at the second input of the threshold unit 9. If an excess occurs over the threshold value z _o recorded in the second memory unit 10, then the output of the threshold unit 9, which is the first output of the detector-meter of multi-frequency signals, receives a signal used to read other coordinates, for example range.

вычитаемый в блоке 34 из величины π, поступающей от блока 39 памяти. Полученной разности в блоке 35 присваивается знак величины b.The estimate exp (iΦ ⁽¹⁾ ) directly, and the estimate exp (iΦ ⁽²⁾ ) through the additional complex conjugation block 13 (Fig. 3) are supplied respectively to the second and first inputs of the additional complex multiplication block 14 (Fig. 4), at the output which produces a value equal to:
exp (iΔΦ) = a + ib = exp (i (Φ ⁽¹⁾ -Φ ⁽²⁾ )). (10)
Values a and b are supplied to the corresponding inputs of the phase calculation unit 6 (Fig. 7), where the estimate ΔΦ = arctg (b / a) is calculated based on the division unit 31 and the functional converter 32. Subsequent conversions of ΔΦ depend on the sign of a. When a ≥ 0, the second key 37 is open and the value through the adder 38 directly goes to the output of the phase calculation unit 6. When a <0, the first key 36 is open, and the second key 37 is closed. Thus in the modular block 28 is formed

subtracted in block 34 from the value of π coming from the block 39 of the memory. The resulting difference in block 35 is assigned the sign of b.

поступающей на второй вход блока 35 присвоения знака, то есть на второй вход блока 43 умножения с выхода сумматора 34.Block 35 character assignment (Fig) works as follows. The value b (ratio (10)) is supplied to the first input of the sign-assigning unit, where in the multiplication unit 40 it is multiplied by a constant factor from the memory unit 41 in order to scale and further limit the limiter 42 to a level of ± 1. Thus, after the restriction, the value at the output of the limiter 42 has the meaning of the sign of the quantity b, which, arriving at the first input of the multiplication block 43, is assigned the difference

arriving at the second input of the character assignment unit 35, that is, at the second input of the multiplication unit 43 from the output of the adder 34.

Блок 7 умножения (фиг. 1) осуществляет умножение найденной оценки разности фаз на коэффициент d, хранящейся в первом блоке 8 памяти, что позволяет найти однозначную оценку радиальной скорости в соответствии с алгоритмом:

Таким образом, соответствующим выбором разноса несущих частот обеспечивается необходимый диапазон однозначно измеряемых доплеровских скоростей, который расширяется по сравнению с одночастотным сигналом в f_н/(f⁽¹⁾ _н=f⁽²⁾ _н) раз. При этом сохраняется однозначность измерения дальности, которая обеспечивается соответствующим выбором периода повторения импульсов Т.The operations considered allow, in block 6 of the phase calculation, first to find an estimate of the phase difference within [-π / 2, π / 2], and then using the transformations to expand the limits of its unambiguous measurement [-π, π], in accordance with the algorithm:

Block 7 multiplication (Fig. 1) multiplies the found estimates of the phase difference by the coefficient d stored in the first block 8 of the memory, which allows you to find a unique estimate of the radial velocity in accordance with the algorithm:

Thus, the appropriate choice of carrier frequency spacing provides the necessary range of unambiguously measured Doppler velocities, which expands in comparison with a single-frequency signal by f _n / (f ⁽¹⁾ _n = f ⁽²⁾ _n ) times. In this case, the uniqueness of range measurement is maintained, which is ensured by the appropriate choice of the pulse repetition period T.

 To reduce the likelihood of the device working by noise, it excludes the issuance of the obtained estimate for output in the absence of a signal reflected from the target. If there is an excess over the value of threshold 20, then the output of the threshold unit 9 receives a signal allowing the passage of the calculation result from the output of the multiplication unit 7 through the key 11 to the second output of the detector-meter of multi-frequency signals. Otherwise, key 15 is open.

The synchronization of the detector-meter of multi-frequency signals is carried out by supplying to all the blocks of the claimed device a sequence of synchronizing pulses generated by the sync generator 12 (Fig. 1), with a repetition period t _k determined from the conditions for ensuring the required resolution in range.

In FIG. 9 shows the dependences of the detection characteristics D of the proposed device (curve 1) and the prototype (curve 2) on the signal-to-noise ratio at the input of the device. The characteristics are obtained by the method of statistical modeling on a computer under the condition of equal powers of single-frequency and multi-frequency signals, i.e. q ⁽¹⁾ = q ⁽²⁾ = q / 2, where q is the signal-to-noise ratio for a single-frequency signal. Comparison of the detection characteristics D was carried out for the case of slow signal fluctuations, the probability of false alarm F = 10 ^-3 , the number of pulses in the packet N = 20. As can be seen, the proposed device at a level of 0.9 outperforms the 4 dB prototype.

 Thus, the detector-meter of multi-frequency signals allows to increase the detection efficiency without increasing the signal energy and measurement accuracy due to fewer functional transformations.

Bibliography:
1. Shirman Y.D. and Manzhos V.N. The theory and technique of processing radar information against the background of interference. Moscow. Radio and communication. - 1981. - 204 p. - Fig. 14.2.

 2. Patent N 63-49193 (Japan), MKI G 01 S 13/52. Radar device for detecting a moving target / K.K. Toshiba. Publ. 10/03/1988 - Inventions of the countries of the world - 1989. - Issue 109. - N 15. - 52 p.

 3. Patent N 2017167 (Russia), MKI G 01 S 13/58. Detector-meter of Doppler signals / D.I. Popov, S.V. Gerasimov and E.N. Mataev. Publ. 07/30/1994 - Inventions - 1994. - N 14. - 121 s. Id

Claims (1)

 A multi-frequency signal detector-meter, comprising a first channel, a phase calculation unit, a multiplication unit, a first memory unit, a threshold unit, a second memory unit, a key and a clock generator, the first channel consisting of a delay unit, complex conjugation unit, complex multiplication unit, averaging unit , module calculation unit, while the outputs of the delay unit are connected to the inputs of the complex conjugation block, the outputs of which are connected to the first inputs of the complex multiplication block, the outputs of which are connected to the inputs of the block averaging, the outputs of which are connected to the inputs of the module calculation unit, the inputs of the first channel are the combined inputs of the delay unit and the second inputs of the complex multiplication unit, the output of the first memory unit is connected to the first input of the multiplication unit, the output of which is connected to the input of the key, the control input of which is connected with the output of the threshold block, the first input of which is connected to the output of the second memory block, the output of the clock is connected to the sync inputs of the delay block of the first channel, the complex pairing unit the first channel, the complex multiplication unit of the first channel, the averaging unit of the first channel, the calculation unit of the first channel module, the phase calculation unit, the multiplication unit, the first and second memory blocks, the threshold block, and the key, characterized in that an additional second channel, an additional block, are introduced complex conjugation, an additional block of complex multiplication, an additional adder, moreover, two division blocks, two multiplication blocks and an adder are added to the first and second channels, the second channel consists of b eye delay, complex conjugation unit, complex multiplication unit, averaging unit, module calculation unit, while the outputs of the delay unit are connected to the inputs of the complex conjugation unit, the outputs of which are connected to the first inputs of the complex multiplication unit, the outputs of which are connected to the inputs of the averaging unit, the outputs of which connected to the inputs of the module calculation unit, the inputs of the second channel are interconnected inputs of the delay unit and the second inputs of the complex multiplication unit, the outputs of the additional unit complex conjugation are connected to the first inputs of the additional complex multiplication block, the outputs of which are connected to the inputs of the phase calculation unit, the output of which is connected to the second input of the multiplication unit, the output of the additional adder is connected to the second input of the threshold block, the output of the calculation unit of the module of the first channel is connected to the first inputs the division blocks of the first channel, the output of the calculation unit of the module of the second channel is connected to the first inputs of the division blocks of the second channel, the outputs of the averaging block of the first channel and connected to the interconnected second inputs of the division and multiplication units of the second channel, the outputs of the averaging unit of the second channel are connected to the interconnected second inputs of the units of division and multiplication of the second channel, the outputs of the multiplication units of the first channel are connected to the inputs of the adder of the first channel, the output of which is the first the output of the first channel, the outputs of the multiplication units of the second channel are connected to the inputs of the adder of the second channel, the output of which is the first output of the second channel, the outputs of the division blocks p the first channel are connected to the first inputs of the multiplication blocks of the first channel and are its second outputs, the outputs of the division blocks of the second channel are connected to the first inputs of the multiplication blocks of the second channel and are its second outputs, the first output of the first channel and the first output of the second channel are connected to the inputs of the additional adder, the second outputs of the first channel are connected to the second inputs of the additional complex multiplication block, the second outputs of the second channel are connected to the inputs of the additional complex multiplication block the output of the sync generator is connected to the sync inputs of the delay unit of the second channel, the complex conjugation unit of the second channel, the complex multiplication unit of the second channel, the averaging unit of the second channel, the calculation unit of the second channel module, the additional complex conjugation unit, the additional complex multiplication unit, the additional adder, two blocks division of the first channel, two division blocks of the second channel, two multiplication blocks of the first channel and the adder of the first channel, two multiplication blocks of the second Nala adder and the second channel, wherein the first and second inputs of the detector-meter multifrequency signals are respectively inputs of the first and second channels, and first and second output -, respectively, and outputs the threshold block key.

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