RU2153230C1 - Method and device for synchronization of complex m sequence - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: method involves generation of corrected values of received signal by means of analog processing of information signal samples taking into account signal estimations produced by recurrent transform of already received and corrected values. EFFECT: increased speed of establishing synchronization, when complexity of M sequence increases. 12 cl, 37 dwg

Description

 The proposed technical solutions are united by a single inventive concept and relate to the field of radio engineering, namely to the field of synchronization of complex signals, in particular M-sequences with increased complexity. An M-sequence with increased complexity is considered to be a sequence formed by complicating the structure of an M-sequence by a nonlinear complication node.

Known methods for synchronizing the M-sequence, described, for example:
- in the article by Ward R. "Distinguishing pseudo-noise signals using the sequential estimation method." - Foreign Radio Electronics, 1966, N 8, p. 20 - 37 as a RASE (Rapid Acqusition by Sequental Estimation) rapid recognition method by sequential evaluation;
- in the book of V.I. Zhuravlev "Search and synchronization in broadband systems". - M .: Radio and communications. 1986, p.86-102, as methods for sequentially evaluating characters of a pseudo-random sequence with one step of verification p.86, sequential assessment with two steps of verification p.92, as well as modified methods of sequential estimation, such as a method of sequentially evaluating characters and generating unreliability metrics p. 95, by A.S. 315298 (USSR) (A method of entering synchronism / Authors. Invention. V.I. Kirichenko, Y.D. Khatskelevich. - Publ. V. B. I., 1971, No. 28) and a method for sequential majority evaluation of characters of the PSP p.97 .

 Each of the listed synchronization methods consists in dividing the received information signal into two processing branches, temporarily delaying the information signal in the first branch, generating the evaluation signal and retaining it in the second branch, calculating the correlation coefficient between the delayed part of the information signal of the first branch and the estimated value of the information signal in the second branch, forming a control signal and generating an M-sequence synchronous with the received sequence .

The disadvantages of the above synchronization methods are the relatively high synchronization time and low noise immunity under the influence of intentional interference, which is due to:
- preliminary quantization of the received signal into two or more levels and evaluation of the signal in a discrete form, leading to the loss of some of the information;
- unreasonable refusal to take into account the recursive properties of the M-sequence for predicting the next symbol based on previously received signals and using signal delay, which leads to an increase in the time of synchronization;
- the determinism of the structure of the used M-sequences, which does not provide high structural secrecy of sync sequences and noise immunity under the influence of intentional interference.

The closest in essence to the claimed method of synchronizing the M-sequence with increased complexity is the "Method for synchronizing transmission systems of discrete information with broadband signals" by A.S. SU 1363507 A1 / Aut. Fig. Yu.V. Arzumanyan and A.Kh. Reichlin - Publ. in bull. N 48, 12.30.87. The prototype method of synchronization of the M-sequence consists in receiving a pseudo-random sequence (PSP), storing the received signal of duration T _s , repeatedly reading it k times, forming a reference code sequence (OKP) in discrete form, repeatedly multiplying the received signal of duration T _s and OKP, integrating the results of multiplication, determining the maximum of the discrete cross-correlation function, comparing it with a threshold, establishing correspondence between the received SRP and the system from accounts on the receiving side, the formation of the control action.

The disadvantages of the prototype synchronization method are the relatively high synchronization time and low noise immunity under the influence of intentional interference, which is due to:
- preliminary quantization of the received signal into two or more levels and evaluation of the signal in a discrete form, leading to the loss of some of the information;
- unreasonable refusal to take into account the recursive properties of the M-sequence for predicting the next symbol based on previously received signals, using signal delay and subsequent recalculation to real time, leading to an increase in the timing of synchronization;
- the determinism of the structure of the used M-sequences, which does not provide high structural secrecy of sync sequences and noise immunity under the influence of intentional interference.

Known devices that implement the above methods of synchronizing the M-sequence, described, for example:
- in the article by Ward R. "Distinguishing pseudo-noise signals using the sequential estimation method." - Foreign Radio Electronics, 1966, N 8, p. 23, fig. 2;
- in the book of V.I. Zhuravlev "Search and synchronization in broadband systems". -M. : Radio and communication. 1986, p.86-102, where a device that implements the method of sequential evaluation with one step of verification is shown in Fig. 3.1, and a device that implements the method of sequential evaluation with two steps of verification is shown in p.98;
- by A. p. SU 1626426 A1 / Aut. Fig. V.P. Efimov, V.V. Epishev, S.B. Matlashevsky. - Publ. in bull. N 5, 02/07/91, which implements a modification of the method of successive majority assessment of the SRP symbols as a delay pseudo-noise signal search device.

 Each of the listed devices includes an evaluation signal generating unit, a delay line cascaded through the information inputs, a correlator, and a control device whose output is connected to the first control input of the feedback shift register, the output of which is the output of the synchronization device.

The disadvantages of these synchronization devices are the relatively high synchronization time and low noise immunity under the influence of intentional interference, which is due to:
- preliminary quantization of the received signal into two or more levels and evaluation of the signal in a discrete form, leading to the loss of some of the information;
- unreasonable refusal to take into account the recursive properties of the M-sequence for predicting the next symbol based on previously received signals and using signal delay, which leads to an increase in the time of entering the synchronization;
- the determinism of the structure of the used M-sequences, which does not provide high structural secrecy of sync sequences and noise immunity under the influence of intentional interference.

 The closest in essence to the claimed device for synchronizing the M-sequence is the device presented in the description of the copyright certificate "Method for synchronizing transmission systems of discrete information with broadband signals" by A.S. SU 1363507 A1 / Aut. Fig. Yu. V. Arzumanyan and A. Kh. Raikhlin - Publ. in bull. N 48, 12.30.87. The known prototype device includes a switch cascaded through the information inputs by a shift register, a multiplier, a reference code sequence generator, an integrator, a threshold block, a parallel register, a reference signal generator and a control unit, the output of which is connected to the control input of the reference signal generator, the output of which is output device synchronization.

The disadvantages of the prototype synchronization device are the relatively high synchronization time and low noise immunity under the influence of intentional interference, which is due to:
- preliminary quantization of the received signal into two or more levels and evaluation of the signal in a discrete form, leading to the loss of some of the information;
- unreasonable refusal to take into account the recursive properties of the M-sequence for predicting the next symbol based on previously received signals, using signal delay and subsequent recalculation to real time, leading to an increase in the timing of synchronization;
- the determinism of the structure of the used M-sequences, which does not provide high structural secrecy of sync sequences and noise immunity under the influence of intentional interference.

 The aim of the invention of the claimed technical solutions is to develop a method for synchronizing the M-sequence with increased complexity and a device that implements it, providing a reduction in the time of entry into synchronization with increasing complexity of the M-sequence.

 This goal is achieved by the fact that in the known method, which consists in receiving a pseudo-random sequence, forming a reference code pseudo-random sequence, reading its values, generating a control action and generating a pseudo-random sequence synchronous with the received, a pseudo-random sequence of increased complexity (PSP PS) is received. OKP is formed from a pseudo-random sequence based on the characteristic polynomial of the n-th order, where n≥3, by non-linear transformation by a given discrete function. Its elements are discretized with a frequency k times higher than the clock frequency of the received pseudo-random sequence of increased complexity, where k≥2. In this case, the reference code pseudo-random sequence is formed in analog form, and only the values of the predefined elements of the reference code pseudo-random sequence are read. After that, they are quantized at levels 0 and 1 and delayed for the duration of one element of a pseudo-random sequence of increased complexity. Then, the read values of each of the given elements of the reference code pseudo-random sequence are corrected taking into account the first discretized sample (DO) of the received element of the pseudo-random sequence of increased complexity. The corrected values of the specified elements of the reference code pseudo-random sequence are delayed for the duration of one sample of the received element of the pseudo-random sequence of increased complexity, and then they are re-adjusted taking into account the value of the subsequent sampled sample of the received element of the pseudo-random sequence of increased complexity. Moreover, the correction and delay of the adjusted values are repeated k times. The values corrected k times are quantized at levels 0 and 1 and stored for n cycles and, in addition, the reference pseudo-random code sequence is re-formed from them, the values of the predefined elements of which are corrected at the next cycle of the received pseudo-random sequence of increased complexity.

The reference code pseudorandom sequence is formed according to the recursive rule for generating the M-sequence based on a given characteristic polynomial of the nth order, where n≥3, in which nonzero analog values of its elements are used, and the summation operation modulo 2 of two variables x and y is replaced by the operation
x + y-2xy.

 To correct the read values of the predefined elements of the reference code pseudo-random sequence, they are read during the duration of one sample of the received element of the pseudo-random sequence of increased complexity and are nonlinearly transformed according to a given analog function. The derivatives of the given nonlinear transformation function are calculated from the values of the predefined elements of the reference code pseudo-random sequence, read over the duration of one sample of the received element of the pseudo-random sequence of increased complexity. After that, from the value of the current sampled sample of a pseudo-random sequence of increased complexity, the value of the generated sampled sample of a reference code pseudo-random sequence of increased complexity is subtracted and multiplied by a given weight coefficient. Then, in parallel, multiply by the values of the derivatives for each value of the predefined elements of the reference code pseudo-random sequence obtained earlier, and summed with the corresponding values of the predefined elements of the reference code pseudo-random sequence.

The analog values of the predefined elements of the reference code pseudo-random sequence and the adjusted values of the specified elements of the reference code pseudo-random sequence obtained at the k-th sample of the received element of the pseudo-random sequence of increased complexity are quantized according to the rule
1 if x> 0.5
0 if x≤0.5
Elements of a pseudo-random sequence of increased complexity synchronous with the received one are generated by nonlinear conversion of the given discrete values of the elements of the pseudo-random sequence generated on the basis of the characteristic polynomial of the n-th order, where n≥3, from the quantized corrected values of the given elements of the reference code pseudo-random sequence .

 A control action is formed if, for a duration of 2n clock cycles, all the quantized values of the given elements of the reference code pseudo-random sequence are equal to their corrected quantized values of the given elements of the reference code pseudo-random sequence.

 The specified new set of performed actions of the claimed method for synchronizing an M-sequence with increased complexity through the use of pseudorandom sequences of increased complexity, adjusting the values of predefined signal elements without preliminary quantization in analog form, using the recurrence properties of the M-sequence to predict the next signal element based on previously accepted elements of the signal can reduce the synchronization time, increase the probability of avilnogo complex reception signals, and also increases the structural and immunity concealment synchronization sequence under conditions of jamming.

 The goal in the claimed device is achieved by the fact that in the synchronization device containing a first switch, a reference code sequence generator, a control unit, a reference signal generator, a sampler, a clock selector, an corrector, a quantizer block, a second switch, an analog block and a digital block are additionally introduced delay lines, digital nonlinear complexity node. The receiving information input of the sampler is connected to the input of the clock selector and is the input of the device. The first control output of the clock selector is connected to the control inputs of the first switch, the block of digital delay lines, the control unit, the reference code sequence generator, and the reference signal generator. The second control output of the clock selector is connected to the control inputs of the sampler and the block of analog delay lines. The output of the sampler is connected to the receiving information input of the corrector. The first, second and third information inputs of the corrector are connected respectively to the first, second and third information outputs of the first switch. The first, second and third information outputs of the corrector are connected respectively to the first, second and third information inputs of the block of analog delay lines, the outputs of which are connected respectively to the fourth, fifth and sixth information inputs of the first switch. The first, second and third outputs of the reference code sequence generator are connected respectively to the first, second and third information inputs of the first switch and to the first, second and third inputs of the quantizer block. The fourth, fifth and sixth information outputs of the first switch are connected respectively to the fourth, fifth and sixth inputs of the quantizer block. The first, second and third outputs of the quantizer block are connected respectively to the first, second and third inputs of the digital delay line block, the outputs of which are connected respectively to the first, second and third information inputs of the control unit. The control output of the control unit is connected to the control input of the second switch. The fourth, fifth and sixth outputs of the quantizer block are connected respectively to the fourth, fifth and sixth information inputs of the control unit and, respectively, to the first, second and third inputs of the second switch. The first, second and third outputs of the reference signal generator are connected respectively to the fourth, fifth and sixth inputs of the second switch. The first, second and third outputs of the second switch are connected respectively to the first, second and third information inputs of the reference signal generator and are connected respectively to the first, second and third inputs of the digital nonlinear complication node, the output of which is the output of the device.

 The corrector consists of an analog nonlinear complication node, the first, second, third and fourth analog adders, a constant factor multiplier, the first, second and third analog multipliers and the first, second and third derivatives calculation blocks. The output of the analog nonlinear complexity node is connected to the second information input of the fourth analog adder. The output of the fourth analog adder is connected to the input of the multiplier by a constant factor, the output of which is connected to the first inputs of the first, second, and third analog multipliers, respectively. The second inputs of the first, second, and third analog multipliers are connected to the outputs of the first, second, and third derivatives calculation units, respectively. The outputs of the first, second and third analog multipliers are connected respectively to the first inputs of the first, second and third analog adders, the outputs of which are respectively the first, second and third information outputs of the corrector. The first input of the analog nonlinear complication node, connected to the first input of the third derivative calculation unit, connected to the second input of the first analog adder, is the first information input of the corrector. The second information input of the analog nonlinear complexity node connected to the second input of the third derivative calculation unit and the second input of the second analog adder is the second information input of the corrector. The third input of the analog nonlinear complication node, connected to the input of the second derivative calculation unit, connected to the input of the first derivative calculation unit, connected to the second input of the third analog adder, is the third information input of the corrector. Moreover, the third and second blocks for calculating derivatives are additionally equipped with voltage reference inputs from a voltage source of positive polarity, the structural diagram of which is not shown in the device.

 The reference code sequence generator consists of n analog delay lines, n + 1 constant factor multipliers, and n-1 feedback function calculators. The control input of the reference code sequence generator is connected to the control inputs of n analog delay lines. The outputs of all n analog delay lines are connected to the inputs of the i-th multipliers by a constant factor, where i = 2 ... (n + 1), and the j-th inputs of the analog delay lines, where j = 2 ... n. The outputs of the jth multipliers by a constant factor are connected to the second inputs of the corresponding calculators of the feedback function. The output of the (n + 1) th multiplier by a constant factor is connected to the first input of the (n-1) th calculator of the feedback function. The outputs, starting from the (n-1) -th feedback function calculator to the first, are connected in series with the first inputs of the corresponding feedback function calculators. The output of the first feedback function calculator is connected to the input of the first multiplier by a constant factor, the output of which is connected to the input of the first analog delay line. Moreover, the outputs of predefined analog delay lines are connected to the corresponding multipliers by a constant factor and are respectively the first, second and third information outputs of the reference code sequence generator. The inputs of the delays following the predetermined analog lines are respectively the first, second, and third information inputs of the reference code sequence generator.

 The control unit consists of the first, second and third adders modulo 2, a three-input element OR-NOT, a serial register, a decoder. The outputs of the first, second and third adders modulo 2 are connected respectively to the first second and third inputs of the three-input element OR-NOT, the output of which is connected to the information input of the serial register. The outputs of the serial register from the first to the 2nth are connected to the corresponding inputs of the decoder. The decoder output is the control output of the control unit. The control input of the serial register is the control input of the control unit. The first inputs of the first, second and third adders modulo 2 are respectively the first, second and third information inputs of the control unit. The second inputs of the first, second and third adders modulo 2 are respectively the fourth, fifth and sixth information inputs of the control unit.

 The first switch consists of the first, second, and third “prohibition” switches and the first, second, third, fourth, fifth, and sixth “enable” switches. The control inputs of the first, second and third “prohibition” switches and the first, second, third, fourth, fifth and sixth “enable” switches are connected to the control input of the first switch. The first information input of the first switch is connected to the input of the first "enable" switch, the output of which is connected to the first information output of the first switch. The second information input of the first switch is connected to the input of the third "enable" switch, the output of which is connected to the second information output of the first switch. The third information input of the first switch is connected to the input of the fifth "enable" switch, the output of which is connected to the third information output of the first switch. The fourth information input of the first switch is connected to the input of the first "ban" switch, the output of which is connected to the first information output of the first switch and connected to the input of the second "enable" switch, the output of which is connected to the fourth information output of the first switch. The fifth information input of the first switch is connected to the input of the second "ban" switch, the output of which is connected to the second information output of the first switch and connected to the input of the fourth "enable" switch, the output of which is connected to the fifth information output of the first switch. The sixth information input of the first switch is connected to the input of the third “ban” switch, the output of which is connected to the third information output of the first switch and connected to the input of the sixth “enable” switch, the output of which is connected to the sixth information output of the first switch.

 The second switch consists of the first, second and third “prohibition” switches and the first, second and third “permission” switches. The control inputs of the first, second and third "prohibition" switches and the first, second and third "enable" switches are connected to the control input of the second switch. The first information input of the second switch is connected to the input of the first "ban" switch, the output of which is connected to the first information output of the second switch. The second information input of the second switch is connected to the input of the second "ban" switch, the output of which is connected to the second information output of the second switch. The third information input of the second switch is connected to the input of the third "ban" switch, the output of which is connected to the third information output of the second switch. The fourth information input of the second switch is connected to the input of the first "enable" switch, the output of which is connected to the first information output of the second switch. The fifth information input of the second switch is connected to the input of the second "enable" switch, the output of which is connected to the second information output of the second switch. The sixth information input of the second switch is connected to the input of the third "enable" switch, the output of which is connected to the third information output of the second switch.

 The specified new set of features of the claimed M-sequence synchronization device with increased complexity due to the use of pseudorandom sequences of increased complexity, adjusting the values of predefined signal elements without prior quantization in analog form, using the recurrence properties of the M-sequence to predict the next signal element based on previously received elements Signal allows reducing synchronization time, increasing the probability of correct th complex reception signals, and also increases the structural and immunity concealment synchronization sequence under conditions of jamming.

 The analysis of the prior art by the applicant made it possible to establish that there are no analogues that are characterized by sets of features that are identical to all the features of the claimed method and synchronization device, which indicates compliance of the claimed inventions with the condition of patentability “novelty”.

 The search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the prototypes of each claimed invention have shown that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the popularity of the influence of the essential features of each of the claimed inventions on the achievement of the specified technical result is not revealed. Therefore, each of the claimed inventions meets the condition of patentability "inventive step".

The claimed objects of the invention are illustrated by drawings, which show:
- figure 1 - structure of the generator PSP PS;
- figure 2 - non-linear conversion function for discrete and analog values;
- FIG. 3 - truth tables of the adder modulo 2 and the substitute analog function;
- figure 4 - truth table of discrete and analog nonlinear functions;
- FIG. 5 is an embodiment of using setpoints to form a PSP PS;
- FIG. 6 - the process of forming PSP PS on the transmitting side;
- Fig.7 - oscillograms explaining the essence of the proposed method;
- FIG. 8 - discriminatory characteristics;
- FIG. 9 - oscillograms explaining the essence of the proposed method;
- FIG. 10 is a graph of the number of errors in determining the values of the SRP elements on the processing cycle;
- FIG. 11 is a block diagram of an M-sequence synchronization device with increased complexity;
- FIG. 12 is a diagram of a clock frequency isolator;
- FIG. 13 is a diagram of the corrector;
- FIG. 14 is a diagram of an analog nonlinear complexity node;
- FIG. 15 is a diagram of the first, second, and third blocks for computing derivatives;
- FIG. 16 is a diagram of a first switch;
- FIG. 17 - circuit breaker "prohibition" and "permit";
- FIG. 18 is a diagram of a second switch;
- FIG. 19 - circuit breaker "prohibition" and "permit";
- FIG. 20 is a block diagram of an analog delay line;
- FIG. 21 is a diagram of an analog delay line;
- FIG. 22 is a diagram of a quantizer block;
- FIG. 23 is a block diagram of a digital delay line;
- FIG. 24 is a diagram of a control unit;
- FIG. 25 is a diagram of a three-input element OR-NOT;
- FIG. 26 is a sequential register diagram;
- FIG. 27 is a diagram of a decoder;
- FIG. 28 is a diagram of a reference code sequence generator;
- FIG. 29 is a diagram of a calculator of a feedback function;
- FIG. 30 is a diagram of a reference signal generator;
- FIG. 31 is a diagram of a digital nonlinear complexity node.

где d_j - j-тый элемент М-последовательности, образуемый сложением по модулю 2 некоторого числа предшествующих элементов, хранящихся в регистре, а именно тех из них, коэффициенты (a_i) при которых равны 1.Implementation of the claimed method for synchronizing the M-sequence with increased complexity is as follows. When using complex signals, frequency-time matching of parameters is of great importance. The synchronization process can take a rather long time, depending on the period of the used memory bandwidth and their correlation properties. To form complex signals, M-sequences (Huffman sequences, binary linear recurrence sequences of maximum length) are widely used, which are essentially pseudorandom sequences. The recurrence rule for the formation of the M-sequence can be represented as a recurrence formula:

where d _j is the j-th element of the M-sequence, formed by modulo 2 addition of a certain number of previous elements stored in the register, namely those of them, the coefficients (a _i ) for which are equal to 1.

However, the period of the M-sequence, equal to L = 2 ⁿ -1, where n is the order of the generating polynomial, can turn out to be longer than the time of the communication session, which greatly complicates the process of establishing synchronization and, accordingly, significantly increases the time of establishing synchronization of the M-sequence, except moreover, the structure of any SRP can be easily revealed using 2n adjacent elements of the SRP using the Berlekamp-Messi algorithm described in the article: JL Massey "Shift register syntheses and BCH decoding. IEEE Trans. Inform. Theory, pp. 122-127, 1969, Vol 15, N1. Therefore, in order to avoid opening the M-po structure been consistent and optimized formulation interference synchronization signals, it is necessary to use the pseudo-random sequence of high complexity, for example, formed by a non-linear complexity M-sequence structure node nonlinear complications (NPI). PRS generator structure PS is represented in FIG. 1.

 Linear Recurrent Register (LRR) is a digital feedback shift register. Such registers operate with zeros and ones, and modulo 2 adders are used as a signal converter in the feedback shift register.

 As NUU it is advisable to use those that do not worsen the balance of the output sequence, for example, a sampling node with inversion.

To avoid additional distortions, the PSP PS is formed in analog form, for which the summation operation modulo 2 of two variables x and y is replaced by the expression x + y-2xy, and the discrete nonlinear conversion function is replaced by the corresponding analog nonlinear conversion function, for example, as shown in FIG. .2, where the values x _i , x _j and x _{k are} read from the specified cells of the SRP generator. The truth table of the summation operation modulo 2 and the corresponding analog expression is presented in figure 3, and the truth table of the discrete and the corresponding analog non-linear transformation is presented in figure 4.

 For the formation of an analog PSP, any nonzero values of x and y ranging from 0 to 1 can be used as its elements. In this case, the truth tables of discrete and analog values coincide.

 The diagram of a variant of the structure of the PSP PS generator shown in Fig. 1 allows one to achieve high structural and equivalent linear complexity, which ensures the non-search and greater computational complexity of determining the state of the LRR.

 As the setpoints, nonzero values are used, read from arbitrary, non-repeating LRR cells. An example of the use of setpoints for the formation of the PSP PS shown in figure 5.

Application of this scheme allows one to achieve growth of equivalent linear complexity according to the formula n ₃ = n (n-1). So, for example, with n = 31 n ₃ = 930, and 2n ₃ = 1860.

 The process of forming PSP PS on the transmitting side is presented in Fig.6. Here, the output SRP in the form of an M-sequence of a register constructed on the basis of a primitive trinome of the 31st degree (n = 31) is complicated by the NUU in the form of a sampling node with inversion. In this case, the nonlinear conversion function for discrete values is replaced by its corresponding analog, as shown in Fig.2.

 A section of the PSP PS on the transmitting side has the form shown in FIG. 7 (a). During transmission, the signals are distorted by noise and interference. On the receiving side, the distorted signal has the form, for example, as shown in Fig. 7 (b).

From the received mixture of signal and noise using known methods allocate the clock frequency (F _t ). Known methods for allocating the clock frequency are described, for example, in the book: E.M. Martynov "Synchronization in discrete message transmission systems." -M.: Communication. 1972, p. 107. Gating pulses with a clock frequency of information signals are shown in Fig. 7 (c). The pulse repetition period with a clock frequency of T = 1 / F _t .

Using known methods of frequency division, a frequency is obtained that is k times the clock frequency f _d = kF _t , where k is the number of sampled samples for the duration of one signal information element. The value of k is chosen in the range from 2 to 10, since for k = 1 a degenerate case is obtained and the effect of improving the estimation is not observed, for k> 10, the signal correction time is significantly increased, and the estimation accuracy is practically not increased. Known methods of frequency division are described, for example, in the book: M. L. Leynov, V. S. Kachaluba, A. V. Ryzhkov "Digital frequency dividers on logical elements". -M. : Energy. 1975, p. 93. Gating pulses with a frequency k times the clock are shown in Fig. 7 (g). The pulse repetition period with a frequency k times the clock is τ = 1 / f _d .
In order to avoid introducing additional distortions, the received signal at the input of the demodulator is not quantized into two levels, but is sampled with a frequency f _d . Known methods for sampling signals are described, for example, in the book: J. Marcus. Discretization and quantization ". - M .: Energy. 1969, p. 45. The analogue sampled samples of the received signal are shown in Fig. 7 (e). After sampling, each sampled sample PSP PS is fed to the information input of the corrector, where correcting signals are generated for each values of a given element of the reference code sequence.

 The possibility of making adjustments to the values of the specified OKP elements stored in the cells of the LRR in analog form according to the received by the PSP PS indicates the discriminatory characteristics presented in Fig. 8 (a) and Fig. 8 (b), which is the dependence of the correction voltage D ( ε) from the detuning (ε) of the value of a given OKP element from the true value of an element of the received PSP PS. If the discriminatory characteristic is zero for any detuning values, then it is impossible to adjust the signal due to the ambiguity introduced by nonlinearity. An example of a “null” discriminatory characteristic is shown in FIG. 8 (a). If the discriminatory characteristic is not equal to zero for any detuning values and has the form as shown in Fig. 8 (b), then it is possible to adjust the signal by forming the corresponding corrective action.

 In FIG. Figure 8 (c) presents the discriminatory characteristics constructed for the values of the given elements of the OKP, showing how tuning is performed at each beat. If the adjustment is not performed, then the previous values of the specified elements of the OKP are overwritten.

 Although it can be seen from figure 8 (c) that the number of “zero” and “non-zero” discriminatory characteristics is approximately the same, it is possible to adjust the signal on average.

 In order to most accurately correct the distorted information signal, processing is distinguished when changing the clock intervals of the information signal and inside the clock intervals of the information signal. The sequence of information signals is shown in Fig.9 (a). The sampling frequency is k times higher than the clock frequency of the information signals shown in Fig.9 (b).

 At the moments of the change of the clock intervals on the 1st to the PS PS, the adjusted values of the specified elements of the OKP are formed for the values of the OKP. The moments of the change of the clock intervals are shown in Fig.9 (c). To generate corrective signals for the values of the specified elements of the OKP at the 1st DO PSP PS, use the value of the nonlinear conversion function of the values of the specified elements of the OKP and the derivatives of the nonlinear transformation of the values of the specified elements of the OKP, which are converted according to the recurrence rule for the formation of the M-sequence, the adjusted values information signal received and corrected for (n-1) clock cycles earlier. To this end, from the 1st TO received PSP, PSs subtract the value of the nonlinear conversion function from the values of the specified OKP elements and multiply by the given weight coefficient C. By physical nature, signal amplification by a constant factor corresponds to signal amplification. Known signal amplification methods are described, for example, in the book: A.A.Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 184. The experiments showed that it is advisable to choose the coefficient C in the range from 0 to 1. At the same time, arbitrary nonzero values of the elements of the OKP in the range from 0 to 1 or the values remaining from the last communication session. After that, the values of the specified elements of the OKP are adjusted. In each branch of the adjustment, the signal is multiplied by the values of the corresponding derivatives of the analog function of the nonlinear transformation from the values of the specified elements of the OKP and summed with the corresponding values of the specified elements of the OKP. Known methods for adding signals are described, for example, in the book: A.A.Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M. : Radio and communication. 1983, p. 194. After that, the corrected values of the specified elements of the OKP, obtained at the 1st DO PSP PS, delay for a time τ equal to the duration of one DO. Methods of delaying signals are known and described, for example, in the book: I. A. Tsikin "Discrete-analog signal processing." -M.: Radio and communication. 1982, p. 19.

 At time instants, within the clock intervals, the corrected values of the specified OKP elements are formed from the sampled samples of the received PS bandwidth, starting from the second to the kth. The time instants within the clock intervals are shown in FIG. 7 (g).

 To generate corrective signals for the values of the specified OKP elements at the 2nd TO PSP PS and subsequent to the kth, use the value of the analog nonlinear conversion function and derivatives of the analog nonlinear conversion function from the corrected values of the specified OKP elements obtained from the previous BS received PSP. For this purpose, starting from the 2nd and up to the k-th DO of the received PSP PS, the value of the analog nonlinear conversion function is subtracted from the corrected values of the specified OKP elements obtained from the previous BS of the received PSP PS, and multiplied by the given weight coefficient C. By physical essence, multiplying the signal by a constant factor corresponds to the amplification of the signal. Known methods of signal amplification are described, for example, in the book: A.A.Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M. : Radio and communication. 1983, p. 184. Experiments have shown that it is advisable to choose the coefficient C from 0 to 1. After this, the correction branches are divided into three branches, where corrective signals are generated for each corrected value of the specified OKP elements obtained from the previous DO received PSP. In each correction branch, the signal is multiplied by the values of the corresponding derivatives of the analog nonlinear conversion function of the corrected values of the specified OKP elements obtained from the previous BS of the received PS PS, as a result of which, at the output of the correction block, correction signals are generated for the corrected values of the specified OKP elements obtained from the previous BS accepted PSP PS. Further, in each branch, the correcting signals are summed with the corresponding values of the corrected values of the specified elements of the OKP obtained from the previous TO received PSP PS. Known methods for adding signals are described, for example, in the book: A.A.Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M. : Radio and communication. 1983, p. 194. After that, the corrected values of the specified OKP elements obtained at the 2nd and up to the k-th DO PSP PS are delayed for a time τ equal to the duration of one DO. Methods of delaying signals are known and described, for example, in the book: I. A. Tsikin "Discrete-analog signal processing." -M.: Radio and communication. 1982, p. 19. The corrected values of the specified OKP elements obtained from the k-th DO PSP PS are considered to be the corrected values of the information signal element as a whole. To evaluate the next element of the information signal, all the above operations are repeated.

Similarly, x _i according to the received PS PSP in the corresponding branches, and x _j , x _{k are} adjusted.

In order to determine the correctness of the adjustment, the values of the specified OKP elements are quantized and delayed for the duration of the element of the received PSP PS, as well as the corrected values of the specified OKP elements at the k-th before the received PS PS and delayed by the duration of one before the received PS PS. Methods of delaying signals are known and described, for example, in the book: I. A. Tsikin "Discrete-analog signal processing." -M.: Radio and communication. 1982, p. 19. In each branch of the adjustment, on each clock cycle, modulo 2 values of the specified elements of the OKP and the corrected values of the specified elements of the OKP are summed (the coincidence is determined). The results of the summation modulo 2 in each branch of the processing are added up arithmetically, thereby calculating the number of mismatches of the initial conditions for adjustment and the adjusted values. The presence of zero indicates the coincidence of the initial conditions for adjustment and the adjusted values of the specified elements of the OKP (x _i , x _j , x _k ). If, as a result of summing over 2n cycles of the PSP PS, the initial conditions for correction and the adjusted values of the specified OKP elements coincide, then a control signal is generated to generate the PSP from the corrected values of the specified OKP elements at k-th before the received PSP and delayed by the duration of one before the received PSP PS. Thus, the generated SRP will be synchronous with the received sequence. For the formation of the PSP PS, synchronous with the received PSP PS, a discrete nonlinear conversion function is used.

 At the same time, the receipt of the corrected values of the specified OKP elements according to the ones received before the PSP PS, their conversion according to the recursive rule for the formation of the M-sequence continues. This will make it possible in the future to obtain more accurate a priori information on the values of BEF the received PS bandwidth in order to reduce the time for possible re-entry into synchronization if it is violated.

 The difference between this method and the known ones is that it does not require multiple transmission of clock signals over the communication channel with subsequent majority processing at the reception or error-free reception of the offset segment of the recurrence sequence, since this leads to an increase in the time of entering the synchronization at signal-to-noise ratios less than unity.

The simulation results of the claimed method for synchronizing the M-sequence with increased complexity are presented in FIG. 10 in the form of graphs of the dependence of the number of errors in determining the values of the elements of the SRP from the processing cycle for various options for the formation of OKP. Studies confirm that the determination of the SRP values takes place over a duration much shorter than 2n ₃ , that is, a decrease in the time of entry into synchronization with an increase in the complexity of the M-sequence is ensured.

 The M-sequence synchronization device with increased complexity shown in FIG. 11, consists of a sampler 1, a clock selector 2, a corrector 3, a first switch 4, a second switch 5, a block of analog delay lines 6, a block of quantizers 7, a block of digital delay lines 8, a control unit 9, a generator of reference code sequences 10, a generator reference signal 11, digital nonlinear complication node 12. The receiving information input of the sampler 1 is connected to the input of the clock selector 2 and is the input of the device. The first control output of the clock selector 2 is connected to the control inputs of the first switch 4, the block of digital delay lines 8, the control unit 9, the reference code sequence generator 10, the reference signal generator 11. The second control output of the clock selector 2 is connected to the control inputs of the sampler 1 and block of analog delay lines 6. The output of the discretizer 1 is connected to the receiving information input of the corrector 3. The first, second and third information inputs of the corrector 3 are connected respectively to the first, second, and third information outputs of the first switch 4. The first, second, and third information outputs of the corrector 3 are connected respectively to the first, second, and third information inputs of the block of analog delay lines b, the outputs of which are connected respectively to the fourth, fifth, and sixth information inputs the first switch 4. The first, second, and third outputs of the reference code sequence generator 10 are connected respectively to the first, second, and third information inputs of the first com mutator 4 and to the first, second and third inputs of the quantizer block 7. The fourth, fifth and sixth information outputs of the first switch 4 are connected respectively to the fourth, fifth and sixth inputs of the quantizer block 7. The first, second and third outputs of the quantizer block 7 are connected respectively to the first , the second and third inputs of the block of digital delay lines 8, the outputs of which are connected respectively to the first, second and third information inputs of the control unit 9. The control output of the control unit 9 is connected to the control the input of the second switch 5. The fourth, fifth, and sixth outputs of the quantizer block 7 are connected respectively to the fourth, fifth, and sixth information inputs of the control unit 9 and, respectively, to the first, second, and third inputs of the second switch 5. The first, second, and third outputs of the reference signal generator 11 are connected respectively to the fourth, fifth and sixth inputs of the second switch 5. The first, second and third outputs of the second switch 5 are connected respectively to the first, second and third information inputs of the generator ra reference signal 11 and connected respectively to the first, second and third inputs digital nonlinear node complication 12 whose output is an output device.

Sampler 1 is intended for discretization of an information signal with a frequency k times higher than the clock frequency of information signals (f _d = k • F _t ), where k is the number of required discretized samples for the duration of one element of the received PS bandwidth. By physical nature, discretizer 1 is a chopper. Circuit breakers that can be used as discretizer 1, known and given, for example, in the book: J. Marcus "Discretization and quantization." - M .: Energy. 1969, p. 52, fig. 2.11.

The clock selector 2 is designed to isolate the clock frequency (F _t ) and sampling frequency (f _d ) from the received PSP PS. In terms of physical nature, the clock isolator circuit 2 corresponds to the phase discriminator circuit. The phase discriminator circuit, which can be used in an M-sequence synchronization device, is known and is given, for example, in the book of E.M. Martynova "Synchronization in discrete message transmission systems." - M.: Communication. 1972, p. 108, Fig. 6.16. Considering the features of the claimed device, the circuit of the clock frequency allocator 2 can be implemented as shown in FIG. 12. The clock isolator 2 consists of a master oscillator 2.1, a control element 2.2, a frequency divider 2.3, an averaging device 2.4 and a phase discriminator 2.5. The information input of the phase discriminator 2.5 is the information input of the clock selector 2. The first and second control outputs of the phase discriminator 2.5 are connected respectively to the first and second control inputs of the averaging device 2.4, the first and second control outputs of which are connected respectively to the first and second control inputs of the control
element 2.2. The first control output of the master oscillator 2.1 is connected to the third control input of the control element 2.2, and the second control output of the master oscillator 2.1 in parallel is connected to the fourth control input of the control element 2.2 and to the first control input of the phase discriminator 2.5. The control output of the control element 2.2 is connected to the control input of the frequency divider 2.3 and is the first control output of the clock selector 2. The control output of the frequency divider is connected to the second control input of the phase discriminator 2.5 and is the second control output of the clock selector 2.

 The corrector 3 is designed to learn the corrected values of the given elements of the reference code sequence, shown in FIG. 13, consists of an analog nonlinear complexity node 3.1, first 3.9, second 3.8, third 3.7 and fourth 3.2 analog adders, a constant factor multiplier 3.3, first 3.6, second 3.5 and third 3.4 analog multipliers and the first 3.12, second 3.11 and third 3.10 blocks computing derivatives. The output of the analog non-linear node of complication 3.1 is connected to the second information input of the fourth analog adder 3.2. The output of the fourth analog adder 3.2 is connected to the input of the multiplier by a constant factor 3.3, the output of which is connected to the first inputs of the first 3.6, second 3.5, and third 3.4 analog multipliers, respectively. The second inputs of the first 3.6, second 3.5, and third 3.4 analog multipliers are connected to the outputs of the first 3.12, second 3.11, and third 3.10 derivative calculation blocks, respectively. The outputs of the first 3.6, second 3.5 and third 3.4 analog multipliers are connected respectively to the first inputs of the first 3.9, second 3.8 and third 3.7 analog adders, the outputs of which are respectively the first, second and third information outputs of the corrector 3. The first input of the analog non-linear complication node 3.1 connected with the first input of the third derivative calculation unit 3.10, connected to the second input of the first analog adder 3.9, is the first information input of the corrector 3. The second information input analog non-linear complication node 3.1, connected to the second input of the third derivative calculation unit 3.10 and the second input of the second analog adder 3.8, is the second information input of the corrector 3. The third input of the analog non-linear complication node 3.1, connected to the input of the second derivative calculation block 3.11, connected to the input the first block of calculation of derivatives 3.12, connected to the second input of the third analog adder 3.7, is the third information input of the corrector 3. Moreover, the third 3.10 and second 3 .11 derivative calculation units are additionally equipped with voltage reference inputs from a voltage source of positive polarity, the block diagram of which is not shown in the device.

The analog nonlinear complication unit 3.1, designed to obtain the values of the nonlinear conversion function from the analog set values of the elements of the reference code sequence, shown in FIG. 14, consists of analog multipliers 3.1.1 _1-2 and analog adders 3.1.2 _1-3 . The output of the analog multiplier 3.1.1 _{1 is} connected to the first input of the analog adder 3.1.2 ₁ , and the output of the analog multiplier 3.1.1 _{2 is} connected to the second input of the analog adder 3.1.2 ₁ , the output of which is connected to the second input of the analog adder 3.1.2 ₂ . The output of the analog adder 3.1.2 _{2 is} connected to the second input of the analog adder 3.1.2 ₃ , the output of which is the output of the analog non-linear node of complication 3.1. The first input of the analog adder 3.1.2 ₃ connected to the first input of the analog multiplier 3.1.1 ₁ is the first information input of the analog non-linear node of complication 3.1. The second input of the analog multiplier 3.1.1 ₁ , connected to the first input of the analog multiplier 3.1.1 ₂ and the first input of the analog adder 3.1.2 ₂ , is the second information input of the analog nonlinear complication node 3.1. The second input of the analog multiplier 3.1.1 ₂ is the third information input of the analog non-linear node of complication 3.1. Schemes of analog adders 3.1.2 _1-3 , which can be used in the circuit of an analog nonlinear node of complication 3.1, are known and are given, for example, in the book: A.A. Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 194, Fig. 7.6. Schemes of analog multipliers 3.1.1 _1-2 , which can be used in the circuit of an analog nonlinear node of complication 3.1, are known and are given, for example, in the book: A. A. Sikarev, ON Lebedev "Microelectronic devices for the formation and processing of complex signals." -M. : Radio and communication. 1983, p. 200, fig. 7.11.

 Schemes of analog adders 3.9, 3.8, 3.7, 3.2, which can be used in corrector 3, are known and are given, for example, in the book: A.A. Sikarev, O. N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 194, Fig. 7.6.

 The constant factor multiplier scheme 3.3 in physical essence is a non-inverting amplifier. Schemes of non-inverting amplifiers are known and are given, for example, in the book: Yu.A. Myachin "180 analog microcircuits (reference)". -M .: Patriot publishing house, MP Symbol-R and the editorial staff of Radio magazine, 1993, p. 7.

 Schemes of analog multipliers 3.4, 3.5, 3.6, which can be used in corrector circuit 3, are known and are given, for example, in the book: A. A. Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 200, fig. 7.11.

The schemes of the first 3.12, the second 3.11 and the third 3.10 of the derivative calculation blocks are shown in FIG. 15 (a), (b), (c). The first derivative calculation unit 3.12 consists of an inverter 3.12.1, the input of which is the input of the first derivative calculation unit 3.12. The output of the inverter 3.12.1 is the output of the first derivative calculation block 3.12. Inverter circuits are known and are given, for example, in the book: M.U. Bank. "Analog integrated circuits in radio equipment." -M.: Radio and communication. 1981, p. 15, fig. 2.1. The second derivative calculation unit 3.11 consists of an analog adder 3.11.1, the first input of which is the input of the second derivative calculation unit 3.11. The second input of the analog adder 3.11.1 is the input voltage reference. The output of the analog adder 3.11.1 is the output of the second derivative calculation unit 3.11. The circuit of the analog adder 3.11.1, which can be used in the second block of calculation of derivatives 3.11, is known and is given, for example, in the book: A.A. Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 194, Fig. 7.6. The third block 3.10 calculation of derivatives consists of analog adders 3.10.1 _1-2 . The first input of the analog adder 3.10.1 ₁ is the first input of the third block of the calculation of derivatives 3.10. The second input of the analog adder 3.10.1 ₁ is the input voltage reference. The output of the analog adder 3.10.1 ₁ is the second input of the analog adder 3.10.1 ₂ . The first input of the analog adder 3.10.1 ₂ is the second input of the third block of the calculation of derivatives 3.10. The output of the analog adder 3.10.1 ₂ is the output of the third block of calculation of derivatives 3.10. Schemes of analog adders 3.10.1 _1-2 , which can be used in the third block of calculation of derivatives 3.10, are known and are given, for example, in the book: A. A. Sikarev, ON Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 194, Fig. 7.6.

The first switch 4 is designed to switch the operating modes of the M-sequence synchronization device with increased complexity when receiving the corrected values of the given elements of the reference code sequence within the clock intervals and at its borders, as shown in FIG. 16, consists of the first, second and third “prohibition” switches 4.1 _1-3 and the first, second, third, fourth, fifth and sixth “permission” switches 4.2 _1-6 . The control inputs of the first, second and third “prohibition” switches 4.1 _1-3 and the first, second, third, fourth, fifth and sixth “enable” switches 4.2 _{1-6 are} connected to the control input of the first switch 4. The first information input of the first switch 4 is connected with the input of the first switch "permission" 4.2 ₁ whose output is connected with the first informational output of the first switch 4. a second data input of the first switch 4 is connected to the input of the third switch "permission" 4.2 ₃ whose output is connected with the second and formational first output switch 4. The third information input of the first switch 4 is connected to the input of the fifth switch "permission" 4.2 ₅ whose output is connected with the third informational output of the first switch 4. A fourth information input of the first switch 4 is connected to the input of the first switch "ban" 4.1 ₁ whose output is connected to the first data output of the first switch 4 and is connected to the input of the second switch "permission" 4.2 ₂ whose output is connected to the fourth output of the first information a switch 4. The fifth informational input of the first switch 4 is connected to the input of the second switch "ban" 4.1 ₂ whose output is connected to the second data output of the first switch 4 and is connected to the input of the fourth switch "permission" 4.2 _4, the output of which is connected to a fifth data output the first switch 4. The sixth information input of the first switch 4 is connected to the input of the third switch "prohibition" 4.1 ₃ , the output of which is connected to the third information output of the first switch 4 and connected to I by the sixth switch of “permission” 4.2 ₆ , the output of which is connected to the sixth information output of the first switch 4. The switches of “prohibition” 4.1 _1-3 and “permission” 4.2 _1-6 shown in FIG. 17 (a) and (b), respectively, in their physical essence correspond to the circuit of an elementary controlled switch. Schemes of controlled elementary switches are known and are given, for example, in the book of V.L. Shilo "Popular microcircuit CMOS reference", -M.: Jaguar. 1993, p. 22.

The second switch 5 is designed to switch the operating modes of the M-sequence synchronization device with increased complexity when searching for synchronization and in the generation mode, shown in FIG. 18, consists of the first, second and third "prohibition" switches 5.1 _1-3 and the first, second and third "permission" switches 5.2 _1-3 . The control inputs of the first, second and third “ban” switches 5.1 _1-3 and the first, second and third “enable” switches 5.2 _{1-3 are} connected to the control input of the second switch 5. The first information input of the second switch 5 is connected to the input of the first “ban” switch "5.1 ₁ whose output is connected with the first informational output of the second switch 5. The second information input of the second switch 5 is connected to the input of the second switch" ban "5.1 ₂ whose output is connected with the second informational output of the second commutator Ator 5. The third information input of the second switch 5 is connected to the input of the third switch "ban" 5.1 ₃ whose output is connected with the third informational output of the second switch 5. The fourth informational input of the second switch 5 is connected to the input of the first switch "permission" 5.2 ₁ whose output connected to the first information output of the second switch 5. The fifth information input of the second switch 5 is connected to the input of the second switch "permission" 5.2 ₂ , the output of which is connected to the second information output of the second switch 5. The sixth information input of the second switch 5 is connected to the input of the third “enable” switch 5.2 ₃ , the output of which is connected to the third information output of the second switch 5. “ban” switches 5.1 _1-3 and “permissions” 5.2 _1-3 , shown in FIG. 19 (a) and (b), respectively, in their physical essence correspond to the circuit of an elementary controlled switch. Schemes of controlled elementary switches are known and are given, for example, in the book of V.L. Shilo "Popular microcircuit CMOS reference", - M .: Jaguar, 1993, p. 22.

The block of analog delay lines b is designed to delay the analogue corrected values of the given elements of the reference code sequence for the duration of one sample of the received signal, shown in Fig.20, consists of the first, second and third analog delay lines 6.1 _1-3 . The control inputs of the first, second and third analog delay lines 6.1 _{1-3 are} connected to the control input of the block of analog delay lines 6. The first information input of the block of analog delay lines 6 is connected to the input of the first analog delay line 6.1 ₁ , the output of which is connected to the first information output of the block analog delay lines 6. The second information input of the analog delay line block 6 is connected to the input of the second analog delay line 6.1 ₂ , the output of which is connected to the second information output of the analog block delay lines 6. The third information input of the analog delay line block 6 is connected to the input of the third analog delay line 6.1 ₃ , the output of which is connected to the third information output of the analog delay line block 6. Schemes of analog delay lines that can be used in the block of analog delay lines 6 are known and shown, for example, in the book: I. A. Tsikin "Discrete-analogue signal processing". -M.: Radio and communication. 1982, p. 19, fig. 2.3. Given the features of the claimed device, the circuit of the analog delay line 6.1 can be implemented as shown in Fig.21. The analog delay line contains a recording amplifier (US) 6.1.1, a controlled switch (UP) 6.1.2 and a reading amplifier (US) 6.1.3. The information input of the recording amplifier 6.1.1 is the input of the analog delay line 6.1, and the output is connected to the information input of the managed switch UP 6.1.2, the control input of which is the control input of the analog delay line 6.1. The output of the managed switch in parallel is connected to the first contact of the capacitor and to the input of the read amplifier 6.1.3, the output of which is the information output of the analog delay line 6.1. The second contact of the capacitor is connected to the ground bus.

The block of quantizers 7 is designed to quantize the analogue corrected values of the given elements of the reference code sequence at level 0 and 1, shown in Fig. 22, consists of the first, second, third, fourth, fifth and sixth quantizers 7.1 _1-6 . The first information input of the quantizer block 7 is connected to the input of the first quantizer 7.1 ₁ , the output of which is connected to the first information output of the quantizer block 7. The second information input of the quantizer block 7 is connected to the input of the second quantizer 7.1 ₂ , the output of which is connected to the second information output of the quantizer 7. The third information input quantizers 7 connected to an input of the third unit 7.1 quantizer ₃ whose output is connected to the third data output unit 7. The fourth quantizers and formational quantizers unit 7 is input is connected to the input of the fourth 7.1 quantizer _4, the output of which is connected to a fourth data output unit 7. The quantizers fifth information input unit quantizers 7 connected to the input of the fifth quantizer 7.1 ₅ whose output is connected to a fifth data output unit 7. The sixth quantizers quantizers information input 7 connected to an input unit of the sixth quantizer 7.1 _6, whose output is connected to the sixth output information quantizers unit 7. Furthermore, the first WTO second, third, fourth, fifth and sixth quantizers 7.1 _1-6 additionally provided with a reference voltage inputs. By their physical nature, the first, second, third, fourth, fifth and sixth quantizers 7.1 _1-6 are comparators that respond to the difference of two signals, one of which is a reference. Comparator circuits that can be used in the block of quantizers 7 are known and shown, for example, in the book: M.U Bank. "Analog integrated circuits in radio equipment." -M.: Radio and communication. 1981, p. 26, fig. 2.19 (a).

The block of digital delay lines 8 is designed to delay the quantized corrected values of the specified elements of the reference code sequence for the duration of one element of the received signal, shown in Fig.23, consists of the first, second and third digital delay lines 8.1 _1-3 . The control inputs of the first, second and third digital delay lines 8.1 _{1-3 are} connected to the control input of the block of digital delay lines 8. The first information input of the block of digital delay lines 8 is connected to the input of the first digital delay line 8.1 ₁ , the output of which is connected to the first information output of the block digital delay line 8. The second information input of the digital delay line unit 8 is connected to the input of a second digital delay line 8.1 _2, the output of which is connected to the output of the second information block of digital delay lines 8. rety information input block of digital delay lines 8 connected to the third input of the digital delay line 8.1 _3, the output of which is connected to the third data output line digital delay unit 8. The digital delay line 8.1 is inherently clocked D-flip-flop, an inverse output of which the device does not is used. Schemes of digital delay lines 8.1, which can be used in the block of digital delay lines 8, are known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 26, fig. thirteen.

The control unit 9 is designed to generate a control action on the start of the reference signal generator, shown in Fig.24, consists of the first, second and third adders modulo 2 9.1 _1-3 , three-input element OR-NOT 9.2, serial register 9.3, decoder 9.4. The outputs of the first, second and third adders modulo 2 9.1 _{1-3 are} connected respectively to the first, second and third inputs of the three-input element OR NOT 9.2, the output of which is connected to the information input of the serial register 9.3. The outputs of the serial register 9.3 from the first to the 2nth are connected to the corresponding inputs of the decoder 9.4. The output of the decoder 9.4 is the control output of the control unit 9. The control input of the serial register 9.3 is the control input of the control unit 9. The first inputs of the first, second and third adders modulo 2 9.1 _1-3 are respectively the first, second and third information inputs of the control unit 9. The second inputs of the first, second and third adders modulo 2 9.1 _1-3 are, respectively, the fourth, fifth and sixth information inputs of the control unit 9. Scheme modulo-2 adders _1-3 9.1, which may be IP Use This Criterion 9 in the control unit, are known and are shown, for example, in the book: L. Maltsev, EM Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M. : Radio and communication. 1986, p. 22, fig. 10. The scheme of the three-input element OR-NOT 9.2 is presented in Fig.25. The first input of a three-input element OR NOT 9.2. connected to the first input of the OR element 9.2.1. The second input of the three-input OR-NOT 9.2 element is connected to the second input of the OR-9.2.1 element, the output of which is connected to the first input of the OR-NOT 9.2.2 element. The third input of the three-input OR-NOT 9.2 element is connected to the second input of the OR-NOT 9.2.2 element, whose inverse output is the output of the three-input OR-NOT 9.2 element. The circuit of the OR 9.2.1 element, which can be used in the three-input element OR-NOT 9.2, is known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 21, fig. 9 (b). The circuit of the OR-NOT 9.2.2 element, which can be used in the three-input OR-NOT 9.2 element, is known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." - M .: Radio and communications. 1986, p. 21, fig. 9 (e). Serial register 9.3, the circuit of which is shown in FIG. 26, consists of 2n digital delay lines 9.1. The information input of serial register 9.3 is connected to the input of the first digital delay line 9.1 ₁ , the output of which is connected to the input of the i-th digital delay line 9.1 _i , where i = 2 ... 2n, and the first output of the serial register 9.3. The output of the 2nd digital delay line 9.1 _{2n is} connected to the 2n output of the serial register 9.3. The control input of the serial register 9.3 is connected to the control inputs of all 2n digital delay lines 9.1. The digital delay line 9.1 is essentially a clocked D-flip-flop, the inverse output of which is not used in the device. Schemes of digital delay lines 9.1, which can be used in serial register 9.3, are known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 26, fig. thirteen.

The generator of reference code sequences 10 is designed to generate a reference code sequence using the analog values of its elements, shown in Fig. 28, consists of n analog delay lines 10.1 _1-n , n + 1 multipliers by a constant factor of 10.2 _{1- (n + 1)} and n-1 feedback function calculators 10.3 _{1- (n-1)} . The control input of the generator of reference code sequences 10 is connected to the control inputs of n analog delay lines 10.1 _1-n . The outputs of all n analog delay lines 10.1 _{1-n are} connected to the inputs of the i-th multipliers by a constant factor of 10.2 _i , where i = 2. (n + 1), and the j-th inputs of the analog delay lines 10.1 _j , where j = 2. ..n. The outputs of the jth multipliers by a constant factor of 10.2 _{j are} connected to the second inputs of the corresponding calculators of the feedback function 10.3. The output of the (n + 1) th multiplier by a constant factor of 10.2 is connected to the first input of the (n-1) th calculator of the feedback function 10.3. The outputs, starting from the (n-1) -th calculator of the feedback function 10.3 and up to the first, are connected in series with the first inputs of the corresponding calculators of the feedback function 10.3. The output of the first calculator of the feedback function 10.3 is connected to the input of the first multiplier by a constant factor 10.2, the output of which is connected to the input of the first analog delay line 10.1. Moreover, the outputs of the predefined analog delay lines 10.1 are connected to the corresponding multipliers by a constant factor of 10.2 and are, respectively, the first, second, and third information outputs of the reference code sequence generator 10. The inputs of the subsequent delays of the predefined analog delay lines 10.1 are, respectively, the first, second, and third information inputs generator of reference code sequences 10. Schemes of analog delay lines 10.1 that can be used in generator of the reference code sequences 10 are known and are shown, for example, in the book: IA Tsikin "Discrete-analog signal processing". -M.: Radio and communication. 1982, p. 19, Fig. 2.3. Taking into account the features of the claimed device, the analog delay line circuit 10.1 can be implemented as shown in Fig.21. Constant factor multiplier schemes 10.2 in physical essence are non-inverting amplifiers. Schemes of non-inverting amplifiers are known and are given, for example, in the book: Yu.A. Myachin "180 analog microcircuits (reference)". -M. : publishing house Patriot, MP Symbol-R and the editors of the journal Radio, 1993, p. 7. The circuit of the feedback function calculator 10.3 shown in FIG. 29 consists of the first and second analog adders 10.3.1 _1-2 , an analog multiplier 10.3.2 and a constant factor multiplier 10.3.3.

Schemes of analog adders 10.3.1 _1-2 , which can be used in the calculator of the feedback function 10.3, are known and are given, for example, in the book: A.A. Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 194, Fig. 7.6.

 The circuit of the analog multiplier 10.3.2, which can be used in the calculator of the feedback function 10, is known and is given, for example, in the book: A.A. Sikarev, O.N. Lebedev "Microelectronic devices for the formation and processing of complex signals." -M.: Radio and communication. 1983, p. 200, fig. 7.11.

 The constant factor multiplier scheme 10.3.3 in physical essence is a non-inverting amplifier. Schemes of non-inverting amplifiers are known and are given, for example, in the book: Yu.A. Myachin "180 analog microcircuits (reference)". -M .: Patriot publishing house, MP Symbol-R and the editorial staff of Radio magazine, 1993, p. 7.

The reference signal generator 11 is designed to generate an M-sequence synchronous with the received one, shown in FIG. 30, consists of n digital delay lines 11.1 _1-n , n + 1 multipliers by a constant factor of 10.2 _{1- (n + 1)} and n- 1 adders modulo 2 10.3 _{1- (n-1)} . The control input of the reference code sequence generator 11 is connected to the control inputs of all n digital delay lines 11.1 _1-n . The outputs of all n digital delay lines 11.1 _{1-n are} connected to the inputs of the i-th multipliers by a constant factor 11.2 _i , where i = 2 ... (n + 1), and the j-th inputs of the digital delay lines 11.1 _j , where j = 2 ... n. The outputs of the jth multipliers by a constant factor of 11.2 _{j are} connected to the second inputs of the corresponding adders modulo 2 11.3. The output of the (n + 1) th multiplier by a constant factor of 11.2 is connected to the first input of the (n-1) th adder modulo 2 11.3. The outputs, starting from the (n-1) -th adder modulo 2 11.3 and up to the first are connected in series with the first inputs of the corresponding adders modulo 2 11.3. The output of the first adder modulo 2 11.3 is connected to the input of the first multiplier by a constant factor 11.2, the output of which is connected to the input of the first digital delay line 11.1. Moreover, the outputs of the predefined digital delay lines 11.1 are connected to the respective multipliers by a constant factor 11.2 and are respectively the first, second and third information outputs of the reference signal generator 11. The inputs of the followers of the predefined digital delay lines 11.1 are, respectively, the first, second and third information inputs of the generator reference signal 11. Schemes of digital delay lines 11.1 are essentially clocked D-flip-flops, whose inverse outputs are in the device They are not used. Schemes of digital delay lines 11.1, which can be used in the reference signal generator 11, are known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 26, fig. 13. The scheme of the multiplier by a constant factor of 11.2 in physical essence is a non-inverting amplifier. Schemes of non-inverting amplifiers are known and are given, for example, in the book: Yu.A. Myachin "180 analog microcircuits (reference)". - M.: publishing house Patriot, MP Symbol-R and the editors of the journal Radio, 1993, p. 7. Adder circuits modulo 2 11.3, which can be used in the reference signal generator 11, are known and shown, for example, in the book: L. A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 22, fig. ten.

Digital nonlinear complexity node 12 is designed to form an M-sequence with increased complexity synchronous with the received one, shown in Fig. 31, consists of the first and second inverters 12.1 _1-2 and the first, second and third elements of NAND 12.2 _1-3 . The first input of the digital nonlinear complexity node 12 is connected to the input of the first inverter 12.1 ₁ , the inverse output of which is connected to the first input of the first element AND-NOT 12.2 ₁ . The second input of the digital nonlinear complexity node 12 is connected to the second input of the first inverter 12.1 ₁ and to the input of the second inverter 12.2 ₂ . The third input of the digital nonlinear complexity node 12 is connected to the second input of the second inverter 12.2 ₂ , the inverse output of which is connected to the second input of the third AND-NOT element 12.2 ₃ , the inverse output of which is the output of the device. Circuits of inverters 12.1 _1-2 that can be used in a digital non-linear node of complication 12 are known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 21, fig. 9 (c). Schemes of AND-NOT 12.2 _1-3 elements that can be used in a digital nonlinear complexity node 12 are known and shown, for example, in the book: L.A. Maltseva, E.M. Fromberg, BC Yampolsky. "Fundamentals of digital technology." -M.: Radio and communication. 1986, p. 21, fig. 9 (d).

 The claimed device synchronization of the M-sequence with increased complexity works as follows. The mixture of signal and noise, Fig. 7 (b), is fed to the receiving information input of the device shown in FIG. 11. First, the signal is fed in parallel to the receiving information input of the sampler 1 and the clock selector 2. In the clock selector 2 shown in FIG. 12, using the phase discriminator 2.5, the repetition period of the information signals is determined, and at the output of the control element 2.2, gating pulses with the clock frequency of the information signal are obtained, FIG. 7 (c). This output is the first control output of the clock frequency isolator 2. And at the output of the frequency divider 2.3 with a division factor of k, gating pulses are obtained with a frequency k times higher than the clock frequency of the information signal, Fig. 7 (g). This output is the second control output of the clock isolator 2. In addition, the signal and noise mixture from the input of the M-sequence synchronization device is supplied to the sampler 1. The control input of the sampler 1 receives gating pulses with a frequency k times the clock frequency of the information signal. In the sampler 1 receive sampled samples of the information signal with a frequency of k times higher than the clock frequency of the information signal, Fig.7 (d). From the output of the sampler 1, the sampled samples of the information signal are fed to the receiving information input of the corrector 3, FIG. thirteen.

 In the case of initial synchronization in the analog delay lines 10.1 of the reference code sequence generator 10, Fig. 28, arbitrary non-zero analog values of the initial conditions in the definition area from 0 to 1 must be recorded or the values remaining from the previous communication session can be found.

Under the influence of a gating pulse with a frequency f _t sprinkling on the control input of the generator of reference code sequences 10, Fig. 28, and on the control inputs of each analog delay line 10.1, its contents are read and simultaneously fed to the information input of the subsequent analog delay line 10.1 and to the input the corresponding constant factor multiplier 10.2. The contents of the analog delay line 10.1 _{n is} read and fed to the input of the multiplier by a constant factor of 10.2 _{n + 1} . In the multiplier by a constant factor of 10.2, the signal is amplified by a coefficient determined by the structure of the generating polynomial, and can take values 0 or 1. If the coefficient of the generating polynomial is equal to unity, then feedback from the corresponding analogue delay line exists, if it is equal to zero, then feedback from the corresponding delay line does not exist. From the output of the multiplier to a constant factor of 10.2 _{n + 1, the} content goes to the second information input of the calculator of the feedback function 10.3 _n-1 , FIG. 29, the first information input of which receives a signal from the multiplier by a constant factor of 10.2 _n . From the output of the calculator of the feedback function 10.3 _n-1 , FIG. 29, the signal is fed to the second information inputs of subsequent calculators of the feedback function 10.3, Fig. 29, the first inputs of which receive a signal from the corresponding multipliers by a constant factor of 10.2. From the output of the calculator of the feedback function 10.3 ₁ , FIG. 29, the signal is fed to the input of the multiplier by a constant factor 10.2 ₁ , the output of which is fed to the information input of the analog delay line 10.1 ₁ . As a result of a shift in the analog delay lines 10.1, multiplication by the corresponding coefficient in the multiplier by a constant factor of 10.2, and actions in the calculator of the feedback function 10.3, a value generated according to the recursive rule for generating the M-sequence is obtained.

Moreover, the values of the specified analog delay lines 10.1 are read and simultaneously fed to the input of the corresponding multiplier by a constant factor of 10.2 and to the first, second and third information outputs of the reference code sequence generator 10, FIG. 28. Thus, at the first, second and third information outputs of the reference code sequence generator 10, FIG. 28, the predicted values of the information signal are received, the first sample of which is sampled at the information input of the corrector 3, FIG. 13. From the first, second and third information outputs of the reference code sequence generator 10, FIG. 28, the values of the specified analog delay lines 10.1 are received simultaneously at the first, second and third information inputs of the first switch 4, FIG. 16, and to the first, second and third information inputs of the quantizer block 7, FIG. 22. In the block of quantizers 7, Fig.22, the values of the specified analog delay lines 10.1 are supplied to the corresponding information inputs of quantizers 7.1 _1-3 , equipped with additional inputs of the reference voltage, and from the output of quantizers 7.1 _1-3 are received respectively at the first, second and third information outputs of the block of quantizers 7, Fig.22. From the first, second and third information outputs of the quantizer block 7, FIG. 22, the quantized values of the given analog delay lines 10.1 are supplied to the first, second and third information inputs of the digital delay line unit 8, FIG. 23, which are connected to respective data inputs of digital delay lines _1-3 8.1, which produces delay signals to the duration of one cycle of the received signal.

Under the influence of a gating pulse with a frequency f _t supplied to the control input of the block of digital delay lines 8, Fig.23, and to each control input of the digital delay line 8.1 _1-3 , quantized values are read and fed to the first, second and third information inputs of the block digital delay lines 8, FIG. 23. From the first, second and third information outputs of the block of digital delay lines 8, Fig.23, the quantized values are respectively received at the first, second and third information inputs of the control unit 9, Fig.24.

Under the influence of a gating pulse with a frequency f _t supplied to the control input of the first switch 4, FIG. 16, and to the control inputs of all “prohibition” switches 4.1 _1-3 and “permissions” 4.2 _1-6 , the contacts of the “prohibition” switches 4.1 _1-3 open and the contacts of the “permission” switches 4.2 _1,3,5 , and 4.2 are closed _2,4,6 . As a result, the first, second, and third information inputs of the first switch 4, FIG. 16 are connected respectively to the first, second and third information outputs of the first switch 4, FIG. 16, and the fourth, fifth and sixth information inputs of the first switch 4, FIG. 16 are connected respectively to the fourth, fifth and sixth information outputs of the first switch 4, FIG. 16.

From the first, second and third information outputs of the first switch 4, FIG. 16, the predicted values of the information signal, the first discretized sample of which was received at the receiving information input of the corrector 3, FIG. 13, respectively, are supplied to the first, second and third information inputs of the corrector 3, FIG. 13. In the analog non-linear node of complication 3.1, FIG. 14, the analog value of the nonlinear conversion function is calculated from the analog values received at the first, second, and third inputs of the analog nonlinear complexity node 3.1. FIG. 14. In the first, second and third blocks for calculating derivatives 3.12 of FIG. 15 (a), 3.11 of FIG. 15 (b), 3.10 of FIG. 15 (c), the value of the derivative of the analog function of the nonlinear transformation is calculated from the corresponding predetermined analog values received at the first, second and third information inputs of the corrector 3, FIG. 13. In analog adder 3.2, the information signal received at the first input of analog adder 3.2 is subtracted from the value of the first sampled sample, the values of the nonlinear conversion function from the analog values received at the first, second and third inputs of the analog non-linear node of complication 3.1, FIG. 14. From the output of analog adder 3.2, the signal is fed to the input of the multiplier by a constant factor of 3.3 with a gain of C. The experiments have shown that it is advisable to choose the value of the coefficient C from 0 to 1. From the output of the multiplier to a constant factor of 3.3, the signal is fed to the first inputs in parallel analog multipliers 3.6, 3.5, 3.4 in the corresponding branch of the adjustment. The second inputs of the analog multipliers 3.6, 3.5, 3.4 receive a signal from the corresponding unit for computing derivatives 3.12, 3.11, 3.10. From the output of the analog multipliers 3.6, 3.5, 3.4, the signal enters the first input of the corresponding analog adder 3.9, 3.8, 3.7, the second input of which sprinkles the predicted value of the information signal from the first, second, and third information inputs of the corrector 3, FIG. 13. The outputs of the analog adders 3.9, 3.8, 3.7 are respectively the first, second and third information outputs of the corrector 3, FIG. 13, Corrected signals from the first, second and third information outputs of the corrector 3, FIG. 13, are fed to the first, second and third information inputs of the block of analog delay lines 6, FIG. From the first, second and third information inputs of the block of analog delay lines 6, FIG. 20, the corrected signals are fed to the information inputs of the corresponding analog delay lines 6.1 _1-3 , FIG. 21, where the corrected signals are delayed for the duration of the duration of one sample of the received signal. Under the influence of a gating pulse with a frequency k times higher than the clock frequency of the received signal, which is fed to the control input of the block of analog delay lines 6, FIG. 20, and for each control input of the analog delay lines 6.1, Fig.21, the corrected signals are read and fed to the first, second and third information outputs of the block of analog delay lines 6, Fig.20. Corrected signals from the first, second and third information outputs of the block of analog delay lines 6, Fig. 20, are fed to the fourth, fifth and sixth information inputs of the first switch 4, Fig. 16. Upon receipt of subsequent sampled samples of the signal, starting from the second to the k-th, gating pulses with a frequency equal to the clock frequency of the information signals to the control input of the first switch 4, FIG. 16 do not arrive. At the same time, the contacts of the "permission" switches 4.2 _1-6 open, the contacts of the "prohibition" switches 4.1 _{1-3 are} closed. From the fourth, fifth and sixth information inputs of the first switch 4, FIG. 16, the corrected signals through the closed contacts of the “prohibition” switches 4.1 _1-3 are received respectively at the first, second and third information outputs of the first switch 4, FIG. 16. The corrected signals from the first, second and third information outputs of the first switch 4, FIG. 16 are received respectively at the first, second and third information inputs of the corrector 3, FIG. 13, where the corrected values are re-adjusted taking into account the subsequent sample of the received signal. Thus, the correction of the predicted values of the information signal is carried out taking into account the discretized samples of the received signal k times. Corrected signals at the k-th sampled sample of the received signal through the closed contacts of the “resolution” switches 4.2, _2,4,6 are fed to the fourth, fifth and sixth information outputs of the first switch 4, FIG. 16. From the fourth, fifth and sixth information outputs of the first switch 4, FIG. 16, the corrected signals arrive simultaneously at the fourth, fifth and sixth information inputs of the quantizer unit 7, FIG. 22, and at the first, second and third information inputs of the reference code sequence generator 10, FIG. 28. In the generator of reference code sequences 10, FIG. 28, a reference code sequence is formed from the corrected signals, the values of the elements of which are adjusted at each clock cycle of the received signal. In the block of quantizers 7, FIG. 22, the corrected signals are fed to the information inputs of the corresponding quantizers 7.1 _3-6 equipped with additional inputs of the reference voltage, and from the output of the quantizers 7.1 _3-6 of the quantizer unit 7, Fig. 22, are simultaneously transmitted to the fourth, fifth and sixth information inputs of the control unit 9 , Fig.24, and the first, second and third information inputs of the second switch 5, Fig. 18.

In the control unit 9, Fig.24, the summation modulo 2 is carried out in adders 9.1 _{1-3 of} quantized delayed signal values received at the first, second and third information inputs, with quantized corrected signal values received respectively at the fourth, fifth and sixth information the inputs of the control unit 9, Fig.24. The outputs of the adders modulo 2 9.1 _{1-3 are} connected to the first, second and third inputs of the three-input element OR NOT 9.2, Fig.25. In this case, the signal at the output of the three-input element OR-NOT 9.2, Fig.25, will appear only when the result of the summation modulo 2 in each branch will be zero. That is, if the predicted signal values coincide with the corrected ones. From the output of the three-input element OR NOT 9.2, FIG. 25, the signal is input to the serial register 9.3, FIG. 26, length 2n. Under the influence of a gating pulse with a frequency f _t supplied to the control input of the departure unit 9, FIG. 24, and to the control input of the serial register 9.3, Fig. 26, 2n long, the contents of the digital delay line 9.3.1 _1-2n are simultaneously overwritten into the subsequent digital delay line 9.3.1 _1-2n and the contents of each digital delay line 9.3.1 are read _1-2n . In this case, the read values are sent to the first, second, ..., 2n-th outputs of the serial register 9.3, Fig.26. The read values go to the first, second, ... , 2n-th inputs of the decoder 9.4, Fig.27. The decoder 9.4, Fig.27, consists of 2n-1 elements And 9.4.1 _{1- (2n-1)} . Thus, the control signal at the output of the decoder 9.4, Fig. 27, and therefore, the control unit 9, Fig. 24, will occur when, on the digital delay lines 9.3.1 _{1-2n of the} serial register 9.3, _Fig . 26, 2n long units will be recorded. That is, when the predicted signal values coincide with those corrected for a duration of 2n clock cycles of the received signal.

In the absence of a control signal sprinkled on the control input of the second switch 5, FIG. 18, and to the control inputs of each switch of the "ban" 5.1 _1-3 and "permission" 5.2 _1-3 , the contacts of the switches of the "ban" 5.1 _{1-3 are} closed and the contacts of the switches of the "permission" 5.2 _{1-3 are opened} . , the second and third information inputs of the second switch 5, Fig. 18, are switched respectively to the first, second and third information outputs of the second switch 5, Fig. 18. The quantized corrected values of the received signal are transmitted simultaneously to the first, second and third information inputs of the reference signal generator 11, figure 3 0, and to the first, second and third inputs of the digital nonlinear complication node 12, Fig. 31, the output of which is the output of the synchronization device.

 The structure of the reference signal generator 11, Fig. 30, completely coincides with the structure of the reference code sequence generator 10, Fig. 28, except that the quantized corrected values of the received signal are stored in the reference signal generator 11, Fig. 30.

Under the influence of a control signal supplied to the control input of the second switch 5, FIG. 18, the contacts of the “permission” switches 5.2 _{1-3 are} closed and the contacts of the “prohibition” switches 5.1 _{1-3 are opened} . In this case, the fourth, fifth and sixth information inputs of the second switch 5, FIG. 18 are connected respectively to the first, second and third information outputs of the second switch 5, FIG. 18.

 The reference signal generator 11, Fig. 30, goes into standalone mode and generates the SRP synchronous with the SRP on the transmitting side, and the SRP PS from the output of the digital nonlinear complexity node 12, Fig. 31, will be synchronous with the received SRP PS.

 In addition, the receipt of the corrected signal values taking into account the received sampled samples does not stop and is performed continuously in order to obtain the predicted signal values to reduce the time when re-entering the synchronization.

Claims (12)

 1. The method of synchronizing the M-sequence, which consists in receiving a pseudo-random sequence, generating a reference code pseudo-random sequence, reading its values, generating a control action and generating a pseudo-random sequence synchronous with the received, characterized in that a pseudo-random sequence of increased complexity is formed, formed by non-linear transformation for a given discrete function of a pseudo-random sequence based on the character of an n-order eristic polynomial, where n ≥ 3, discretize its elements with a frequency k times the clock frequency of the received pseudo-random sequence of increased complexity, where k ≥ 2, and the reference code pseudo-random sequence is formed in analog form, and only the values of predefined elements are read reference code pseudo-random sequence, then they are quantized at levels 0 and 1 and delayed for the duration of one element of the pseudo-random sequence of increased complexity spans, after which the read values of each of the given elements of the reference code pseudo-random sequence are adjusted taking into account the first discretized sample of the received element of the pseudo-random sequence of increased complexity, the corrected values of the given elements of the reference code pseudo-random sequence are delayed for the duration of one sampled sample of the received element of the pseudo-random sequence of increased complexity, then they are re-adjusted with taking into account the value of the subsequent discretized reference of the received element of the pseudo-random sequence of increased complexity, moreover, the correction and delay of the corrected values are repeated k times, then they are quantized at levels 0 and 1 and stored by n clock cycles, and, in addition, from the corrected k times values of the reference code pseudo-random sequence re-form the reference code pseudo-random sequence, the values of the predefined elements of which are adjusted at the next clock second pseudo-random sequence of high complexity.  2. The method according to claim 1, characterized in that the reference code pseudo-random sequence is formed according to a recursive rule for generating an M-sequence according to a given characteristic n-order polynomial, where n ≥ 3, in which non-zero analog values of its elements are used, and the summation operation is module 2 of two variables x and y is replaced by the operation x + y - 2xy.  3. The method according to claim 1, characterized in that for the correction of the read values of the predefined elements of the reference code pseudo-random sequence, they are read over the duration of one sample of the received element of the pseudo-random sequence of increased complexity, they are nonlinearly transformed according to the given analog function, and then the derivatives of the given nonlinear conversion functions by the values of predefined elements of the reference code pseudo-random sequence and, counted during the duration of one sampled sample of the received element of a pseudo-random sequence of increased complexity, then from the value of the current sampled sample of a pseudo-random sequence of increased complexity, the value of the generated sampled reference of the reference code pseudo-random sequence of increased complexity is subtracted and multiplied by a given weight coefficient, then parallelly multiplied by the values of the derivatives for each value pre-ass data elements of the reference code pseudo-random sequence obtained earlier, and summed with the corresponding values of the predefined elements of the reference code pseudo-random sequence. 4. The method according to claim 1, characterized in that the analog values of the predefined elements of the reference code pseudo-random sequence and the adjusted values of the specified elements of the reference code pseudo-random sequence obtained on the k-th sample of the received element of the pseudo-random sequence of increased complexity are quantized according to the rule
x _c = 1 if x _a ≥ 0.5;
x _c = 0 if x _a <0.5.  5. The method according to claim 1, characterized in that the elements of a pseudo-random sequence of increased complexity synchronous with the received one are generated by nonlinear conversion of the given discrete values of the elements of the pseudo-random sequence generated on the basis of the characteristic polynomial of the n-th order, where n ≥ 3, from the quantized corrected values of the given elements of the reference code pseudo-random sequence.  6. The method according to claim 1, characterized in that the control action is formed if, for a duration of 2n cycles, all the quantized values of the given elements of the reference code pseudo-random sequence are equal to their adjusted quantized values of the given elements of the reference code pseudo-random sequence.  7. An M-sequence synchronization device comprising a first switch, a reference code sequence generator, a control unit, a reference signal generator, characterized in that a sampler, a clock selector, a corrector, a quantizer block, a second switch, an analog block and a block of digital lines are additionally introduced delays, digital nonlinear complication node, the receiving information input of the sampler is connected to the input of the clock selector and is the input of the device, the first control the stroke of the clock divider is connected to the control inputs of the first switch, the block of digital delay lines, the control unit, the generator of the reference code sequences, the reference signal generator, the second control output of the clock separator is connected to the control inputs of the sampler and the block of analog delay lines, the output of the sampler is connected to the receiver the information input of the corrector, the first, second and third information inputs of the corrector are connected respectively to the first, second and third inputs formation outputs of the first switch, the first, second and third information outputs of the corrector are connected respectively to the first, second and third information inputs of the block of analog delay lines, the outputs of which are connected respectively to the fourth, fifth and sixth information inputs of the first switch, the first, second and third outputs of the generator reference code sequences are connected respectively to the first, second and third information inputs of the first switch and to the first, second and third input Am of the quantizer block, the fourth, fifth and sixth information outputs of the first switch are connected respectively to the fourth, fifth and sixth inputs of the quantizer block, the first, second and third outputs of the quantizer block are connected respectively to the first, second and third inputs of the block of digital delay lines, the outputs of which are connected respectively, to the first, second and third information inputs of the control unit, the control output of the control unit is connected to the control input of the second switch, the fourth, fifth and the outputs of the quantizer block are connected respectively to the fourth, fifth and sixth information inputs of the control unit and, respectively, with the first, second and third inputs of the second switch, the first, second and third outputs of the reference signal generator are connected respectively to the fourth, fifth and sixth inputs of the second switch, the first, the second and third outputs of the second switch are connected respectively to the first, second and third information inputs of the reference signal generator and are connected respectively to the first, second the first and third inputs of a digital nonlinear complication node, the output of which is the output of the device.  8. The device according to claim 1, characterized in that the corrector consists of an analog non-linear complication node, the first, second, third and fourth analog adders, a constant factor multiplier, the first, second and third multipliers and the first, second and third derivatives calculation blocks , the output of the analog nonlinear complexity node is connected to the second information input of the fourth analog adder, the output of which is connected to the input of the multiplier by a constant factor, the output of which is connected to the first inputs with respectively, of the first, second, and third multipliers, the second inputs of which are connected to the outputs of the first, second, and third derivatives, respectively, the outputs of the multipliers are connected respectively to the first inputs of the first, second, and third analog adders, the outputs of which are the first, second, and third information outputs, respectively of the corrector, the first input of the analog nonlinear complexity node connected to the first input of the third derivative calculation unit, connected to the input of the first tax adder is the first information input of the corrector, the second information input of the analog nonlinear complication node connected to the second input of the third derivative calculation unit and the input of the second analog adder is the second information input of the corrector, the third input of the analog nonlinear complication node connected to the input of the second calculation unit derivatives, connected to the input of the first block of the calculator of derivatives, connected to the second input of the third analog adder, is provided by the third information input of the corrector, and the third and second blocks for calculating derivatives are additionally equipped with voltage reference inputs.  9. The device according to claim 1, characterized in that the reference code sequence generator consists of n analog delay lines, n + 1 constant factor multipliers and n - 1 feedback function calculators, the control input of the reference code sequence generator is connected to the control inputs n analog delay lines, the outputs of all n analog delay lines are connected to the inputs of the i-th multipliers by a constant factor, where i = 2 ... (n + 1), and the j-th inputs of the analog delay lines, where j = 2 ... n, outputs of j-th constant multipliers the multiplier is connected to the second inputs of the corresponding calculators of the feedback function, the output of the n + 1th multiplier by a constant factor is connected to the first input of the n - 1st calculator of the feedback function, the output of the n - 1st calculator of the feedback function and is connected to the first in series with the first inputs of the corresponding feedback function calculators, the output of the first feedback function calculator is connected to the input of the first multiplier by a constant factor, the output of which is connected to the input of the first analog line delays, and the outputs of predefined analog delay lines are connected to the corresponding multipliers by a constant factor and are respectively the first, second and third information outputs of the reference code sequence generator, the inputs of subsequent analog delay lines are the first, second and third information inputs of the reference code sequence generator.  10. The device according to claim 1, characterized in that the control unit consists of the first, second and third adders modulo 2, the element OR is NOT, the shift register, the element And, the outputs of the first, second and third adders modulo 2 are connected respectively to the first second and third inputs of the OR element are NOT, the output of which is connected to the information input of the shift register, the outputs of which from the first to the 2nd are connected to the corresponding inputs of the element And, the output of which is the control output of the control unit, the control input of the shift register ha is the control input of the control unit, the first inputs of the first, second and third adders modulo 2 are respectively the first, second and third information inputs of the control unit, the second inputs of the first, second and third adders modulo 2 are the fourth, fifth and sixth information inputs control unit.  11. The device according to claim 1, characterized in that the first switch consists of the first, second and third "prohibition" switches and the first, second, third, fourth, fifth and sixth "permission" switches, the control inputs of the first, second and third switches "prohibition" and the first, second, third, fourth, fifth and sixth "enable" switches are connected to the control input of the first switch, the first information input of the first switch is connected to the input of the first "enable" switch, the output of which is connected from the first m information output of the first switch, the second information input of the first switch is connected to the input of the third "enable" switch, the output of which is connected to the second information output of the first switch, the third information input of the first switch is connected to the input of the fifth "enable" switch, the output of which is connected to the third information the output of the first switch, the fourth information input of the first switch is connected to the input of the first "ban" switch, the output of which is connected to the first the information output of the first switch and connected to the input of the second "enable" switch, the output of which is connected to the fourth information output of the first switch, the fifth information input of the first switch is connected to the input of the second "prohibition" switch, the output of which is connected to the second information output of the first switch and connected to the input of the fourth switch "permission", the output of which is connected to the fifth information output of the first switch, the sixth information input of the first switch and connected to the input of the third “ban” switch, the output of which is connected to the third information output of the first switch and connected to the input of the sixth “enable” switch, the output of which is connected to the sixth information output of the first switch.  12. The device according to claim 1, characterized in that the second switch consists of the first, second and third switches "prohibition" and the first, second and third switches "permission", the control inputs of the first, second and third switches "prohibition" and the first, the second and third “enable” switches are connected to the control input of the second switch, the first information input of the second switch is connected to the input of the first “ban” switch, the output of which is connected to the first information output of the second switch, the second information the input of the second switch is connected to the input of the second “ban” switch, the output of which is connected to the second information output of the second switch, the third information input of the second switch is connected to the input of the third “ban” switch, the output of which is connected to the third information output of the second switch, the fourth information input the second switch is connected to the input of the first "enable" switch, the output of which is connected to the first information output of the second switch, the fifth information the first input of the second switch is connected to the input of the second switch "permission", the output of which is connected with the second informational output of the second switch, the sixth informational input of the second switch is connected to the input of the third switch "permission", the output of which is connected with the third informational output of the second switch.

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