RU2038703C1 - Digital receiver of digital signals with rotating phase - Google Patents

Abstract

FIELD: electric communications. SUBSTANCE: device has band- pass filter 1, automatic gain control amplifier 2, analog-to-digital converter 3, multipliers 4 and 5, oscillator 6, low-pass filters 7-10, adders 11 and 12, phase correction signal generator 13, commutation unit 14, linear frequency modulation converter 15, synchronization signals detection unit 16, adaptive corrector 17, phase shifter 18, decision making unit 19, decoder 20, unscrambling unit 21, phase manipulation unit 22, phase error calculation unit 23, carrier phase tuning unit 24, carrier commutation unit 25. EFFECT: increased functional capabilities. 5 cl, 4 dwg

Description

 The invention relates to telecommunications and can be used to receive discrete signals transmitted over communication channels at a speed of 2400 bit / s.

 Closest to the invention in technical essence is a digital signal receiving device comprising an error calculation unit, an AGC amplifier, an ADC phase shifter, an adaptive corrector, a level control unit, a demodulation and phase compensation unit, a decision unit and a decoder.

 The disadvantage of the receiver of the digital adaptive signal conversion device is the impossibility of coherent reception of discrete signals with a "rotating phase" used in data transmission at a speed of 2400 bit / s.

 The objective of the invention is to expand the functionality when working at a speed of 2400 bps.

 Figure 1 shows the structural electrical circuit of a digital receiver; in FIG. 2 diagram of a block for selecting clock signals; figure 3 diagram of a block allocation clock frequency; on figa and b circuit switching carrier and phase manipulator, respectively.

 The digital rotary phase digital receiver contains a bandpass filter 1, an amplifier 2 with automatic level control 2, an analog-to-digital converter 3, the first and second multipliers 4 and 5, the generator 6, the first, second, third and fourth low-pass filters ( LPF) 7-10, the first and second adders 11 and 12, the phase correction signal generator 13, the switching unit 14, the linear frequency modulated signal converter 15, the clock extraction unit 16, the adaptive corrector 17, the phase shifter 18, the decision unit 19, the decoder 20 descramb er 21, the phase manipulator 22, the unit 23 calculating the phase error, the phase adjusting unit 24 of the carrier wave and the switching unit 25 carrier.

 The clock allocation unit 16 comprises a clock frequency allocation unit 26, a clock adjustment unit 27, and a reference oscillator 28.

 The clock allocation block 26 comprises first and second multipliers 29 and 30, an adder 31, a bandpass filter 32, and a comparator 33.

 The carrier switching unit 25 comprises a first key 34, a comparator 35, an AND element 36, a trigger 37, a second, third and fourth keys 38-40.

 The phase manipulator 22 contains the first, second, third and fourth multipliers 41-44 and the first and second adders 45 and 46.

 The digital receiver operates as follows.

 When transmitting data on tonal frequency (PM) channels with speeds of 1200 and 2400 bit / s, two types of phase-shifted signals are used: option A, in which the phase difference between adjacent packets is a multiple of π at a speed of 1200 bit / s and π / 2 at a speed of 2400 bits / s, and option B with a phase difference multiple of π / 2 at a speed of 1200 bps and π / 4 at a speed of 2400 bps. Signals of type B have received the name of “rotary phase” signals in the literature and are used when working on PM channels of poor quality in order to maintain more stable operation of the clock synchronization system of the receiver of discrete signals.

t+iπ+π

η_j(m)+φ(t)

, (1) где ω_o круговая несущая частота;
φ(t) изменение фазы сигнала, вызванное его прохождением по каналу связи;
η(m) коэффициент, принимающий в данном случае значение 0,1.The phase-manipulated signal at a bit rate of 1200 bps can be represented as follows:
1. With the option of manipulation A
S _i Acos

t + iπ + π

η _j (m) + φ (t)

, (1) where ω _{o is the} circular carrier frequency;
φ (t) the phase change of the signal caused by its passage through the communication channel;
η (m) is a coefficient taking in this case a value of 0.1.

t+i₁

+π

(m)+

+ φ(t)

. (2)
Сравнивая (1) и (2) видим, что в структуре сигнала по варианту В появляется вращающаяся компонента i π/2, не несущая полезной информации, которую следует устранить в приемнике. При когерентном методе приема сигналов вида (1) и (2) в цифровом приемнике необходимо сформировать опорные колебания expj[ ω_ot+iπ+φ(t) для детектирования сигналов по варианту А и
expj

t+i₁

+ i

+φ(t)

по варианту В.2. With the option of manipulation In
S _i Acos

t + i ₁

+ π

(m) +

+ φ (t)

. (2)
Comparing (1) and (2), we see that the rotating component i π / 2 appears in the signal structure according to option B, which does not carry useful information that should be eliminated in the receiver. With a coherent method of receiving signals of the form (1) and (2) in a digital receiver, it is necessary to generate reference oscillations expj [ω _o t + iπ + φ (t) for detecting signals according to option A and
expj

t + i ₁

+ i

+ φ (t)

according to option B.

 It can be seen from the last expression that in order to receive signals with option B of manipulation, the phase of the reference oscillation in the receiver must be rotated by an angle π / 2. Similarly, it can be shown that when receiving signals at a speed of 2400 bit / s, manipulated according to option B, the phase of the reference oscillation in the receiver must be rotated by an angle multiple of i π / 4.

i₁

-i

+

η_j(m). (3)
С другой стороны, фазовую ошибку, вычисляемую в цифровом приемнике дискретных сигналов, можно записать следующим образом:
sinΔφ_i= I

, (4) где I_m{·} операция выделения мнимой части произведения;

комплексный сигнал на входе решающего блока приемника;

комплексно-сопряженная оценка сигнала на выходе решающего блока приемника.The rotation of the phase of the reference oscillation in the receiver is carried out initially not every clock cycle, but only by the enable signal U _i obtained by calculating the phase difference of the received and reference oscillation Δφ equal to the following value for the speed of 1200 bit / s (option B):
Δφ _i =

i ₁

-i

+

η _j (m). (3)
On the other hand, the phase error calculated in the digital receiver of discrete signals can be written as follows:
sinΔφ _i = I

, (4) where I _m {·} is the operation of extracting the imaginary part of the work;

complex signal at the input of the decision block of the receiver;

complex conjugate signal estimation at the output of the receiver decision block.

sin

i₁

i

+

η_j(m)

. (5)
В зависимости от соотношения фаз принимаемого и опорного колебаний Δφ_i может принимать значения, кратные K₁ π/2, где К₁ 0,1,2,3 для сигналов на скорости 1200 бит/с, манипулированных по варианту В, и кратные К₂ π /4, где К₂ 0,1,7 для сигналов варианта В на скорости 2400 бит/с.From (3) and (4) it follows that

sin

i ₁

i

+

η _j (m)

. (5)
Depending on the ratio of the phases of the received and reference oscillations, Δφ _i can take values that are multiples of K ₁ π / 2, where K ₁ 0,1,2,3 for signals at a speed of 1200 bit / s, manipulated according to option B, and multiples of K ₂ π / 4, where K ₂ 0,1,7 for the signals of option B at a speed of 2400 bit / s.

(6)
для сигналов со скоростью 2400 бит/с
U_i=

(7)
Рассмотренный выше алгоритм приема сигналов с "вращающейся фазой" реализован в предлагаемом устройстве.Then from (5) we obtain the following algorithm for the formation of the resolving signal U _i :
for signals at 1200 bps
U _i =

(6)
for signals at 2400 bps
U _i =

(7)
The above algorithm for receiving signals with a "rotating phase" is implemented in the proposed device.

 The digital receiver operates as follows.

The phase-shifted signal coming from the PM channel is filtered by a band-pass filter 1, then it is amplified by an amplifier 2 with automatic level control to a nominal value and converted into a digital form in the analog-to-digital converter 3. Digital samples of the received signal with a frequency of mf _pt (f _{pt is the} clock frequency of the receiver) generated by the sync signal extracting unit 16 are fed to a synchronous demodulator made on the first 4 and second 5 multipliers, generator 6, four low pass filters 7-10, first 11 and second 12 adders.

 Low-pass filters 7-10 are digital non-recursive filters, the values of the impulse characteristics of which are recorded in the driver 13 of the phase correction signal. Lowpass filters 7-10, in addition to post-detector filtering, perform the functions of a compromise corrector for the non-uniformity of the GVZ of the PM channel.

.The complex envelope of the received signal in the form of a real component at the output of the adder 11 and an imaginary component at the output of the adder 12 is supplied to the switching unit 14, which in this case switches the input signals to the first and fourth outputs, respectively, thereby supplying them to the input of the adaptive corrector 17. counts of the real and imaginary components received with a frequency f _PM from the output of the adaptive corrector 17 are received respectively at the first and second inputs of the phase shifter 18, which is a complex a multiplier constructed according to a structure similar to that of a phase manipulator 22. The third and fourth inputs of the phase shifter 18 are supplied with a definitely formed reference oscillation from the outputs of the phase manipulator 22. The phase-corrected signal is supplied from the outputs of the phase shifter in the form of two components to the second and third inputs of the decision block 19, which is a threshold circuit in which, according to the samples of the input signals, a decision is made on the adoption of an information symbol

.

с выхода решающего блока 19.The signals from the output of the phase shifter 18 are also received at the first and second inputs of the phase error calculation unit 22, the samples of which simultaneously come in the third and fourth inputs

from the output of the decisive block 19.

=

-γ₁Δφ_i-

(8) подстройки текущей фазы опорного колебания и алгоритм преобразования

⇒ expj

, осуществляемого, например, с помощью постоянного запоминающего устройства, входящего в состав блока 24 подстройки фазы несущего колебания.The phase error calculation unit 23 implements the algorithm (4) for evaluating the phase mismatch of the received and reference oscillations. The phase error calculation obtained in block 23 of the phase error calculation Δφ _i is supplied to the carrier oscillation phase adjustment block 24, which implements the algorithm

=

-γ ₁ Δφ _i -

(8) adjusting the current phase of the reference oscillation and the transformation algorithm

⇒ expj

carried out, for example, using a permanent storage device included in the block 24 phase adjustment of the carrier oscillation.

A phase mismatch error from the output of the phase error calculation unit 23 is also fed to the second input of the carrier switching unit 25, in which it is fed to the input of the comparator 35, to the second input of which the threshold voltage U _n1 or U _n2 is supplied from the output of the key 34, depending on the selected speed receiver work 1200 or 2400 bit / s. Switching of the first key is carried out by logical signals supplied to the third input of the carrier switching unit 25. The comparator 35 implements an algorithm for comparing a phase error with a threshold and generating an enabling signal U _i in accordance with expressions (6) or (7). Depending on the results of the comparison, a logical 1 or a logical 0 signal appears at the output of the comparator 35, which is fed to the input of the And 36 element, to the second input of which clock pulses are applied, tied to the moments of manipulation in the received signal. The clock frequency comes from the second output of the block 16 allocation of clock signals. To the third input of the And 36 element from the fourth input of the carrier switching unit 25, a logical "0" is supplied, allowing the reception of signals manipulated by option B.

, т.е. если в i-ый момент времени разность фаз между принимаемый и опорным сигналами в приемнике близка к k π, соотношение (5), т.е. другими словами, если в i-ый тактовый момент времени фазы принимаемого и опорного сигнала совпадают с точностью до π то на выходе элемента И 36 формируется разрешающий сигнал U_i 1, по которому перебрасывается триггер 37, переключая сигналами с первого и второго выходов ключи 38 и 39 таким образом, чтобы на выходе ключа 38 присутствовал логический "0", а на выходе ключа 39 логическая "1", поступающие на их второй и третий входы соответственно с первого и второго выходов ключа 40. Одновременно на третий и четвертый входы фазового манипулятора 22 с выходов блока 24 подстройки фазы несущего колебания подается сигнал вида expj

= cos

+jsin

. Предположим, что до момента прихода разрешающего сигнала U_i ключи 38 и 39 находились в таком положении, что на первом выходе блока 25 коммутации несущей и соответственно на первом входе фазового манипулятора 22 была логическая "1", на втором выходе блока 25 коммутации несущей и соответственно на втором входе фазового манипулятора 22 был логический "0". Тогда сигнал на выходе сумматора 45 фазового манипулятора 22 был бы пропорционален cos cos

а на выходе сумматора 46 пропоpционален sin sin

При переключении триггера 37 (U_i 1) сигнал на первом входе фазового манипулятора 22 становится равным логическому "0", а на втором входе логической "1". При этом сигнал на выходе сумматора 45 фазового манипулятора 22 будет пропорционален sin sin

а на выходе сумматора 46 cos cos

т.е. произойдет поворот фазы опорного колебания, подаваемого на третий и четвертый входы фазовращателя 18, на π /2. Далее данный процесс будет автоматически повторяться, осуществляя тем самым вращение фазы опорного колебания в приемнике на угол, кратный π /2.The resolving signal U _i , tied to the moments of manipulation in the received signal, is output from the output of the And 36 element to the counting input C of the trigger 37. The value of the resolving signal U _i is determined by the algorithm described by expressions (6) and (7). If, for example, at a bit rate of 1200 bps I

, i.e. if at the ith moment of time the phase difference between the received and reference signals in the receiver is close to k π, relation (5), i.e. in other words, if at the i-th clock moment of time the phases of the received and reference signals coincide to an accuracy of π, then the output signal U 36 forms an enable signal U _i 1, along which the trigger 37 is transferred, switching keys 38 and signals from the first and second outputs 39 so that at the output of the key 38 there is a logical “0”, and at the output of the key 39 a logical “1”, received at their second and third inputs respectively from the first and second outputs of the key 40. At the same time, at the third and fourth inputs of the phase manipulator 22 from exits 24 Lok adjustment phase of the carrier wave signal supplied form expj

= cos

+ jsin

. Suppose that before the arrival of the enable signal U _{i, the} keys 38 and 39 were in such a position that at the first output of the carrier switching unit 25 and, accordingly, at the first input of the phase manipulator 22 there was a logical “1”, at the second output of the carrier switching unit 25 and, accordingly, at the second input of the phase manipulator 22 was a logical "0". Then the signal at the output of the adder 45 of the phase manipulator 22 would be proportional to cos cos

and at the output of the adder 46 is proportional to sin sin

When the trigger 37 (U _i 1) is switched, the signal at the first input of the phase manipulator 22 becomes equal to the logical "0", and at the second input, the logical "1". The signal at the output of the adder 45 of the phase manipulator 22 will be proportional to sin sin

and at the output of the adder 46 cos cos

those. the phase of the reference oscillation supplied to the third and fourth inputs of the phase shifter 18 will turn by π / 2. Further, this process will be automatically repeated, thereby rotating the phase of the reference oscillation in the receiver by an angle multiple of π / 2.

±1, т.е. если разность фаз в i-ый момент времени между принимаемым и опорным колебаниями кратна π /2, то разрешающий сигнал на выходе элемента И 36 не появляется (логический "0"), триггер 37 не перебрасывается и соответственно ключи 38 и 39 остаются в исходном положении, сохраняя тем самым логическую "1" на первом входе фазового манипулятора 22 и логический "0" на его втором входе. Поворота фазы опорного колебания в данном случае не происходит.If at the i-th clock moment I

± 1, i.e. if the phase difference at the ith moment of time between the received and reference oscillations is a multiple of π / 2, then the resolving signal at the output of the And 36 element does not appear (logical "0"), the trigger 37 does not transfer and, accordingly, the keys 38 and 39 remain in the initial position , thereby preserving the logical "1" at the first input of the phase manipulator 22 and the logical "0" at its second input. The rotation phase of the reference oscillation in this case does not occur.

 Similarly, the proposed device operates at a transmission speed of 2400 bps.

 The difference from the algorithm considered above in this case is the comparison of the phase error with a threshold voltage equal to in the comparator 35, and the supply to the inputs of the keys 38 and 39 of voltages proportional to the value of 0.707 that come from the outputs of the key 40 when it is closed.

 To receive the clock pulses in the receiver, reduced to the moments of manipulation in the received signal, there is a block 16 allocation of clock signals, which operates as follows.

 The real and imaginary components of the complex envelope of the received signal are fed to the first and second inputs of the clock frequency isolation unit 26, in which they are squared in the multipliers 29 and 30 and added together, thus forming the square of the complex envelope module at the output of the adder 31. The spectrum of the complex envelope of the received signal contains a component with a frequency equal to the clock, which is allocated by the band-pass filter 32 and fed to the comparator 33, which generates rectangular pulses of the received clock frequency at its output. The selected clock pulses are fed to the first input of the clock adjustment unit 27, the second input of which is supplied with high frequency pulses from the output of the reference generator 28. The clock adjustment block 27 is a discrete phase-locked loop with pulse control of the addition and subtraction signals, in which, as The reference oscillation uses the clock frequency extracted from the received signal.

The pulses of the clock frequency tuned to the received signal from the second output of the sync signal separation unit 16 are supplied to the carrier switching unit 25, thereby linking the enable signal U _i to the manipulation moments in the received signal. In addition, pulses with a frequency of mf _PM (m 5-8) from the first output of the block 16 allocation of clock signals are fed to the second input of the analog-to-digital Converter 3 to sample the received signal when it is converted to digital form.

Claims (5)

 1. DIGITAL RECEIVER OF DISCRETE SIGNALS WITH "ROTATING PHASE", comprising an amplifier with automatic level control, the output of which is connected to the first input of an analog-to-digital converter (ADC), an adaptive corrector, a decision unit, the first and second inputs of which are connected to the first and second inputs phase error calculation unit, the third and fourth inputs of which are connected respectively to the first and second outputs of the deciding unit and the first and second inputs of the decoder, the phase adjustment block of the carrier wave, characterized in that a bandpass filter, a first and a second multiplier, a generator, a first, a second, a third and a fourth low-pass filter (LPF), a first and a second adder, a phase correction signal generator, a switching unit, a signal converter with linear frequency modulation, a clock extraction unit, phase shifter, descrambler, phase manipulator, carrier switching unit, the output of the bandpass filter, the input of which is the input of the receiver, connected to the input of the amplifier with automatic level control, the ADC output is connected to the first input odes of the first and second multipliers, the second inputs of which are connected respectively to the first and second outputs of the generator, the output of the first multiplier is connected to the first inputs of the first and second low-pass filters, the second inputs of which are connected to the output of the driver of the phase correction signal and the first inputs of the third and fourth low-pass filters, the second input the latter is connected to the second input of the third low-pass filter and the output of the second multiplier, the output of the first low-pass filter is connected to the first input of the first adder, the second input of which is connected to the output of the third low-pass filter, the output is quad o LPF is connected to the first input of the second adder, the second input of which is connected to the output of the second LPF, the output of the first adder is connected to the first input of the switching unit, the second input of which is connected to the output of the second adder, the first output of the switching unit is connected to the first output of the signal converter with linear frequency modulation and the first inputs of the block selection of clock signals and adaptive corrector, the second input of which is connected to the second input of the block selection of clock signals, the second output of the signal converter from frequency modulation and the second output of the switching unit, the third and fourth outputs of which are connected respectively to the first and second inputs of the signal converter with linear frequency modulation, the first and second outputs of the adaptive corrector are connected respectively to the first and second inputs of the driver, the third and fourth inputs of which are connected to the first and second outputs of the phase manipulator, the first and second inputs of which are connected respectively to the first and second outputs of the carrier switching unit, the first input of which connected to the output of the phase error calculation unit and the input of the carrier phase adjustment block, the first and second outputs of which are connected to the third and fourth inputs of the phase manipulator, the first and second outputs of the phase shifter are connected respectively to the first and second inputs of the decision unit, the second ADC input is connected to the first output of the clock allocation unit, the second output of which is connected to the second input of the carrier switching unit, the third input of the decision unit and the third input of the adaptive corrector, the output of the decoder oedinen to the input of the descrambler, the output of which is the output of the receiver, the third and fourth inputs of unit switching carrier are appropriate digital receiver inputs.  2. The receiver according to claim 1, characterized in that the clock allocation unit comprises serially connected a clock allocation unit and a clock adjustment unit, the second input of which is connected to the output of the reference generator, the inputs of the clock allocation unit are the inputs of the clock allocation unit are inputs of the unit allocation of clock signals, the outputs of which are the outputs of the block adjustment of the clock.  3. The receiver according to claim 2, characterized in that the clock allocation unit comprises a first and second multiplier, an adder, a band-pass filter and a comparator, the first and second inputs of the first multiplier are interconnected and are the first input of the clock allocation unit, the second input of which are the combined first and second inputs of the second multiplier, the output of which is connected to the first input of the adder, the second input of which is connected to the output of the first multiplier, the output of the adder is connected to the input of the bandpass filter, the output of which of the connections to the input of the comparator, whose output is the output of the clock selection block.  4. The receiver according to claim 1, characterized in that the carrier switching unit comprises a comparator, four keys, an element And a trigger, the first input of the carrier switching unit is the first input of the comparator, the second input of which is connected to the output of the first key, the first and second inputs of which are threshold voltage inputs, the comparator output is connected to the first input of the And element, the second input of which is the second input of the carrier switching unit, the output of the And element is connected to the first input of the trigger, the second input of which is connected to the third input element And is the fourth input of the carrier switching unit, the first trigger output is connected to the first input of the second key, the second and third inputs of which are connected respectively to the first and second outputs of the fourth key and the first and second inputs of the third key, the first input of which is connected to the second output of the trigger , the output of the second key is the first output of the carrier switching unit, the second output of which is the output of the third key, the third input of the carrier switching unit is the third input of the first key and the first input tvertogo key, second, third and fourth inputs which are the inputs of the constant signal.  5. The receiver according to claim 1, characterized in that the phase manipulator contains four multipliers and two adders, the outputs of which are the outputs of the phase manipulator, the first inputs of the first and second multipliers are combined and are the third input of the phase manipulator, the fourth input of which is the combined second inputs of the third and the fourth multiplier, the second input of the first multiplier is combined with the second input of the third multiplier and is the first input of the phase manipulator, the second input of which is the combined second moves of the second and fourth multipliers, the output of the first multiplier is connected to the first input of the first adder, the second input of which is connected to the output of the fourth multiplier, the output of the third multiplier is connected to the first input of the second adder, the second input of which is connected to the output of the second multiplier.

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