RU205198U1 - A PARAMETRIZABLE SINGLE-STROKE BINARY MULTIPLIER WITH A FIXED DOT IN A DIRECT AND AUXILIARY CODE - Google Patents

Abstract

The utility model relates to the field of digital signal processing, to the structures of computing units of microprocessors. The technical result of the utility model is the creation of a parameterizable single-cycle multiplier of binary numbers with a fixed point in the direct and complementary code, which possesses: increased universality due to the fact that any of the factors can be represented both in the direct and in the complementary code; improved parameterisability due to the possibility of implementation for multipliers with any number of digits; smaller size in area and increased speed due to the absence of additional adders for converting the product and a simpler topology; increased versatility due to the possibility of outputting the result in a two-row code, which allows you to use partial products further without transfer delay. For this, a corresponding scheme of a parameterizable single-cycle multiplier is proposed. 1 wp f-ly, 8 dwg

Description

The utility model relates to the field of digital signal processing, to the structures of computing units of microprocessors, and specifically to parameterizable single-cycle multipliers of binary numbers with a fixed point in the direct and two's complement code, and can be used to calculate the product of fixed-point numbers in the direct and complement codes.

To solve problems of digital signal processing, one of the key operations is the multiplication operation. Along with addition, this is the main operation required to calculate Fourier transforms, filters and matrix products, which, in turn, is the basis for solving communication problems, image and video processing, as well as convolutional neural networks. Thus, the performance of multiplication operations is the basis for quickly solving critical digital signal processing problems. This applies to both floating point and fixed point multiplication. In this case, fast and efficient multiplication of fixed-point numbers is most important, since multiplication of floating-point numbers is based on the multiplication of their mantissas, which are fixed-point numbers in direct code.

The traditional approach to the development of single-cycle fixed-point multipliers involves the use of an array of one-bit multipliers that calculate the partial products of the factors, as well as an array of one-bit full adders and half-adders arranged in cascades and calculating the sums of the partial products. In this case, the traditional scheme is designed to multiply numbers in direct code. In the event that one or both of the factors are represented in a two's complement code, corrections of the factors and / or the result are required, which slow down the execution of the multiplication operation.

Known multiplier described in patent RU2422881 (C1), which is based on an array of one-bit full adders and half adders. This structure has a low transfer delay, in addition, it has the possibility of parameterization for multipliers of different bit widths.

The disadvantage of this multiplier is not sufficient versatility, due to the possibility of multiplying only numbers in the direct code.

US Pat. Nos. 5313414 (A) and US5351206 (A) disclose multiplier structures based on an array of 1-bit full adders and half adders. These structures have low transfer latency. There is a possibility of parameterization for multipliers of different bit sizes.

The disadvantage of these multipliers is not sufficient versatility, due to the possibility of multiplying only numbers in the two's complement code and the fact that one of the factors is a constant.

The closest to the claimed utility model is the multiplier described in US Pat. No. 5,153,850 (A), which allows multiplying both direct and complementary numbers. This multiplier is chosen as a prototype of the claimed utility model.

The disadvantages of the multiplier of the prototype are large dimensions in area and low speed, due to the lack of parameterization and the presence of additional adders for converting the product.

The technical result of the utility model is the creation of a parameterizable single-cycle multiplier of binary numbers with a fixed point in the direct and complementary code, which possesses: increased universality due to the fact that any of the factors can be represented both in the direct and in the complementary code; improved parameterisability, due to the possibility of implementation for multipliers with any number of digits; smaller size in area and increased speed, due to the absence of additional adders for converting the product and a simpler topology; increased versatility, due to the possibility of outputting the result in a two-row code, which allows the use of partial products for further computations without transfer delay on the adder.

The stated technical result was achieved by creating a parameterizable single-cycle multiplier of binary numbers with a fixed point in the direct and complementary code, containing the interconnected:

- an array of one-bit multipliers [1], made with the possibility of forming partial one-bit products of the input factors;

- logical blocks XOR [2], made with the possibility of modifying the multipliers taking into account their type, as well as with the ability to receive input signals (tcA) and (tcB)

- an array of one-bit full adders [3] and half-adders [4], arranged in cascades with a shift and connected with the possibility of forming a final product, represented by a two-row code in the form of two partial products.

In a preferred embodiment of the multiplier, the inputs to the multiplier are:

- the first factor (a), represented by the bit vector a _{n – 1} , a _{n – 2} , ..., a ₁ , a ₀ , where n is the size of the vector (n ≥ 1), and _{n – 1} is the most significant (signed) bit;

- the second factor (b), represented by the bit vector b _{m – 1} , b _{m – 2} , ..., b ₁ , b ₀ , where m is the size of the vector (m ≥ 1), b _{m – 1} is the most significant (signed) bit;

- signal (tc _A ), made with the possibility of determining the type of the first factor (a): 0 - direct code, 1 - additional code;

- signal (tc _B ), made with the possibility of determining the type of the second factor (b): 0 - direct code, 1 - additional code;

the output of the multiplier is:

- the first partial product (s) (the sum of partial products of factors), represented by the bit vector s _{n + m – 1} , s _{n + m – 2} , ..., s ₁ , s ₀ , where (n + m) is the size of the vector , s _{n + m – 1} - most significant (sign) bit;

- the second partial product (p) (carry vector) represented by the bit vector p _{n + m – 1} , p _{n + m – 2} , ..., p ₁ , p ₀ , where (n + m) is the size of the vector, p _{n + m – 1} is the most significant (sign) bit.

In a preferred embodiment of the multiplier for n ≥ 4, m ≥ 4

- for any of the blocks one-bit multiplier [1], logical block XOR [2], one-bit full adder [3] and half-adder [4], the order of inputs does not affect the output result, that is, the inputs of these blocks can be swapped;

- signal (n _A ) at the output of the logical block XOR [2], the inputs of which are connected to the inputs of the multiplier (a _{n – 1} ) and (tc _A );

- signal (n _B ) at the output of the logical block XOR [2], the inputs of which are connected to the inputs of the multiplier (b _{m – 1} ) and (tc _B );

- the array of one-bit full adders [3] and half adders [4] contains (m – 2) stages, which are numbered using the index (i), where (i = 0,1, ..., m – 3;

- a cascade of one-bit full adders [3] and half-adders [4] with index (i = 0) contains (n) one-bit full adders [3] and half-adders [4], which are numbered using the index (j), where (j = 0 , 1, ..., n – 1);

- each stage of one-bit full adders [3] and half-adders [4] with an index (i = 1, ..., m – 3) contains (n – 1) one-bit full adders [3] and half adders [4], which are numbered when using the index (j), where (j = 1, ..., n – 1);

- elements of the cascade of one-bit full adders [3] and half-adders [4] with index (i = 0) are (n – 1) one-bit full adders [3] with indices (j = 1, ..., n – 1) and one one-digit half-adder [4] with index (j = 0);

- elements of a cascade of one-bit full adders [3] and half-adders [4] with an index (i = 1, ..., m – 4), provided (m> 4), are (n – 2) one-bit full adders [3] with indices (j = 2, ..., n – 1) and one single-digit half-adder [4] with an index (j = 1);

- elements of a cascade of one-bit full adders [3] and half-adders [4] with index (i = m – 3) are (n – 1) one-bit full adders [3] with indices (j = 1, ..., n – 1) ;

- the output of the multiplier (p ₀ ) is connected to a logical zero;

- the output of the multiplier (s ₀ ) is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the inputs of the multiplier (a ₀ ) and (b ₀ );

- the output of the multiplier (p ₁ ) is connected to a logical zero;

- the outputs of the multiplier (s ₁ ) and (p ₂ ) are connected to the outputs (s) and (co), respectively, of a one-digit half-adder [4] with indices (i = 0, j = 0), inputs (a) and (b) of which are connected with the outputs of one-bit multipliers [1], the inputs of the first of which are connected to the inputs of the multiplier (a ₁ ) and (b ₀ ), and the inputs of the second to the inputs of the multiplier (a ₀ ) and (b ₁ );

- the outputs of the multiplier (s ₂ ) and (p ₃ ) are connected to the outputs (s) and (co), respectively, of a one-bit full adder [3] with indices (i = 0; j = 1), inputs (a), (b) and (co) of which are connected to the outputs of one-bit multipliers [1], the inputs of the first of which are connected to the inputs of the multiplier (a ₂ ) and (b ₀ ), the inputs of the second to the inputs of the multiplier (a ₁ ) and (b ₁ ), and the inputs of the third to multiplier inputs (a ₀ ) and (b ₂ );

- the outputs of the multiplier (s _k ) and (p _{k + 1} ), where (k = 3, ..., m – 2), provided (m> 4), are connected to the outputs (s) and (co), respectively, of one-bit half adders [4] with indices (i = k – 2; j = 1), respectively;

- the outputs of the multiplier (s _k ) and (p _{k + 1} ), where (k = m – 1, ..., m + n – 3), are connected to the outputs (s) and (co), respectively, of one-bit full adders [3 ] with indices (i = m – 3; j = k – m + 2), respectively;

- the output of the multiplier (s _{m + n – 2} ) is connected to the output of the logical block XOR [2], the input (a) of which is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the inputs of the multiplier (a _{n – 1} ) and (b _{m – 1} ), and the input (b) of which is connected to the output of the logical block XOR [2], the inputs of which are connected to the signals (n _A ) and (n _B );

- the output of the multiplier (p _{m + n – 1} ) is connected to the output of the logical block XOR [2], the inputs of which are connected to the signals (n _A ) and (n _B );

- the output of the multiplier (s _{m + n – 1} ) is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the signals (n _A ) and (n _B );

- inputs (a) of one-bit full adders [3] with indices (i = 0, ..., m – 3; j = n – 1), connected to the outputs of logical blocks XOR [2], inputs (a) of which are connected to outputs of one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _j ) and (b _{i + 1} ), respectively, and the inputs (b) of which are connected to the signals (n _A );

- inputs (a) of one-bit full adders [3] with indices (i = 1, ..., m – 3; j = 2, ..., n – 2) are connected to outputs (s) of one-bit full adders [3] with indices (i – 1; j + 1), respectively;

- input (a) of a one-bit full adder [3] with indices (i = m – 3; j = 1) is connected to the output (s) of a one-bit full adder [3] with indices (i – 1; j + 1);

- inputs (a) of one-bit half-adders [4] with indices (i = 1, ..., m – 4; j = 1), provided (m> 4), are connected to outputs (s) of one-bit full adders [3] with indices (i – 1; j + 1).

For a better understanding of the claimed invention, the following is a detailed description with the corresponding graphic materials. For a better understanding of the claimed utility model, its detailed description with corresponding graphic materials is given below.

FIG. 1. Scheme of multiplication of binary numbers in direct code, known from the prior art.

FIG. 2. A matrix multiplier circuit for 4-bit multipliers known in the art.

FIG. 3. Designation and truth table of a one-bit multiplier known from the prior art.

FIG. 4. Designation and truth table of the XOR logic block known from the prior art.

FIG. 5. Designation and truth table of a one-bit full adder known from the prior art.

FIG. 6. Designation and truth table of a one-digit half-adder known from the prior art.

FIG. 7. Scheme of a parameterizable single-cycle multiplier of binary numbers with a fixed point in direct and complementary code for multipliers of 6 bits, made according to the utility model.

FIG. 8. A simplified diagram of a parameterizable single-cycle multiplier of binary numbers with a fixed point in direct and complement code for multipliers of 6 bits, made according to the utility model, in which the graphic designations of single-bit multipliers and XOR blocks are replaced by logical expressions.

Let us consider in more detail the operation of the claimed parameterizable single-cycle multiplier of binary numbers with a fixed point in the direct and complementary code (Fig. 7 - 8).

Multiplication of multi-digit binary numbers is carried out similarly to multiplication of decimal numbers: the partial products obtained by bitwise multiplication of the digits that make up each number are added taking into account the weight and form the final product. FIG. 1 shows an example of multiplication of four-bit binary numbers in direct code.

The claimed utility model is based on the traditional structure of a binary matrix multiplier. An example of such a structure for two four-bit direct-code multipliers is shown in FIG. 2. This structure consists of an array of one-bit multipliers that form partial products, and an array of one-bit full adders and half-adders connected in such a way as to perform sequential addition of partial products to form the final product. The advantages of this structure are scalability, that is, such a structure is easy to compose for multipliers of any size and is easy to parameterize, and simplicity of wiring when developing an IC topology, which has a positive effect on the area and speed of the device. The disadvantage of this structure is that it does not allow the multiplication of numbers in two's complement code. The declared utility model solves this problem by introducing a correction for partial products, in which the most significant (sign) digits of the factors are involved. The correction is carried out based on flags indicating the type of multipliers (direct or complementary code). In this case, there is no additional delay in the execution of the multiplication.

The hardware implementation of the claimed utility model is an IP-block of a parameterizable single-cycle multiplier of binary numbers with a fixed point in the direct and two's complement code. The circuit of the claimed multiplier (a variant for multipliers with a size of 6 bits) is shown in Fig. 7.

The declared multiplier includes:

- one-bit multipliers [1], which form partial one-bit products of the input factors;

- logical blocks XOR [2], modifying the multipliers taking into account their type, which is determined by the input signals (tc _A ) and (tc _B );

- an array of one-bit full adders [3] and half-adders [4], arranged in cascades with a shift and connected in such a way as to form a final product represented by a two-row code (two partial products).

The input data for the multiplier are:

- the first factor (a), represented by the bit vector a _{n – 1} , a _{n – 2} , ..., a ₁ , a ₀ , where n is the size of the vector (n ≥ 1), and _{n – 1} is the most significant (signed) bit;

- the second factor (b), represented by the bit vector b _{m – 1} , b _{m – 2} , ..., b ₁ , b ₀ , where m is the size of the vector (m ≥ 1), b _{m – 1} is the most significant (signed) bit;

- signal (tc _A ), which determines the type of the first factor (a) (0 - direct code, 1 - additional code).

- signal (tc _B ), which determines the type of the second factor (b) (0 - direct code, 1 - additional code).

The output of the multiplier is:

- the first partial product (s) (the sum of partial products of factors), represented by the bit vector s _{n + m – 1} , s _{n + m – 2} , ..., s ₁ , s ₀ , where (n + m) is the size of the vector , s _{n + m – 1} - most significant (sign) bit;

- the second partial product (p) (carry vector) represented by the bit vector p _{n + m – 1} , p _{n + m – 2} , ..., p ₁ , p ₀ , where (n + m) is the size of the vector, p _{n + m – 1} is the most significant (sign) bit.

Consider an embodiment of the claimed multiplier, in which (n ≥ 4, m ≥ 4).

Variants of the claimed multiplier for the cases (n <4) or (m <4) are not considered, however, they can be implemented on the basis of the formula for the case (n ≥ 4, m ≥ 4).

As follows from the truth tables of one-bit multiplier [1], logical block XOR [2], one-bit full adder [3] and half-adder [4], for any of these blocks the order of inputs does not affect the output result, that is, the inputs of these blocks can be changed places.

Let's designate as a signal (n _A ) the output of the logical block XOR [2], the inputs of which are connected to the inputs of the multiplier (a _{n – 1} ) and (tc _A ).

Let's designate as a signal (n _B ) the output of the logical block XOR [2], the inputs of which are connected to the inputs of the multiplier (b _{m – 1} ) and (tc _B ).

The array of one-bit full adders [3] and half-adders [4] contains (m – 2) stages, which are numbered using the index (i), where (i = 0,1, ..., m – 3).

A cascade of one-bit full adders [3] and half-adders [4] with index (i = 0) contains (n) one-bit full adders [3] and half-adders [4], which are numbered using the index (j), where (j = 0, 1, ..., n – 1).

Each stage of one-bit full adders [3] and half-adders [4] with an index (i = 1, ..., m – 3) contains (n – 1) one-bit full adders [3] and half adders [4], which are numbered using index (j), where (j = 1, ..., n – 1).

Elements of a cascade of one-bit full adders [3] and half-adders [4] with index (i = 0) are (n – 1) one-bit full adders [3] with indices (j = 1, ..., n – 1) and one single-bit half adder [4] with index (j = 0).

Elements of a cascade of one-bit full adders [3] and half-adders [4] with an index (i = 1, ..., m – 4), provided (m> 4), are (n – 2) one-bit full adders [3] with indices (j = 2, ..., n – 1) and one one-digit half-adder [4] with an index (j = 1).

Elements of a cascade of one-bit full adders [3] and half-adders [4] with index (i = m – 3) are (n – 1) one-bit full adders [3] with indices (j = 1, ..., n – 1).

The output of the multiplier (p ₀ ) is connected to a logical zero.

The output of the multiplier (s ₀ ) is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the inputs of the multiplier (a ₀ ) and (b ₀ ).

The output of the multiplier (p ₁ ) is connected to a logic zero.

The outputs of the multiplier (s ₁ ) and (p ₂ ) are connected to the outputs (s) and (co), respectively, of a one-bit half-adder [4] with indices (i = 0, j = 0), inputs (a) and (b) of which are connected to outputs of one-bit multipliers [1], the inputs of the first of which are connected to the inputs of the multiplier (a ₁ ) and (b ₀ ), and the inputs of the second to the inputs of the multiplier (a ₀ ) and (b ₁ ).

The outputs of the multiplier (s ₂ ) and (p ₃ ) are connected to the outputs (s) and (co), respectively, of a one-bit full adder [3] with indices (i = 0; j = 1), inputs (a), (b) and ( co) which are connected to the outputs of one-bit multipliers [1], the inputs of the first of which are connected to the inputs of the multiplier (a ₂ ) and (b ₀ ), the inputs of the second to the inputs of the multiplier (a ₁ ) and (b ₁ ), and the inputs of the third to the inputs multiplier (a ₀ ) and (b ₂ ).

The outputs of the multiplier (s _k ) and (p _{k + 1} ), where (k = 3, ..., m – 2), under the condition (m> 4), are connected to the outputs (s) and (co), respectively, of one-digit half-adders [4] with indices (i = k – 2; j = 1), respectively.

The outputs of the multiplier (s _k ) and (p _{k + 1} ), where (k = m – 1, ..., m + n – 3), are connected to the outputs (s) and (co), respectively, of one-bit full adders [3] with indices (i = m – 3; j = k – m + 2), respectively.

The output of the multiplier (s _{m + n – 2} ) is connected to the output of the logical block XOR [2], the input (a) of which is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the inputs of the multiplier (a _{n – 1} ) and (b _{m –1} ), and the input (b) of which is connected to the output of the logic block XOR [2], the inputs of which are connected to the signals (n _A ) and (n _B ).

The output of the multiplier (p _{m + n – 1} ) is connected to the output of the logic block XOR [2], the inputs of which are connected to the signals (n _A ) and (n _B ).

The output of the multiplier (s _{m + n – 1} ) is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the signals (n _A ) and (n _B ).

Inputs (a) of one-bit full adders [3] with indices (i = 0, ..., m – 3; j = n – 1), connected to the outputs of logical blocks XOR [2], inputs (a) of which are connected to the outputs one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _j ) and (b _{i + 1} ), respectively, and the inputs (b) of which are connected to the signals (n _A ).

Inputs (a) of one-bit full adders [3] with indices (i = 1, ..., m – 3; j = 2, ..., n – 2) are connected to outputs (s) of one-bit full adders [3] with indices (i – 1; j + 1), respectively.

Input (a) of a one-bit full adder [3] with indices (i = m – 3; j = 1) is connected to the output (s) of a one-bit full adder [3] with indices (i – 1; j + 1).

Inputs (a) of one-bit half-adders [4] with indices (i = 1, ..., m – 4; j = 1), provided (m> 4), are connected to outputs (s) of one-bit full adders [3] with indices (i – 1; j + 1), respectively.

Inputs (ci) of one-bit full adders [3] with indices (i = 1, ..., m – 3; j = 2, ..., n – 1) are connected to outputs (co) of one-bit full adders [3] with indices (i – 1; j), respectively.

Input (ci) of one-bit full adder [3] with indices (i = m – 3; j = 1) is connected to the output of logic block XOR [2], the inputs of which are connected to signals (n _A ) and (n _B ).

Inputs (b) of one-bit full adders [3] with indices (i = m – 3; j = 1, ..., n – 1), connected to the outputs of logical blocks XOR [2], inputs (a) of which are connected to the outputs one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _{j – 1} ) and (b _{i + 2} ), respectively, and the inputs (b) of which are connected to the signals (n _B ).

Inputs (b) of one-bit full adders [3] with indices (i = 1, ..., m – 4; j = 2, ..., n – 1), provided (m> 4), are connected to the outputs of one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _{j – 1} ) and (b _{i + 2} ), respectively.

Inputs (b) of one-bit half-adders [4] with indices (i = 1, ..., m – 4; j = 1), provided (m> 4), are connected to the outputs of one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _{j – 1} ) and (b _{i + 2} ), respectively.

Input (ci) of a one-bit full adder [3] with indices (i = 0; j = n – 1) is connected to the output of the logical block XOR [2], the inputs of which are connected to signals (n _A ) and (n _B ).

Input (a) of a one-bit full adder [3] with indices (i = 0; j = n – 2), connected to the outputs of the logical block XOR [2], input (a) of which is connected to the output of a one-bit multiplier [1], whose inputs connected to the inputs of the multiplier (a _{j + 1} ) and (b _i ), and the input (b) of which is connected to the signal (n _A ).

Inputs (a) of one-bit full adders [3] with indices (i = 0; j = 2, ..., n – 3), provided (n> 4), are connected to the outputs of one-bit multipliers [1], the inputs of which are connected with the inputs of the multiplier (a _{j + 1} ) and (b _i ), respectively.

Inputs (b) of one-bit full adders [3] with indices (i = 0; j = 2, ..., n – 1) are connected to the outputs of one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _{j – 1} ) and (b _{i + 2} ), respectively.

Inputs (ci) of one-bit full adders [3] with indices (i = 0; j = 2, ..., n – 2) are connected to the outputs of one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _j ) and ( b _{i + 1} ), respectively.

The output of the multiplier, represented by the first partial product (s) (the sum of the partial products of factors) and the second partial product (p) (the carry vector) can be converted to the final product (x) represented by the bit vector x _{n + m – 1} , x _{n + m – 2} , ..., x ₁ , x ₀ , where (n + m) is the size of the vector, x _{n + m – 1} is the most significant (sign) bit.

To obtain the final product (x), it is necessary to feed the output of the multiplier, represented by the first and second partial products, to the inputs of an (n + m) -bit half-adder, called a cast adder.

The final product (x) is the output of the cast adder.

The declared parameterizable single-cycle multiplier of binary numbers with a fixed point in direct and two's complement code has the following advantages.

Possesses the property of universality due to the fact that any of the factors can be represented both in direct and in complementary code.

It is parameterizable due to the fact that it can be implemented for multipliers with any number of digits.

Has a smaller area in comparison with non-universal multipliers.

It has ease of wiring when implemented as a topology of an integrated microcircuit, which reduces its size in area and increases its performance.

Gives the result in two-row code, which allows you to use partial works further without delay of transfer when forming a complete work.

Gives out the full multiplier product, if it contains an additional (n + m) -digit half-adder, which sums the partial products of a two-row code.

Although the above-described embodiment of the claimed utility model has been set forth for the purpose of illustrating the claimed utility model, it is clear to those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and meaning of the claimed utility model disclosed in the attached utility model claims.

Claims (33)

1. Parameterizable single-cycle multiplier of binary numbers with a fixed point in direct and complement code, containing the interconnected: - an array of one-bit multipliers [1], made with the possibility of forming partial one-bit products of the input factors; - logical blocks XOR [2], made with the possibility of modifying the multipliers taking into account their type, as well as with the ability to receive input signals (tc _A ) and (tc _B ); - an array of one-bit full adders [3] and half-adders [4], arranged in cascades with a shift and connected with the possibility of forming a final product represented by a two-row code in the form of two partial products, and for n ≥ 4, m ≥ 4: - for any of the blocks one-bit multiplier [1], logical block XOR [2], one-bit full adder [3] and half-adder [4], the order of inputs does not affect the output result, that is, the inputs of these blocks can be swapped; signal (n_A) at the output of the logical block XOR [2], the inputs of which are connected to the inputs of the multiplier (a_{n – 1}) and (tc_A); signal (n_B) at the output of the logic block XOR [2], the inputs of which are connected to the inputs of the multiplier (b_{m – 1}) and (tc_B); - the array of one-bit full adders [3] and half adders [4] contains (m – 2) stages, which are numbered using the index (i), where (i = 0,1, ..., m – 3); - a cascade of one-bit full adders [3] and half-adders [4] with index (i = 0) contains (n) one-bit full adders [3] and half-adders [4], which are numbered using the index (j), where (j = 0 , 1, ..., n – 1); - each stage of one-bit full adders [3] and half-adders [4] with an index (i = 1, ..., m – 3) contains (n – 1) one-bit full adders [3] and half adders [4], which are numbered when using the index (j), where (j = 1, ..., n – 1); - elements of the cascade of one-bit full adders [3] and half-adders [4] with index (i = 0) are (n – 1) one-bit full adders [3] with indices (j = 1, ..., n – 1) and one one-digit half-adder [4] with index (j = 0); - elements of a cascade of one-bit full adders [3] and half-adders [4] with an index (i = 1, ..., m – 4), provided (m> 4), are (n – 2) one-bit full adders [3] with indices (j = 2, ..., n – 1) and one single-digit half-adder [4] with an index (j = 1); - elements of a cascade of one-bit full adders [3] and half-adders [4] with index (i = m – 3) are (n – 1) one-bit full adders [3] with indices (j = 1, ..., n – 1) ; - the output of the multiplier (p ₀ ) is connected to a logical zero; - the output of the multiplier (s ₀ ) is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the inputs of the multiplier (a ₀ ) and (b ₀ ); - the output of the multiplier (p ₁ ) is connected to a logical zero; - the outputs of the multiplier (s ₁ ) and (p ₂ ) are connected to the outputs (s) and (co), respectively, of a one-digit half-adder [4] with indices (i = 0, j = 0), inputs (a) and (b) of which are connected with the outputs of one-bit multipliers [1], the inputs of the first of which are connected to the inputs of the multiplier (a ₁ ) and (b ₀ ), and the inputs of the second to the inputs of the multiplier (a ₀ ) and (b ₁ ); - the outputs of the multiplier (s ₂ ) and (p ₃ ) are connected to the outputs (s) and (co), respectively, of a one-bit full adder [3] with indices (i = 0; j = 1), inputs (a), (b) and (co) of which are connected to the outputs of one-bit multipliers [1], the inputs of the first of which are connected to the inputs of the multiplier (a ₂ ) and (b ₀ ), the inputs of the second to the inputs of the multiplier (a ₁ ) and (b ₁ ), and the inputs of the third to multiplier inputs (a ₀ ) and (b ₂ ); - the outputs of the multiplier (s _k ) and (p _{k + 1} ), where (k = 3, ..., m – 2), provided (m> 4), are connected to the outputs (s) and (co), respectively, of one-bit half adders [4] with indices (i = k – 2; j = 1), respectively; - the outputs of the multiplier (s _k ) and (p _{k + 1} ), where (k = m – 1, ..., m + n – 3) are connected to the outputs (s) and (co), respectively, of one-bit full adders [3] with indices (i = m – 3; j = k – m + 2), respectively; - the output of the multiplier (s _{m + n – 2} ) is connected to the output of the logical block XOR [2], the input (a) of which is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the inputs of the multiplier (a _{n – 1} ) and (b _{m – 1} ) and the input (b) of which is connected to the output of the logical block XOR [2], the inputs of which are connected to the signals (n _A ) and (n _B ); - the output of the multiplier (p _{m + n – 1} ) is connected to the output of the logical block XOR [2], the inputs of which are connected to the signals (n _A ) and (n _B ); - the output of the multiplier (s _{m + n – 1} ) is connected to the output of the one-bit multiplier [1], the inputs of which are connected to the signals (n _A ) and (n _B ); - inputs (a) of one-bit full adders [3] with indices (i = 0, ..., m – 3; j = n – 1) are connected to outputs of logical blocks XOR [2], inputs (a) of which are connected to outputs one-bit multipliers [1], the inputs of which are connected to the inputs of the multiplier (a _j ) and (b _{i + 1} ), respectively, and the inputs (b) of which are connected to the signals (n _A ); - inputs (a) of one-bit full adders [3] with indices (i = 1, ..., m – 3; j = 2, ..., n – 2) are connected to outputs (s) of one-bit full adders [3] with indices (i – 1; j + 1), respectively; - input (a) of a one-bit full adder [3] with indices (i = m – 3; j = 1) is connected to the output (s) of a one-bit full adder [3] with indices (i – 1; j + 1); - inputs (a) of one-bit half-adders [4] with indices (i = 1, ..., m – 4; j = 1), provided (m> 4) are connected to outputs (s) of one-bit full adders [3] with indices (i – 1; j + 1). 2. The multiplier according to claim 1, characterized in that the input data of the multiplier are: - the first factor (a), represented by the bit vector a _{n – 1} , a _{n – 2} , ..., a ₁ , a ₀ , where n is the size of the vector (n ≥ 1), and _{n – 1} is the most significant (signed) bit; - the second factor (b), represented by the bit vector b _{m – 1} , b _{m – 2} , ..., b ₁ , b ₀ , where m is the size of the vector (m ≥ 1), b _{m – 1} is the most significant (signed) bit; - signal (tc _A ), made with the possibility of determining the type of the first factor (a): 0 - direct code, 1 - additional code; - signal (tc _B ), made with the possibility of determining the type of the second factor (b): 0 - direct code, 1 - additional code; the output of the multiplier is: - the first partial product (s) (the sum of partial products of factors), represented by the bit vector s _{n + m – 1} , s _{n + m – 2} , ..., s ₁ , s ₀ , where (n + m) is the size of the vector , s _{n + m – 1} - most significant (sign) bit; - the second partial product (p) (carry vector) represented by the bit vector p _{n + m – 1} , p _{n + m – 2} , ..., p ₁ , p ₀ , where (n + m) is the size of the vector, p _{n + m – 1} is the most significant (sign) bit.

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