RU2040808C1 - Device for control of regeneration in semiconductor dynamic memory unit - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has first and second clocks 1 and 2, first and second flip-flops 3 and 4, first and second bus shapers 5 and 6, local control unit 7, counters 8, decoder 9, encoder 10, register 11, AND gate 12, OR gate 13, regeneration rate control unit 32, detecting group 33 for measuring parameters of external fields. EFFECT: increased functional capabilities. 2 dwg

Description

 The invention relates to computer technology and can be used to restore information in semiconductor dynamic storage devices that are part of specialized computers that are exposed during operation to physical fields of increased intensity, for example, in information-measuring systems for monitoring the radiological situation, in x-ray and NMR tomographs, in industrial robots, etc.

 With increased intensity of the ionizing radiation and / or electromagnetic fields acting on the computer, it is first of all necessary to ensure the safety of the information recorded in the storage devices. This problem is most often solved by using semiconductor dynamic storage devices (DZU) in computer systems, in which the storage of information is periodically regenerated. At the same time, the contents of the memory cells are regenerated at predetermined and, as a rule, constant time intervals, when determining the duration of which it is necessary to take into account two contradictory circumstances.

 Firstly, when the DZU is in the regeneration mode, it cannot interact with other parts of the computer, the operation of which is interrupted for the duration of the regeneration cycle. Therefore, to reduce unproductive total costs of computer time, an increase in the time interval between regeneration cycles is required, that is, a decrease in the frequency of starting regeneration of the DZU.

 Secondly, the information stored in the memory cells of the DZU is destroyed over time, and therefore, to increase the noise immunity of the DZU and increase the reliability of its operation by ensuring the safety of the data entered into it, it is necessary to reduce the time interval between regeneration cycles, that is, to increase the cleanliness of the start of regeneration of the DZU .

 When semiconductor DZUs are exposed to ionizing radiation and / or strong electromagnetic fields, the rate of destruction of information recorded in it increases, which requires an increase in the frequency of start-up of regeneration of DZUs, leading to an additional decrease in computer performance.

 When operating a computer with a DZU in stable conditions, it is possible to select the optimal start frequency for the regeneration of the DZU, at which the required noise immunity and reliability of the DZU are achieved with a definite and constant decrease in its performance.

 In the case of exposure to computers with a semiconductor DZU of physical fields of varying intensity, maintaining a constant frequency of starting the regeneration of the DZU with increasing field intensity above the specified values can lead to disruption of the computer's performance due to a sharp decrease in the reliability of the DZU. The choice of an increased regeneration frequency of the DZU, oriented to the maximum peak values of the intensity of physical fields, leads to unjustified losses of machine time at medium and low intensity.

 Providing the ability to automatically change the start frequency of the regeneration of the DZU depending on the change in the intensity of the external physical fields acting on the computer will eliminate this drawback.

A device is known for regenerating dynamic memory, which provides an increase in computer performance both by eliminating the regeneration of memory cells located in rows that were not accessed at all when writing information to the memory, and by performing regeneration of only those previously used memory rows to which no circulation for a given period of time [1]
The known device for the regeneration of dynamic memory contains the first and second clock generators, the first and second triggers, the first and second bus drivers, the local control unit, a group of counters, a decoder, an encoder, a register, an AND element, an OR element, a delay element, a trigger group and group of elements And, the output of the first clock generator is connected to the sync inputs of the local control unit and the first trigger, the direct output of which is the output of the direct memory access (DAP) requirement, the input pre of setting the DAP is the installation input of the second trigger, the direct output of which is the channel capture confirmation output, and is also connected to the control inputs of the first and second bus drivers, with the input of the local control unit operating mode and with the reset input of the first trigger, the installation input of which is connected to the element output OR, the inverse output of the second trigger is connected to one of the inputs of the AND element, the other input of which is connected to the output of the second clock generator, and the output to one of the inputs of each of the elements AND of the group of elements AND, the other input of each of which is connected to the direct output of the corresponding trigger of the group of triggers, and the output with the counting input of the corresponding counter of the group of counters, the high-order output of each of which is associated with one of the inputs of the OR element and with one of the inputs of the encoder the outputs of which are connected to the inputs of the second bus driver, the outputs of which are the outputs of the address, the input of the recording gating is the input of the delay element, the output of which is connected to the reset input of each of triggers of a group of triggers, the installation input of each of which is connected to the corresponding output of the decoder, connected with its information inputs to the outputs of the register, the information inputs of which are address inputs, the outputs of the first bus driver are the control outputs of the device, the control inputs of which are the group of inputs of the local control unit, group the outputs of which are connected to the inputs of the first bus driver, the local control unit for its outputs of the synchronization signal and write enable signal is coupled to respective inputs of the register, the output signal is sampled to the control input of the decoder, and output the reset signal to the reset input of the second flip-flop, the reset input of the counters of each group is connected to the corresponding output of the decoder.

 However, this device does not provide, when the intensity of the external physical fields changes, an automatic change in the period of time after which the regeneration of previously used memory cells is started.

 The objective of the invention is to provide the possibility of adapting the start frequency of the regeneration of the DZU to a change in the intensity of external physical fields, which allows to increase the average effective speed of the DZU while maintaining the required noise immunity and reliability of its operation, the result of which is an increase in computer performance.

 This is achieved by the fact that in a device for controlling regeneration in a semiconductor dynamic storage device comprising first and second clock generators, first and second triggers, first and second bus drivers, a local control unit, a group of counters, a decoder, an encryptor, a register, an AND element , OR element, delay element, group of triggers and group of elements AND, the output of the first clock generator is connected to the clock inputs of the local control unit and the first trigger, the direct output of which is It is the output of the direct memory access requirement, the input of direct memory access is the installation input of the second trigger, the direct output of which is the channel capture confirmation output, and is also connected to the control inputs of the first and second bus drivers, with the input of the operation mode of the local control unit and with the reset input of the first trigger, the installation input of which is connected to the output of the OR element, the inverse input of the second trigger is connected to one of the inputs of the AND element, the other input of which is connected is connected to the output of the second clock pulse generator, and the output to one of the inputs of each of the elements AND of the group of elements AND, the other input of each of which is connected to the direct output of the corresponding trigger of the group of triggers, and the output with the counting input of the corresponding counter of the group of counters, the output of the highest order of each of which is connected with one of the inputs of the OR element and with one of the inputs of the encoder, the outputs of which are connected to the inputs of the second bus driver, the outputs of which are the outputs of the address, the input of the recording gate the input of the delay element is connected, the output of which is connected to the reset input of each of the triggers of the group, the installation input of each of which is connected to the corresponding output of the decoder connected by its information inputs to the outputs of the register, the information inputs of which are address inputs, the outputs of the first bus driver are the control outputs of the device , the control inputs of which are the group of inputs of the local control unit, the group of outputs which is connected to the inputs of the first bus form The control unit, the local control unit for its outputs of the synchronization signal and the write enable signal, is connected to the corresponding input of the register, the output of the gating signal to the control input of the decoder, and the output of the reset signal to the reset input of the second trigger, a group of measuring sensors for the parameters of external physical fields and a control code generation unit are introduced regeneration frequency, the inputs of which are connected with the outputs of the group of measuring sensors of the parameters of external physical fields, and the outputs with information inputs by all but the senior, bits of each of the counters of the group of counters, the recording permission input of each of which is connected to the corresponding output of the decoder.

 In FIG. 1 is a functional diagram of a device made according to the invention; in FIG. 2 is a timing diagram of the operation of the device in the mode of information regeneration.

 The device contains first 1 and second 2 clock generators, first 3 and second 4 triggers, second 5 and first 6 bus drivers, local control unit 7, counters 8, decoder 9, encoder 10, register 11, AND element 12, OR element 13 In FIG. 1 also shows the elements of the computer interacting with the device: the Central processor 14 and RAM 15, which is used as a semiconductor DZU. In addition, in FIG. 1 shows the output 16 of the direct memory access (DAP) requirement, the RAP grant input 17, the channel capture confirmation (PZ) output 18, the address bus 19, the memory management bus 20, the output group 21 and the input group 22 of the local control unit 7, input 23 the operating mode of the local control unit 7, the output 24 of the synchronization signal, the output 25 of the write enable signal, the output 26 of the strobe signal, the output 27 of the reset signal, the sync input 28 of the local control unit 7.

 In addition, the device contains a delay element 29, a group of triggers 30.1,30.i, 30.n, a group of elements And 31.1,31.i, 31.n, a block 32 for generating a regeneration frequency control code, a group 33 of measuring sensors of parameters of external physical fields and input 34 gating recording.

 As the local control unit 7, a local control unit of the known device can be used.

 Group 33 of measuring sensors of parameters of external physical fields may contain, depending on the operating conditions of the device, sensors of intensity α and β radiation, sensors of electromagnetic field strength, etc.

 When using sensors with an analog output, the block 32 for generating the regeneration frequency control code may contain, for example, a weighted analog adder, the inputs of which are inputs of the unit, and an analog-to-digital converter that converts the analog signal at the output of the adder to the output code of block 32.

 When using sensors with a digital output, block 32 can be made in the form of a multi-input summing device that performs weighted summing of input codes.

 If sensors with both an analog output and a digital one are used, then in this case an analog-to-digital converter can be connected to one of the inputs of the multi-input summing device, converting the output signal of the analog weight adder processing the output signals of the corresponding sensors into code.

 The device operates as follows.

 In the initial state, triggers 3, 4, 30.1 30.n are reset, and the counters 8.1 8.n are reset, and at the outputs of block 7 there are zero signal levels. The pulses from the output of the generator 2 clock pulses through the element And 12 and the group of elements And 31.1 31.n to the counting inputs of the counters 8 correspond to the addresses of the lines that were accessed when writing information to memory. The counting inputs of the counters 8.1 8.n, to which there was no access when writing information to the memory, will not be transmitted, since the corresponding elements of the And 31.1 31.n group are blocked by low signal levels at the corresponding outputs of the triggers 30.1 30.n of the group.

 When one of the counters 8.1 8.n overflows, the signal from the output of its highest order through the OR 13 element is fed to the input of the trigger 3 installation.

 At the same time, at the output of the encoder 10, the counter code 8.i is set (from 1 to n), which corresponds to the address code of the line of those RAM cells for which the storage time has expired and regeneration is required.

 A trigger 3 is installed on the leading edge of the pulse of the clock generator 1, and a direct memory access demand signal 16 is generated at its direct output. The processor 14 suspends the operation, releases the address bus 19 and provides a response signal to the input of the RAP providing 17, which sets the trigger 4, which in turn resets the trigger 3, generates a signal at the output 18 confirmation channel capture (PZ), and also opens the bus drivers 5 and 6.

 The signal from the inverted output of trigger 4 prevents the pulses of the generator 2 clock pulses from passing through the And 12 element to the inputs of the counters 8. The signal from the direct output of trigger 4 enters the local control unit 7 and allows, after completing the current cycle, accessing the main memory 15 and removing active synchronization signals device (CIA), synchronization of a passive device (CIA), received at the inputs 22 of the local control unit 7, the formation of a positive differential clock (TI) from the generator 1 clock s signal regeneration (RGN) on one of the outputs of the group 21 outputs the local control unit 7. This signal enters through the bus driver 6 into the RAM 15 and remains active during the entire regeneration time.

 According to the following clock pulses, the local control unit 7 generates at the corresponding outputs of the group of 21 outputs the signals SIA and "Input", which are received in the RAM 15 via the bus driver 6 together with the address code, the time from the output of the bus driver 5. At the same time, the line address code is sent to the information inputs of the register 11. Record in the register 11 occurs on the leading edge of the signal at the output 24 of the synchronization signal coming from the local control unit 7. In response to the “Input” signal, the random access memory 15 generates an SIRC signal, which enters block 7 through a group of 22 inputs. After that, through one TI the signal "Enter" is removed, in response to which the RAM 15 removes the signal of the SIP. On the second after this TI, the SIA signal is taken, and on the trailing edge of this pulse, block 7 generates a single pulse at the output 26 of the gating signal, which is fed to the control input of the decoder 9, thereby recording in counter 8.i corresponding to the code stored in register 11 , the code generated at the outputs of block 32 generating the regeneration frequency control code. After this, an impulse appears at the output of the reset signal 27, resetting trigger 4. The signals of RGN and PZ are removed, the regeneration cycle is completed.

 Thus, regeneration can be carried out for any line of RAM 15. If during the operation of the device none of the counters 8 is full, i.e. Since the information storage time did not work out for any line, the device operates as follows.

 In the access mode to the RAM 15, the processor 14 sets the memory address code on the bus 19, and on the bus 20 the control signals are generated that enter the local control unit 7 by the group of 22 inputs: the channel synchronization signal of the passive device (CCI), the channel selection signal of the external devices (HLC). The least significant bits of the address code, which are the address code of the line by the signal from the output 24 of the local control unit 7, if there is an enable signal at its output 25, the write enable signal is written to the register 11. A write-inhibit signal appears at the output of the local control unit 7 when the processor 14 is not RAM 15, and to the registers of external devices. In this case, no signal is generated at the output 26 of the local control unit 7.

Since when accessing the RAM 15, all memory cells are regenerated with the specified address of the line, then at the end of the cycle of accessing the RAM 15 by the signal from the output 26 of the local control unit 7 of the signal from the output of the decoder 9, the code from the outputs of block 32 is entered into the counter 8.1, the sequence number of which coincides with the code row address stored in the register 11. The request for the regeneration of cells RAM 15 with the address line can come from the output of the counter 8, only after a time period T _RGN Rege era tio, provided that during that time the processor 14 no longer appeal to the cells with the same row address.

· (2^k-1-N) где f₂ частота импульсов на выходе генератора 2 тактовых импульсов;
К разрядность счетчиков 8.1 8.n;
N (K-1) разрядный код на выходе блока 32 формирования кода управления частотой регенерации.The current counter codes 8.1 8.n determine the permissible information storage time for each line of RAM 15, which cannot exceed the value determined by the expression
T _WGN =

· (2 ^k-1 -N) where f ₂ is the pulse frequency at the output of the generator 2 clock pulses;
K digit capacity of the counters 8.1 8.n;
N (K-1) bit code at the output of block 32 generating the regeneration frequency control code.

 The code of the number N is generated by the regeneration frequency control code generating unit 32, which mathematically processes the information on the current values of the parameters characterizing the intensity of the external physical fields acting on the ROM coming from the outputs of the group 33 measuring sensors. In the simplest case, the code of the number N is a linear combination of the values of the measured parameters, reduced to a single scale using weight summation. It is only important that an increase in the current value of at least one parameter (while the current values of the other parameters remain unchanged) leads to an increase in the number N.

 At the same time, there are no fundamental restrictions on the implementation of more complex functional dependences of the number N on the measured current values of the parameters characterizing the intensity of external physical fields acting on the DZU. In particular, functional converters can be installed at the inputs and outputs of block 32, or block 32 itself can be implemented as a specialized computer that performs more complex input data processing.

 As follows from the above formula, with an increase in the number N due to an increase in the intensity of external physical fields acting on the ROM, the value of the permissible information storage time for each line of RAM 15 decreases, that is, the frequency of regeneration of the memory cells of the ROM increases.

 When recording information in any memory location 15 with a signal from the input 34 of the recording gating input to the trigger inputs of the group triggers 30.1 30.n through the delay element 29, the corresponding trigger is set to a single state, since it has a high level signal generated by the decoder at the installation input 9. The installation of the trigger 30.i of the group occurs during the initial recording of information, upon repeated access to the cells of the RAM 15 with the same address of the line, the trigger 30.i remains in the established state In fact, the delay element 29 also provides coordination on the load characteristics of the processor line 14 with the sync inputs of the triggers 30.1 30.n of the group.

 Thus, the regeneration of dynamic memory cells, in which information was not entered, is excluded from the regeneration cycle.

Claims (1)

 DEVICE FOR REGENERATION CONTROL IN A SEMICONDUCTOR DYNAMIC REMEMBER DEVICE, containing the first and second clock generators, the first and second triggers, the first and second bus drivers, the local control unit, a group of counters, a decoder, an encoder, an AND element, an element, And, , a group of triggers and a group of elements AND, the output of the first clock generator is connected to the clock inputs of the local control unit and the first trigger, the direct output of which is the output of the requirement direct memory access, direct access to memory access input is the installation input of the second trigger, the direct output of which is the channel capture confirmation output, and is also connected to the control inputs of the first and second bus drivers, with the input of the operating mode of the local control unit and with the reset input of the first the trigger, the installation input of which is connected to the output of the OR element, the inverse input of the second trigger is connected to one of the inputs of the AND element, the other input of which is connected to the output of the second generator torus of clock pulses, and the output to one of their inputs of each of the elements AND of the group of elements AND, the other input of each of which is connected to the direct output of the corresponding trigger of the group of triggers, and the output with the counting input of the corresponding counter of the group of counters, the output of the highest level of each of which is connected with one of the inputs of the OR element and with one of the input of the encoder, the outputs of which are connected to the inputs of the second bus driver, the outputs of which are the outputs of the address, the input of the recording gate is the input of the back element Arms, the output of which is connected to the reset input of each of the triggers of the group, the installation input of each of which is connected to the corresponding output of the decoder, connected by its information inputs to the outputs of the register, the information inputs of which are address inputs, the outputs of the first bus driver are the control outputs of the device, the control inputs which is the group of inputs of the local control unit, the group of outputs of which is connected to the inputs of the first bus driver, the local unit control board with its outputs the synchronization signal and the recording permission signal is connected to the corresponding inputs of the register, the output of the gating signal to the control input of the decoder, and the output of the reset signal to the reset input of the second trigger, characterized in that a group of measuring sensors of parameters of external physical fields and a formation unit are introduced into it a control code for the regeneration frequency, the inputs of which are connected to the outputs of the group of measuring sensors of the parameters of external physical fields, and the outputs with information inputs Odes of all but the senior bits of each of the counters of the group of counters, the recording permission input of each of which is connected to the corresponding output of the decoder.

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