RU170412U1 - GENERATOR OF A RANDOM SEMI-MARKOV PROCESS WITH SYMMETRIC DISTRIBUTION LAWS - Google Patents

Abstract

The utility model relates to the field of computer technology and can be used to build simulation models of systems operating under random disturbances, configure and operate various automation devices. The technical result obtained in this technical solution is to simplify the random semi-Markov process generator by reducing the number of block cells memory, which sets the duration of the simulated random process, 2 times and reduce their capacity. achieved by the fact that in the generator of a random semi-Markov process with symmetric distribution laws, containing a synchronization unit, the first output of which is connected to the synchronization input of the first memory register, the output of which is the generator output, the output of the first memory register is connected to the information input of the second memory register, the output of which is connected to the first address input of the first memory block, the second address input of which is connected to the output of the third memory register, the information input of which is connected with the sensor output of the evenly distributed random numbers, the output of the first memory block is connected to the information input of the first memory register, three keys, the OR-NOT element, the second memory block, counter, key block, the OR element, the first input of which is connected to the second output of the synchronization block, the output of the OR element is connected to the input "Poll" of the sensor of uniformly distributed random numbers, the output of which is connected to the information input of the key block, the counter, the counting input of which is connected to the first input of the synchronization block, the output of the counter The input is connected to the input of the OR-NOT element, the output of which is connected to the control inputs of the first, second and third keys, the information inputs of the first and second keys are combined and connected to the third input of the synchronization block, the fourth output of which is connected to the information input of the third key, the output of which is connected to the synchronization input of the third memory register, the output of the first key is connected to the second input of the And element, the output of the second key is connected to the control input of the key block and to the synchronization input of the second register memory, the adder-subtracter is introduced, the output of which is connected to the information input of the counter, and the control input is connected to the highest bit of the key block, the first input of the adder-subtractor connected to the output of the memory block, and the second input is the input of the generator through which the required average value is input duration of intervals. 1 ill.

Description

The utility model relates to computer technology and can be used to build simulation models of systems operating in conditions of random disturbances, configure and operate various automation devices.

A known generator of random intervals with symmetric distribution laws (Utility Model Patent No. 156596 of October 16, 2015), whose operation is based on converting a random number distributed but given a probabilistic law, into a random interval.

A known generator of a random semi-Markov process (SU 1377853 from 08/07/1986) is known, the operation of which is based on converting a random number distributed according to a given probabilistic law into a random interval.

The closest in technical essence to the proposed technical solution is a random semi-Markov process generator containing a synchronization unit, the first output of which is connected to the synchronization input of the first memory register, the output of which is the generator output, the output of the first memory register is connected to the information input of the second memory register, the output of which connected to the first address input of the first memory block, the second address input of which is connected to the output of the third memory register, information whose input is connected to the output of the sensor of uniformly distributed random numbers, the output of the first memory block is connected to the information input of the first memory register, three keys, an OR-NOT element, a second memory block, a counter, a key block, an OR element, the first input of which is connected to the second the output of the synchronization block, the output of the OR element is connected to the input "Poll" of the sensor of uniformly distributed random numbers, the output of which is connected to the information input of the key block, the output of which is connected to the address input of the second memory block whose output is connected to the output of the preset counter, the counting input of which is connected to the first input of the synchronization unit, the output of the counter is connected to the input of the OR-NOT element, the output of which is connected to the control inputs of the first, second and third keys, the information inputs of the first and second key are combined and connected to the third input of the synchronization unit, the fourth output of which is connected to the information input of the third key, the output of which is connected to the synchronization input of the third memory register, the output is of the key is connected to the second input of the And element, the output of the second key is connected to the control input of the key block and to the synchronization input of the second memory register (SU 1377853 from 08/07/1986).

The disadvantage of the prototype, which manifests itself in the modeling of random intervals distributed according to the distribution laws symmetric with respect to mathematical expectation, is the high cost due to the use of an unreasonably large memory block and a large capacity of memory cells.

To achieve high accuracy in modeling the probability distribution of intervals, the number of memory cells should be selected large enough. This significantly increases the cost of the device, since a memory block is the most expensive element of stochastic devices of this type, and the cost of manufacturing and programming memory blocks increases monotonically with an increase in the number of memory cells.

The technical result obtained in this technical solution is to simplify the random semi-Markov process generator by reducing the number of memory block cells in which the duration of the simulated random process is set by 2 times and reducing their bit capacity.

The technical result is achieved by the fact that in the generator of a random semi-Markov process with symmetric distribution laws containing a synchronization unit, the first output of which is connected to the synchronization input of the first memory register, the output of which is the generator output, the output of the first memory register is connected to the information input of the second memory register, the output of which connected to the first address input of the first memory block, the second address input of which is connected to the output of the third memory register, information the path of which is connected to the output of the sensor of uniformly distributed random numbers, the output of the first memory block is connected to the information input of the first memory register, three keys, the OR-NOT element, the second memory block, counter, key block, the OR element, the first input of which is connected to the second output synchronization block, the output of the OR element is connected to the "Poll" input of a uniformly distributed random number sensor, the output of which is connected to the information input of the key block, the counter, the counting input of which is connected to the first input of the sync block onization, the counter output is connected to the input of the OR-NOT element, the output of which is connected to the control inputs of the first, second and third keys, the information inputs of the first and second keys are combined and connected to the third input of the synchronization block, the fourth output of which is connected to the information input of the third key, the output of which is connected to the synchronization input of the third memory register, the output of the first key is connected to the second input of the And element, the output of the second key is connected to the control input of the key block and to the synchronization input and the second memory register, an adder-subtracter is introduced, the output of which is connected to the information input of the counter, and the control input is connected to the highest bit of the key block, the first input of the adder-subtractor connected to the output of the memory block, and the second input is the input of the generator through which the required average value of the duration of the intervals.

The introduction of new features and the relationships between them that distinguish the claimed solution from the prototype, in combination, makes it possible to simplify the generator by using a memory unit with half the number of cells with fewer bits.

The essence of the technical solution lies in the fact that when modeling random intervals distributed according to probabilistic laws symmetric with respect to mathematical expectation (truncated Gaussian, Cauchy, etc.), there is no need to store all numbers from the range of possible values in the memory block, but enough -first, center them and, secondly, leave only half of the centered numbers, for example positive. The first measure allows you to reduce the capacity of the cells of the memory block, and the second - the number of cells of the memory block in half.

Each of these centered positive numbers x _{i is} written in m _i cells of the memory block

m _i =] 2 ^N-1 p _i [,

where p _i is the probability of occurrence of the number x _i in accordance with the distribution law;

] • [- rounding to the integer;

N is the bit depth of the sensor evenly distributed random numbers;

N-1 - bit width of the address bus of the memory block.

In total, the memory block contains 2 ^N-1 cells, i.e. 2 times less than the total number of 2 ^N combinations at the sensor output of equally probable random codes. For half the combinations of equally probable codes (at zero level in the high order) random numbers selected from the memory block correspond to the positive half of the centered distribution, for the other half of the codes (at the unit level in the high order) these numbers are represented in the reverse code and correspond to the negative half centered distribution. After summing the obtained numbers with the mathematical expectation, the result is numbers with a given probability distribution, with which random intervals are modeled.

In FIG. 1 shows a functional diagram of a generator. The generator of a random semi-Markov process with symmetric distribution laws consists of a synchronization unit 1, a sensor 2 evenly distributed random numbers, registers 3-6, an OR element 7, keys 8-10, a key block 11, a memory block 12, an adder-subtractor 13, a register 14 , element OR NOT 16. Block 1 contains a clock and a counter similar to the prototype,

The adder-subtractor 13, depending on the signal at the control input, performs addition or subtraction. If the control input of the adder-subtracter is zero, then it adds up two codes entering its inputs, if the control input is unity, the adder-subtracter subtracts from the number received at the second input the number received at the first input. (Alekseenko A.G., Shagurin I.I. Microcircuitry: Textbook for universities under the editorship of I.L. Stepanenko. - M .: Radio and communications, 1982. - 416 p. (P. 124)).

The generator operates as follows.

, так как по истечении случайного количества тактов, распределенного по закону W(I), процесс из всякого i-го состояния обязательно переходит в новое состояние, номер которого не равен i.Let a random process with n states be modeled. In each of the states, the process can contain I clocks, and I is a discrete random variable with a probability distribution W (I). The probabilities of transition from the ith state to the kth are given by the matrix {P _ik }, and

, since after a random number of clock cycles distributed according to the law W (I), the process from any i-th state necessarily goes into a new state, the number of which is not equal to i.

The specified probability of the transition of the simulated process from one state to another is provided by the special design of the memory unit 4. The duration of the process conditions, subject to the required distribution law, is formed by counting the number of clock cycles of the generator in the counter 14 and comparing the calculated number with the number distributed according to the given law generated at the output of the adder-subtractor 13.

в каждой группе пропорционально с коэффициентом 2^m значениям вероятностей P_ik. расположенных в i-й строке матрицы {Р_ik}. Другими словами, P_ik=a_ik*2^m. В ячейки первой группы записаны номера "1", в ячейки второй группы - номера "2" и т.д. до n. Всего в блоке 4 памяти содержится n строк.Each i-th line of memory block 4 contains 2 ^m cells, where m is the bit capacity of a random number at the output of sensor 2, and each of them is designed to store an integer not exceeding n. All 2 ^m cells are divided into n groups in such a way that the number of cells a _ik ,

in each group proportionally with a coefficient of 2 ^{m to} the probability values P _ik . located in the i-th row of the matrix {P _ik }. In other words, P _ik = a _ik * 2 ^m . The cells of the first group contain the numbers "1", the cells of the second group contain the numbers "2", etc. to n. In total, block 4 of the memory contains n lines.

The signal from block 10 opens the key block 11 and submits a random code from the sensor 2 of evenly distributed random codes to the memory block 12. If the random code, which is the address of some cell of the memory block 12, has a zero level in the high order, then the read code from the memory block 12 arrives to the first input of the adder-subtractor 13 and is added to the code of the mathematical average value of the duration of the intervals (input 16), because at the control input of the adder-subtractor 13 there is a zero level. If a unit is present in the high order of the address, then the number read from the memory block 12 is sent to the adder-subtractor 13 and subtracted from the code of the average value of the duration of the intervals, since there is a unit level at the control input of the adder-subtractor.

A random number from the output of the adder-subtractor 13 is entered in the counter 14, where it is converted into a time interval.

Obviously, the time intervals T _i between the zeroing signals of the counter 14 will be random and distributed according to the distribution law identical to the distribution law of the codes x _i recorded in the memory unit 12.

Thus, the introduction of new features allows you to generate a random semi-Markov process using a generator with a memory unit that has half the number of cells than in the prototype, as well as their lower capacity.

Register 3 is designed to store a random number, which is the numbers (address) of the column of the memory block 4. Register 6 is intended for storing the number (address) of a line of memory block 4. Register 5 stores the state number of the generated process read from the matrix memory.

At the initial time before the arrival of the first clock signal from block 1, register 5 is set to the initial state, registers 3, 6 and counter 13 are set to zero. "1" appears at the output of the OR-NOT element and keys 8-10 are open. Block 1 begins to produce clock signals at its outputs. The signal from the second output of block 1 through the OR element 7 initiates the operation of the random number sensor 2, at the output of which an m-bit binary number r _t1 = С _t1 2 ^m appears. The signal from the fourth output of block 1 through the public key 8 initiates the recording of the value With _t1 in the memory register 3. The value of C _t1 ^' is the column number of the memory block 4. The signal from the third output of block 1 through the public key 10 initiates an entry in register 6 stored in register 5 (according to the initial setting, this number is i). By the column number C _t1 and the row number (i) in the memory block 4, a cell is excited whose contents will be equal to the state number of the generated process. Assume that this state has number k. The probability of the kth state, provided that the register i contains the number i, will be equal to P _ik . Indeed, the choice of the kth state number from the matrix memory means that the value of C _t falls into the kth group of cells of the ith row. The kth group contains a _ik cells.

The probability that a number uniformly distributed in the interval [0-1] takes one of a _ik values is equal to a _ik / 2 ^m = P _ik .

Simultaneously with the selection of the status number from the memory unit 4, the signal from the third output of the unit 1 opens the key unit 11 and, through the public key 9 and the OR element 7, initiates the operation of the random number sensor 2. The random number C _t1 through the key block 11 is input to the memory block 12, where it is converted to the number 1, which is entered in the subtracting counter 14. At the input of the OR-NOT 15 element, "0" appears and the keys 8-10 are closed.

The signal from the first output of block 1 provides a record of the status number of the output register 5 selected from the memory block 4, the bit outputs of which are the output of the entire device. At the same time, the same signal is fed to the input of the counter 14 and decreases its content by one. At the fifth clock cycle of the clock generator, the counter-divider of synchronization block 1 returns to the initial state, and the first clock cycle of the random semi-Markov process generator with symmetric distribution laws ends.

The operation of the generator on the next step depends on the value of the number contained in counter 14. If the contents of the counter are zero, then “1” is present at the output of the OR-NOT 15 element, keys 8-10 are open, and the generator operates in the described manner. If the contents of the counter are greater than zero, then “0” is stored at the output of the OR-NOT element and keys 8-10 are closed. The signal from the second output of the control unit through the OR element 7 initiates the operation of the sensor 2. However, the signal from the fourth output of the unit 1 through the private key 8 does not pass and the contents of register 3 remains the same as in the previous clock cycle. The signal from the third output of block 1 also does not pass through the private key 10 and therefore, firstly, the contents of the register 6 remains the same, and secondly, a random number from the output of the sensor 2 through the block 11 of the keys does not pass to the address input of the block 12 and does not influence on the contents of the counter 14. The signal from the first output of block 1 reduces the contents of the counter 14 by one and initiates the recording in the register 5 of the contents of the memory cell of the block 4 selected on this clock.

Since the column and row numbers stored in registers 3, 5 have not changed, the reading will occur from the same cell as in the previous clock cycle, which means that the status number of the generated process will not change.

The state of the simulated process at the output of the device will remain unchanged as long as the contents of the counter 14 is greater than zero. Since the number entered in counter 14 is distributed according to the law W (I), the number of clock cycles at which the state of the modeled process will be unchanged is also distributed according to the law W (I).

The technical and economic effect of using a utility model is determined by the use of a smaller memory unit, and therefore, cheaper.

Claims (1)

A random semi-Markov random process generator with symmetric distribution laws, comprising a synchronization unit, the first output of which is connected to the synchronization input of the first memory register, the output of which is the generator output, the output of the first memory register is connected to the information input of the second memory register, the output of which is connected to the first address input of the first a memory unit, the second address input of which is connected to the output of the third memory register, the information input of which is connected to the output of the sensor randomly distributed random numbers, the output of the first memory block is connected to the information input of the first memory register, three keys, an OR-NOT element, a second memory block, a counter, a key block, an OR element, the first input of which is connected to the second output of the synchronization block, the output of the OR element connected to the "Poll" input of a uniformly distributed random number sensor, the output of which is connected to the information input of the key block, a counter, the counting input of which is connected to the first input of the synchronization block, the output of the counter is connected to the input OR-NOT element, the output of which is connected to the control inputs of the first, second and third keys, the information inputs of the first and second keys are combined and connected to the third input of the synchronization unit, the fourth output of which is connected to the information input of the third key, the output of which is connected to the synchronization input of the third memory register, the output of the first key is connected to the second input of the AND element, the output of the second key is connected to the control input of the key block and to the synchronization input of the second memory register, characterized in that an adder-subtractor is inserted into it, the output of which is connected to the counter, and the control input is connected to the highest bit of the key block, the first input of the adder-subtractor connected to the output of the second memory block, and the second input is the input of the generator through which the required average interval duration value.

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