RU1780192C - Device for transmission of digital information - Google Patents

Abstract

The inventive device contains n coding blocks 2, a frequency divider 4, a pulse shaper 5, a counter 6, a decoder 8, two groups of elements HE 9 and 12, two groups of triggers 10 and 13, an OR element 11. 3 ill.

Description

(L

with

00

about

tshl

4D Yu

The invention relates to the transmission of digital information and can be used, for example, in telegraph and telephone communications.

A device for transmitting short messages containing modulo two adders, information shift registers, timing shift registers, counters, triggers, decoders, valves, a signal output signal isolation device, an initial state input circuit (ed. St. USSR part 431638, CL H 04 L3 / 00).

The disadvantage of this device is that it cannot provide the transmission of continuous streams of digital information from several sources,

The closest technical solution to the proposed one is a device for transmitting discrete messages, comprising two valves, an information shift register, five adders modulo two, two timing shift registers, two input combinations of the original combination, a decoder, a control unit implemented on a master oscillator, five valves, three OR elements, five triggers, three counters, a switch, a decoder, and pseudo-random sequence generators, each of which is implemented on two adders per module two valve and shift register (USSR SU, № 1,195,471, cl. H 04 L 17/02),

The disadvantages of this device are the obligatory separation in the work cycle of inputting information and reading it into the communication channel and the cumbersome construction structure.

The aim of the invention is to increase noise immunity by arranging the transmission of continuous streams of digital information from multiple sources and simplifying the construction structure.

This goal is achieved by the fact that in the device for transmitting digital information containing the first group of triggers, the OR element, counter and decoder, an additional second group of triggers, the first and second groups of elements NOT, the first and second coding blocks, a frequency divider and a pulse shaper are introduced the output of which is connected to the R input of the counter, the outputs of which are connected respectively to the inputs of the decoder, the outputs of which are connected to the inputs of the corresponding first and second groups of elements NOT, the outputs of which are connected the R and C inputs of the first and second trigger groups, respectively, whose D inputs are connected to the outputs of the first and second coding blocks, respectively.

the first control inputs of which are connected and connected to the input of the pulse shaper and to the output of the frequency divider, the input of which is connected to the C-input of the counter; the outputs of the first and second triggers are connected to the inputs of the OR element; the second control inputs of the first and second coding blocks are combined and are the control input of the device,

0 information inputs of which are information inputs of the first and second coding blocks; the input of the frequency divider is the clock input of the device, the output of which is the output of the OR5 element,

Fig. 1 is a functional diagram of a device for transmitting digital information; figure 2 - timing diagrams; Fig. 3 is a flow chart of a device for transmitting digital information,

explaining his work; FIG. 4 is an algorithm

work of the encoder

N51530060 explaining the organization of the code,

obtained at the output of the coding device 5,

A device for transmitting digital information contains encoded blocks 2, a frequency divider 4, a pulse shaper 5, a counter 6, a decoder 8, the first and

0 second groups of elements NOT 9 and 10, first and second groups triggers 10 and 13 element OR 11,

Figure 1 also indicates the information inputs 1 of the device, controlling 3

5 and clock 7 inputs, output 14 of the device.

In Fig. 2, the corresponding signals denote the following signals: a - signal at the clock input 7, b - signal at the output of the frequency divider 4, c - signal at the output

0 of the first coding unit 2, g - signal

the output of the second coding unit 2, d signal at the output of the third coding

block 2, the g-signal at the output 14 of the device.

Information inputs of the device 1

5 are connected respectively to the information inputs of the first and second coding blocks 2. The first control inputs of the first and second coding blocks 2 are combined with the control input 3 of the device.

0 The second control inputs of the first and second coding blocks 2 are combined with the output of the frequency divider 4 and the input of the pulse shaper 5. The output of the 5 pulse shaper is connected to the R-input

5 of counter 6, the C-input of counter 6 is connected to the input of the frequency divider 4 and the clock input 7. The outputs of the counter 6 are connected respectively to the inputs of the decoder 8. The outputs of the decoder 8 are connected respectively to the inputs of the first and second groups

elements HE 9 and 12. The outputs of the first and second groups of elements HE 9 and 12 are connected respectively to the C and R inputs of the first and second groups of triggers 10 and 13. The D inputs of the first and second groups of triggers 10 and 13 are connected respectively to the outputs of the first and second coding blocks 2. The outputs of the first and second groups of triggers 10 and 13 are connected respectively to the inputs of the OR element 11. The output of the OR element 11 is connected to the output 14 of the device.

A stabilized frequency K fraxT is applied to clock input 7, where K is the number of channels from which digital information is transmitted.

In the frequency divider 4, a division of the clock frequency from clock input 7 to the number of channels K is organized.

Counter 6 is a binary counter that is triggered by the trailing edges of the KfiaKT frequency pulses.

As a shaper of 5 pulses, a shaper along the leading edge, two inverters and a 134 HLZ microcircuit were used.

As coding blocks 2 used devices on autosw. USSR No. 1530060, class H 03 M 7/00.

All coding blocks 2 are built on time-code counters of the same size.

The frequency input of the time code counters of the coding blocks 2 is applied to control input 3 (see ed. St. INh 1530060). The first control input in each coding unit 2 (autosw. No. 1530060) is designated as the third control input 14.

The second control input in each coding unit 2 (autoswitch Mg 1530060) is designated as the second control input 13. The first control input 14 is also indicated there, but it is not shown in Fig. 1 of this description, since it is specified in the named description so that the logical unit level is brought to the first control input 14.

The operation of the device is as follows.

When the power is turned on at the initial moment of time, the first and second coding blocks 2 (the first shift registers and second triggers in coding blocks 2 - see description of the invention to auth. No. 1530060), counter 6, the first and second groups of triggers 10 and 0 are reset to zero. 13 (zeroing of the first and second coding blocks 2, counter 6, first and second groups of flip-flops 10 and 13 is not shown in FIG. 1). The information inputs of the first and second coding blocks 2 are fed continuous

digital microforgation streams from K sources. In the first and second cadres C11x blocks 2, the streams are tsifropoy and, chofgi.; |;: 1 m ::, you will transform trerypio.) S zzkodprozipyy zkvmvalenty information. On the leading edge of the pulse from the output of the frequency divider 4, the output of each coding unit 2 receives one bit of the encoded information equivalent. On the leading edge of that

on the other hand, a pulse is generated at the output of the pulse shaper 5, resetting the counter 6. After this, a logical zero signal of read permission of the first coding unit 2 is organized by the rear edge of the first clock pulse from the input 7 of the decoder 8, according to which the information bit from the first coding unit 2 is recorded in the first group of triggers 10

and appears on the first pass of the OR element 11 and the output 14 of the device. On the trailing edge of the second clock pulse at the second output of the decoder 8, a read enable signal of the second coding unit 2 is generated, the first trigger 10 from the first group is reset to zero, the information bit from the output of the second coding unit 2 is read to the output 14 of the device. Similarly on the trailing edges of the third,

fourth, ... Kth clock pulses to the output of the device 14 are read the bits of the encoded equivalents of information from the third, fourth, respectively,. Whom you are coding, their blocks 2. On the front

to the edge of the next pulse from the output of the frequency divider 4, the entire operation cycle is repeated first; second bits of encoded information equivalents are sequentially read to the device output 14

To sources. On the leading edges of all subsequent pulses from the output of the frequency deltel 4 to the output 14 of the device, third, fourth, etc. are sequentially read. bits of encoded equivalents of K information sources.

Figure 2 on a time chart shows an example of the organization of the transmission of information from three sources, when

information from the first source in the first coding block is converted to code 11000100111 (see, Fig. 2c), from the second source in the second coding block to code 00011100010 (see Fig. 2d), from the third source S to the third, encoding block - into code 01110000110 (see fig.2d).

In Fig. 3, the following conventions are adopted in the operation algorithm of a device for transmitting digital information: D frequency divider 4; KB - coding unit 2: MF - counter 6; N-1 ... K.

According to the algorithm of the device for transmitting digital information on the leading edge of the first pulse, MF is reset at the output D, and a logical unit appears at the output of the first KB (see, Fig. 2c), and a logical zero appears at the output of the second KB (see Fig. 2d), at the output of the third KB - logical zero (see Fig.2d). Received at the outputs of three KB combination 100 will be kept until the leading edge of the second pulse at output D (see Fig. 26). After resetting the SC to the trailing edge of the first clock pulse (see Fig. 2a), at the first output of the decoder 8, arrange the reading separation of the first KB, to the first trigger 10 from the first group and then the unit bit is read to the device output, along the trailing edge of the second clock pulse (see Fig. 2a), the zero bit is read at the output of the device when a read permission appears at the second output of the decoder 8, along the trailing edge of the third clock pulse (see Fig. 2a), a zero bit is read at the output of the device when a read permission appears at the third output of the decoder 8. Next, the entire cycle is repeated first — a combination of 101 appears at the outputs of three KB at the output edge of the third pulse D at the outputs of three KB, and one bit is read to the device output at the trailing edge of the fourth clock pulse, along the trailing edge of the fifth clock pulse - bit zero, on the trailing edge of the sixth clock pulse - bit unit. The operation cycle is repeated at the third, fourth and all subsequent pulses at the output D.

In Fig. 4, the following conventions are adopted in the algorithm of operation of the coding unit:

K.V. - code times at the output of the counter 11,

RG1 is the first shift register 1,

RG2 - second shift register 2,

P.F, is the leading edge of the pulse at input 15,

Z.F. trailing edge of the pulse at the input 15.

For freezing, hsdlruy.s is received, and at the input of the coding unit, the sequence — 1011 (see timing diagrams in FIG. 2 in the description of the Coding device by autosw. No. 1530060) —or two pulses, and the leading edge of the first pulse comes when 01011 is ready for the outputs of the time code counter, and the leading edge of the second pulse comes when 00101 is ready for the outputs of the time code counter. 101011 is written to the RG1 register (the sixth-order logical unit is added to the time code Register RG1),

further along the rising edge of the first clock, the combination 101011 is written to the register RG2. After the sixth bit of the register RG2 has arrived, the logical unit nullifies the register RG1, and the register RG2 transfers to the shift mode with the logical unit entered. Further along the leading edge of the second clock pulse at the output of the sixth bit of the register RG2 - the output of the coding block - a logical zero appears, the third clock pulse - a logical unit, the fourth - a logical zero, then the logical unit, the sixth - a logical unit remains, in the seventh - the logical unit remains, Between the seventh and eighth clock pulses the first input pulse is reset to zero - a gate of the trailing edge is formed, due to which with the arrival of the eighth clock

the pulse of the register RG2 is zeroed and a logic zero appears at the output of the coding block, which is held there until the sixteenth clock pulse arrives, since the leading edge of the second input pulse appears between the fifteenth and sixteenth pulses and a new combination 100101 is written to the register RG1 Upon the arrival of the sixteenth clock pulse, the combination 100101 is recorded in the register RG2. A logic unit appears at the output of the encoding block, the register RG2 is put into shift mode, and a logic seventeen clock pulse appears at the output of the encoding block

zero, an eighteenth clock pulse remains a logical zero, a nineteenth clock pulse appears as a logic unit, a twentieth clock pulse is reset to zero, a twenty-first clock pulse again appears a logical unit and is held at the output of the coding block until it arrives thirtieth pulse, since between the twenty-ninth and thirtieth clock pulses the leading edge of the second input pulse arrives, register RG2 is reset and, at the beginning of the seventeenth clock pulse, the output of the coding block logical zero is stored.

The proposed device for transmission

digital information allows:

1) to ensure the transmission of continuous streams of digital information from several sources:

2) to simplify the structure of building a transmitter of digital information from several sources.

3) to ensure the transmission of information encoded with great accuracy from several sources.

Claims (1)

SUMMARY OF THE INVENTION A device for transmitting digital information comprising a first group of triggers, an OR element, a counter and a decoder, characterized in that, in order to increase the noise immunity, a second group of triggers, a first and a second group of elements NOT, a first and a second group of coding blocks, a divider frequency and pulse shaper, the output of which is connected to the R-input of the counter, the outputs of which are connected to the corresponding inputs of the decoder, the outputs of which are connected to the inputs respectively howl and the second group of elements 14E. the outputs of which are connected to the R and C inputs of the first and second trigger groups, respectively. The D-inputs of which are connected to the outputs of the first and second groups of coding units, the first control inputs of which are combined and connected to the input of the pulse former and to the output of the frequency divider, the input of which is connected to the C-input of the counter, the outputs of the first and second trigger groups are connected to inputs of the OR element, the second control inputs of the first and second groups of coding blocks are combined and are the control input of the device, the information inputs of which are the information inputs of the first and second groups of code purifying, input frequency divider units is the clock inputs of the device, the output of which is an output of OR. /,Z,J,f,J,/.r J.//J /..J,//,J /.f,J/.J//J//J//J Itpllltfltltli r-yrn o, n 1. 0 0 0 and П ПП ППП 1 HiF fiHv 0 I t. 01 Fig2