RU156778U1 - RECONFIGURABLE COMPUTER SYSTEM - Google Patents

Abstract

A reconfigurable computing system comprising a master server 2 connected through an EtherNet control switch 1 of a computing system via a network interface 3 and EtherNet network interfaces 7, ..., 7 with a group of K slave computing nodes 4, ..., 4, each of which contains a group of N reconfigurable computing devices 13, ..., 13, containing a group of M computing FPGAs 20, ..., 20 each, and computers 8 with a PCIe bus on the motherboard, characterized in that an Ethernet monitoring network switch is additionally introduced into it computational system 5, connected via EtherNet 6 network interfaces to the master server 2 and to a group of K Ethernet monitoring ports 18, ..., 18 of the known computing nodes 4, ..., 4, each of which 4 has an additional two-port interface board 9 connected via an internal high-speed serial interface PCI-Express 10 to computer 8 of the slave computing node 4, an Ethernet monitoring switch 14 of the slave computing nodes 4, connected to computer 8 of the slave computing node 4 via the EtherNet 12 network interface, to the network Ethernet monitoring unit 18 and a group of N Ethernet monitoring ports 26, ..., 26, PCI Express 11 switch of the slave computing node 4, and the input port of the PCI Express 11 switch is connected to the interface card 9 with a high-speed serial PCI-Express 15 interface, and the output ports are connected N ports 16, ..., 16 of a high-speed serial PCI-Express interface of a group of N reconfigurable computing devices 13, ..., 13, each of which 13 additionally includes a PCI-Express 30 switch mode control unit, an interface FPGA 22 , pa

Description

The utility model relates to the field of computer engineering, in particular, to reconfigurable high-performance computing systems with high reliability, using direct interaction of computing FPGAs with processors via high-speed serial PCIe channels, the possibility of increasing the computing power of the reconfigurable part and combining computing FPGAs into various structures, and can be used to solve labor-intensive tasks and process large information arrays and streams, using zovaniem parallelization and pipelining of computational processes.

Reconfiguration is a change in architecture and / or data processing algorithm that allows you to organize various sequential (pipeline), parallel and / or serial-parallel data processing schemes within a given group of computing tools.

Computing nodes are computing devices, consisting, as a rule, of a universal computing tool that controls the work of a group of special high-performance computing tools.

A reconfigurable computing module is a single-board education containing computing FPGAs, connected by links and connected to some interfaces.

Reconfigurable computing devices are a combination of reconfigurable computing modules connected to a single control center inside a computing node.

A reconfigurable FPGA FPGA system from the DINI Group (http://www.dinigroup.com/product/data) is known, which contains compute nodes DNK7_F5_8_Cluster, each of which contains a universal computer connected to the EtherNet control network and eight compute modules DNBFC_K7F5_PCIe in of five Xilinx Kintex-7 410T FPGAs that are installed on the motherboard in PCIe slots and are connected to the Xeon E3-1275 processor via Xilinx Virtex-6 system FPGAs that implement PCIe x4 bridges on each computing module and configure FPGA computing. Computing FPGAs of the module are connected by a ring serial 46-bit channel, and one of them is still connected to the system FPGAs by a 78-bit bus, which provides data exchange between computing FPGAs and the processor.

The disadvantages of this computing system are the lack of the ability to combine computing FPGAs in a single field, the low maximum data exchange rate between computing FPGAs and the control processor, a limited system for increasing the computing power of the reconfigurable part on FPGAs, two different types of projects for computing FPGAs and insufficiently high reliability.

The reasons hindering the achievement of the technical result are the presence of communication between computing FPGAs only inside the module, the lack of direct connection of computing FPGAs to the control processor, only through the system FPGA, the lack of the ability to easily connect additional computing FPGAs to control processors, due to the limited PCIe slots on the motherboard circuit board, as well as the lack of a control system and temperature control mode of operation and a complicated cooling and power supply system integral FPGAs.

A reconfigurable FPGA FPGA system of the DINI Group company is known (http: // http: //www.dinigroup.com/product/data), the computing nodes of which DNBFC_S12_12_Cluster are a universal computer connected to a common EtherNet control network and contain eight computing DNBFC_S12_PCIe modules consisting of twelve Xilinx Spartan-6 150LX computing FPGAs installed on the motherboard in PCIe connectors and connected to the Xeon E3-1275 processor via Xilinx Virtex-6 system FPGAs that implement PCIe x4 bridges on each computing module and perform configurations FPGA computing. Computing FPGAs of the module are connected by a serial serial 77-bit channel with a data manager, also implemented on the Spartan-6 150LX FPGA, which is also connected to the system FPGA by a 64-bit bus, which provides data exchange between computing FPGAs and the processor, and two external high-speed serial duplex 4-bit GTP channels.

The disadvantages of this computing system are the large delay in the distribution of data when combining computing FPGAs in a single field and the transition to inter-module interaction, the low data rate between computing FPGAs and the control processor, a limited system for increasing the computing power of the reconfigurable part on the FPGA, and insufficiently high reliability.

The reasons hindering the achievement of the technical result are the indirect connection of computing FPGAs, the interaction of 12 computing FPGAs with processors is through one system FPGA, the lack of the ability to easily connect additional computing FPGAs to control processors, due to the limited PCIe slots on the motherboard, as well as lack of a control and management system for the temperature regime of operation and a complicated cooling system and power supply for computing FPGAs.

The closest computing system for the same purpose, to the claimed utility model, by the totality of features adopted as a prototype, is the Maxwell FPGA supercomputer (http://fpga.parallel.ru. Http://www.fhca.org/maxwell.html , http://www.springer.com), containing a master server connected via an ethernet control switch of a computer system via a network interface to a group of 32 slave computer nodes containing computers connected to the PCI-X bus on the motherboard and connected to them PCI-X reconfigurable FPGA computing devices that are integrated between themselves and the adjacent computing nodes over high speed serial interfaces Rocket 10.

The disadvantages of this computing system are the low data exchange rate between the computing FPGAs and the control processor, the ineffective system for increasing the computing power of the reconfigurable part on the FPGA, the only possible structure for combining the computing FPGAs in the field, and the insufficiently reliable operation.

The reasons hindering the achievement of the technical result are the use of an insufficiently high-speed PCI-X interface for the interaction of computing FPGAs and control processors, the inability to easily connect additional computing FPGAs to control processors, the fixed (mechanical, using cables) combining computing FPGAs in the field, and lack of a system for monitoring and controlling the temperature regime of computing FPGAs.

The problem to which the proposed utility model is directed is to create a high-performance computing system with a high-speed data exchange system and high reliability.

The technical result of the proposed utility model is the creation of a high-performance computing system with a configurable FPGA architecture, with the possibility of combining computing FPGAs into various computing structures, increasing the computing power of the reconfigurable part to FPGAs by simply connecting additional FPGAs of similar computing modules, redistributing the computing power of the reconfigurable part to FPGA computing nodes, in accordance with the nature of the performed tasks, and increase the speed of data exchange between computing FPGAs and the control processor through the use of high-speed PCI-Express interface, as well as ensuring high reliability of the computing system, through the use of a state-of-the-art monitoring system.

To solve this problem, in a reconfigurable computer system containing a master server 2, connected via an EtherNet control switch 1 of a computer system via a network interface 3 and EtherNet network interfaces 7 ₁ , ..., 7 _K with a group of K slave computing nodes 4 ₁ , ..., 4 _K , each of which contains a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , containing a group of M computing FPGAs 20 ₁ , ..., 20 _M each, and computers 8 with a PCIe bus on the motherboard,

in addition, a network Ethernet monitoring switch of computing system 5 was introduced, connected via EtherNet 6 network interfaces to the master server 2 and to a group of K Ethernet monitoring network ports 18 ₁ , ..., 18 _K slave computing nodes 4 ₁ , ..., 4 _K ,

each of which 4 _i includes an additional two-port interface board 9 connected via an internal high-speed serial PCI-Express interface 10 to computer 8 of the slave computing node 4 _i , an Ethernet monitoring switch 14 of slave computing nodes 4 _i , connected to the computer 8 of the slave computing node 4 _i via the EtherNet 12 network interface, to the Ethernet monitoring port 18 _i and a group of N Ethernet monitoring ports 26 ₁ , ..., 26 _N , PCI Express 11 switch of the slave computing node 4 _i , and the input port the PCI Express 11 switch is connected to the interface board 9 with a high-speed serial PCI-Express 15 interface, and N ports 16 ₁ , ..., 16 _N high-speed serial PCI-Express interfaces of a group of N reconfigurable computing devices 13 ₁ , ..., 13 _{N are} connected to the output ports ,

each of which 13 _j additionally includes a PCI-Express 30 switch mode control unit, an interface FPGA 22, an FPGA configuration memory 24 and a configuration and monitoring unit 23, a PCI-Express switch of reconfigurable computing devices 19, the interface FPGA 22 connected to the control unit PCI-Express 30 switch mode, FPGA configuration memory 24, configuration and monitoring unit 23, the PCI-Express switch of reconfigurable computing devices 19 is connected to the PCI-Express 30 switch mode control unit, high-speed input port 16 _j , to output port 28 _{j of} serial PCI-Express interface of reconfigurable computing devices 13 _j , via high-speed serial interface PCI-Express 17 to interface FPGA 22 and high-speed serial interfaces PCI-Express 21 ₁ , ..., 21 _M to a group of M computing FPGAs 20 ₁ , ..., 20 _M , which are connected by a common configuration and monitoring bus 25 to the configuration and monitoring unit 23 and are sequentially interconnected and the interface FPGA 22 with a ring high-speed serial the second information exchange channel 27, the interface FPGA 22 is also connected to the network monitoring port Ethernet 26 _j reconfigurable computing devices 13 _j ,

and in each slave computing device 4 _{i, the} output ports 28 ₁ , ..., 28 _{N of the} serial PCI-Express interface of reconfigurable computing devices 13 ₁ , ..., 13 _{N are} combined into a group of 29i high-speed output ports of the serial PCI-Express interface of the slave computing nodes 4 _i , which are used to increase the computing power of computing nodes 4.

In FIG. 1 is a functional diagram of a utility model of a reconfigurable computing system.

In FIG. 1 and the following abbreviations are adopted in the text:

VU - computing node;

IP - interface board;

KP - a computer with a PCIe bus on the motherboard;

VP - computing FPGA;

DS - output transparent port of a PCI-Express device;

US - input "transparent" port of the PCI-Express device;

NT - output “opaque” port of the PCI-Express device;

To - the number of slave WU computing system;

N is the number of reconfigurable devices in the slave slaves;

M - the number of VP in the reconfigurable devices of the slave;

i, j, n are counting variables.

In FIG. 1 adopted the following notation:

1 - control switch EtherNet computing system;

2 - leading server computing system;

3 - EtherNet network interface between the EtherNet 1 management switch and master 2;

4 ₁ , ..., 4 _K - a group of their K slave WU;

5 - network switch monitoring EtherNet computing system;

6 - EtherNet network interface between the EtherNet 5 network monitoring switch and master server 2;

7 ₁ , ..., 7K - a group of K EtherNet network interfaces between the EtherNet 1 control switch and a group of K slave slaves 4 ₁ , ..., 4 _K ;

8 - KP slave WU 4 ₁ , ..., 4 _K ;

9 - two-port interface board of the slave VU 4 ₁ , ..., 4 _K ;

10 - internal high-speed serial interface PCI-Express between the CP slave slave 8 and IP 9 slave slave 4;

11 - PCI-Express switch slave VU 4 ₁ , ..., 4 _K ;

12 - EtherNet network interface between the EtherNet 14 monitoring switch and KP 8 in slave units 4 ₁ , ..., 4 _K ;

13 ₁ , ..., 13 _N - a group of N reconfigurable computing devices in the slave WU 4 ₁ , ..., 4 _K ;

14 - EtherNet monitoring switch for slave VU 4 ₁ , ..., 4 _K ; for small K and N it can be combined with the EtherNet 5 monitoring network switch;

15 - high-speed serial PCI-Express interface between switch 11 and IP 9 in slave units 4 ₁ , ..., 4 _K ;

16 ₁ , ..., 16 _N - a group of N high-speed input ports of the serial PCI-Express interface of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

17 - high-speed serial PCI-Express interface between the PCI-Express 19 switch and the FPGA interface 22 reconfigurable computing devices 13 ₁ , ..., 13 _N ;

18 ₁ , ..., 18 _K - a group of K network Ethernet monitoring ports of slave slaves 4 ₁ , ..., 4 _K ;

19 - PCI-Express switchboard of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

20 ₁ , ..., 20 _M - a group of M computing FPGAs of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

21 ₁ , ..., 21 _M is a group of M high-speed serial PCI-Express interfaces between the PCI-Express 19 switch and VI 20 ₁ , ..., 20 _M in reconfigurable computing devices 13 ₁ , ..., 13 _N ;

22 - interface FPGA reconfigurable computing devices 13 ₁ , ..., 13 _N ;

23 is a block configuration and monitoring reconfigurable computing devices 13 ₁ , ..., 13 _N ;

24 - memory configurations FPGA reconfigurable computing devices 13 ₁ , ..., 13 _N ;

25 - a common bus for configuring and monitoring the VP of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

26 ₁ , ..., 26 _N - a group of N network Ethernet monitoring ports of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

27 - ring high-speed serial information exchange channel between the interface FPGA 22 and computing FPGAs 20 ₁ , ..., 20 _M in reconfigurable computing devices 13 ₁ , ..., 13 _N ;

28 ₁ , ..., 28 _N - a group of N high-speed output ports of the serial PCI-Express interface of reconfigurable computing devices 13 ₁ , ..., 13 _N ;

29 ₁ , ..., 29 _K - K groups of N high-speed output ports of the serial PCI-Express interface of slave slaves 4 ₁ , ..., 4 _K ;

30 - control unit mode switch PCI-Express 19 in reconfigurable computing devices 13 ₁ , ..., 13 _N.

The master server 2 is designed to organize task flow management for slave slaves 4 ₁ , ..., 4 _K through the EtherNet control switch of computing system 1 via the EtherNet 3 network interface and load operating systems in KP 8 slave slaves 4 ₁ , ..., 4 _K , and for the organization of monitoring the state of hardware of a computer system, which includes a control power on and off KP 8 and reconfigurable computing devices 13 _1, ..., 13 _N, collection and analysis of telemetry data about temperature and power slave mode 4 x TA _1, ..., _K 4, the network interface EtherNet 6. Host server 2 may be constructed to implement the independent data management and control systems and monitoring hardware.

The driven VU 4 ₁ , ..., 4 _K are designed for high-speed information processing and solving labor-intensive computational problems. KP 8 slave WU 4 ₁ , ..., 4 _K are designed to organize the management of reconfigurable computing devices 13i, ..., 13n when solving labor-intensive computing problems.

Two-port IP 9 slave VU 4 ₁ , ..., 4 _K are designed to provide interaction with KP 8 via the internal high-speed serial interface PCI-Express 10 and with the switch PCI-Express 11 via the high-speed serial interface PCI-Express 15.

The PCI-Express 11 switch is designed to ensure the interaction of KP 8 and reconfigurable computing devices 13 ₁ , ..., 13 _N via high-speed serial PCI-Express 16 ₁ , ..., 16 _N interfaces in slave slaves 4 ₁ , ..., 4 _K. With small values of N, the switch 11 can be implemented on several IP 9 in the slave WU 4 ₁ , ..., 4 _K.

EtherNet network monitoring switch 5 is intended for the organization of interaction of the master server and the slave 2 Slave 4 _1, ..., _K 4, the network interface EtherNet 6.

Reconfigurable computing devices 13 ₁ , ..., 13 _N slave VU 4 ₁ , ..., 4 _K are intended for the direct solution of labor-intensive tasks and processing large information arrays and streams using parallelization and pipelining of computing processes.

The PCI-Express switch 19 reconfigurable computing devices 13 ₁ , ..., 13 _{N is} designed to organize the exchange of information with the interface FPGA 22 and VP 20 ₁ , ..., 20 _M at the input port 16 and the organization of interaction between VP 20 ₁ , ..., 20 _M via PCI-Express 21 ₁ , ..., 21 _M interfaces and through switch 11 with gearbox 8 of slave control units.

Computing FPGAs 20 ₁ , ..., 20 _M are designed for the hardware implementation of labor-intensive algorithms of computational problems and carry out high-performance processing of incoming input data.

Interface FPGA 22 is designed to organize the exchange of information VP 20 ₁ , ..., 20 _M on the ring high-speed serial channel 27 and the input port PCI-Express 16 through the resources of the high-speed serial interface PCI-Express 17.

The reconfigurable device 23 configuration and monitoring unit is designed to configure VP 20 ₁ , ..., 20 _M via the Ethernet 26 monitoring port, PCI-Express interface 17 and from the FPGA 24 configuration memory via the FPGA 22 interface, and configure the FPGA 22 interface from the configuration memory 24 to turn on the power, as well as to monitor and control the power and temperature conditions of the air conditioner 20 ₁ , ..., 20 _M via the configuration and monitoring bus 25, using temperature sensors built into the computing air conditioner 20 ₁ , ..., 20 _M.

Configuration FPGA 24 memory is intended for storing configuration for interface FPGA 22 and start configuration for VP 20 ₁ , ..., 20 _M.

The EtherNet 14 switch is designed to organize the interaction of reconfigurable computing devices 13 _i , ..., 13 _N via the Ethernet 26 monitoring port and power supply control of the 8 CP slaves 4 ₁ , ..., 4 _K via the EtherNet 12 network interface.

The PCI-Express 30 switch mode control unit is designed to control the operating mode of input 16 and output 28 ports of the PCI-Express 19 switch.

The proposed reconfigurable computer system operates as follows.

The master server 2, in conjunction with the EtherNet switches 1, 5, and 14, is turned on first. After the initial loading of the OS, the master server 2 first turns on reconfigurable computing devices 13 ₁ , ..., 13 _N in the slave WU 4 ₁ , ..., 4 _K. After loading the interface FPGA 22 and computing FPGAs 20 ₁ , ..., 20 _M from the FPGA configuration memory 24, setting the thresholds for operating the FPGA temperature protection and the operating mode of the PCI-Express 19 switch, KP 8 slave computing modules are turned on. After loading the OS KP 8, which can be carried out from autonomous disks or via the EtherNet network, the master server 2 launches programs for them reconfiguring the FPGAs 20 ₁ , ..., 20 _M reconfigurable computing devices 13 ₁ , ..., 13 _N in the slave WU 4 ₁ , ..., 4 _K , in accordance with the current requirements for the architecture of the computing system. Next, the voltage of the interface FPGA 22 and computing FPGAs 20 ₁ , ..., 20 _M is checked, as well as the connections of all FPGAs to the PCI-Express switches of the slave VU 4 ₁ , ..., 4 _K via PCI Express circuits.

Since at the initial configuration of computing FPGAs, they are initialized as agents of the PCI-Express network, in a format that obviously covers the resource needs of users (except for individual, individual cases), and are allocated in the memory of KP 8 at the stage of its loading, then after reconfiguration by working programs Rebooting OS slave slaves, as a rule, is not required. Computing FPGAs 20 ₁ , ..., 20 _{M are} initialized as agents of the PCI-Express network and are distributed in three memory areas of KP 8, one megabyte each.

One of the areas (BAR2) is designed for the interaction of KP 8 of the slave VU 4 and the control and status registers, including the direct memory access control channel (DMA) registers, which are available in each of the FPGAs 20 as agents of the PCI-Express network.

Another area (BAR1) is intended for data exchange with the KP 8 processor of the slave VU 4 via the internal interfaces of computing FPGAs. These include the interfaces through the internal memory of the FPGA random access (BRAM) and serial access (FIFO), as well as a direct command interface for working with user hardware devices.

The third area (BAR0) is intended for data exchange between PCI-Express network agents located in the same address space, i.e. between computing FPGAs 20 within the same slave VU 4. The exchange between computing FPGAs 20 is supported at the software and hardware level.

When using data exchange between computing FPGAs 20 within reconfigurable computing devices 13 of slave VU 4 via a ring high-speed serial data exchange channel 27 and / or data transfer mode via PCI-Express interfaces, one can obtain the union of all computing FPGAs 20 ₁ , ..., 20 _M in unified computing field WU 4.

When using data exchange between computing FPGAs of 20 different VU 4 via PCI-Express interfaces through output ports 28 of switches 19, it is possible to obtain a combination of all computing FPGAs 20 into a single computing field within the computing system as a whole. Data exchange between computing FPGAs 20 located in different VU 4 is carried out through NT ports, which are actually “opaque” bridges that divide the address spaces of computing nodes 4, and which allow computing FPGAs 20 to interact through established address windows.

In order to redistribute the resource of computing FPGAs 20 between different WUs 4, at the stage of setting thresholds for temperature protection and the operating mode of the PCI-Express 19 switch, setting the input port (NT or US) of switch 19 and the output port (NT or US), the connection of computing FPGAs 20 to KP 8 VU 4 from the US port, while from the NT port the address spaces of VU 4 are separated. This property of the utility model is distinctive and allows optimizing the reconfigurable computing system in depending on the nature of the tasks performed, without resorting to mechanical switching of PCI-Express connections of various computing nodes.

The monitoring system of the state of technical means allows not only continuous monitoring of the state of the main characteristics of the computing system (supply voltage and current temperature of computing FPGAs 20), but also timely disconnecting of overheating computing FPGAs 20 from power supply in order to reduce the risk of their irreparable failure.

A useful model of a reconfigurable computing system provides a multi-user and multi-tasking mode of operation with a minimum unit of use of one computing FPGA 20, since they all have independent interfaces with PC 8 and can be configured for various tasks. The distribution of resources of a reconfigurable computing system between user tasks is carried out depending on the needs and availability of free computing FPGAs 20.

The proposed reconfigurable computing system can be implemented on the following elements:

The leading server 2 can be executed on the basis of the 2xIntel (R) Xeon (R) CPU E5-2665 8 cores, with 32 Gb RAM, 1 Tb hard disk and switches 1 and 5 as GigabitEthernet.

Slave WU 4: Processor 2xIntel (R) Xeon (R) CPU E5-2665 8 cores; RAM 32 Gb; Hard disk 1 Tb; 8 reconfigurable computing devices 13, 8 computing FPGAs 20 each; Interface board 9 of the slave VU - ABE-2010 based on the PEX8619 switch chip from PLX Technology; Switch 14 GigabitEthernet.

Reconfigurable computing devices 13: computing FPGAs 20 — on Xilinx chips of the XC7K480T-1FFG1156C type; Interface FPGA 22 - on a Xilinx chip of type XC6VLX75T-1FFG784C; PCI-Express 18 switch - on the PX8648 switch chip from PLX Technology; The configuration and monitoring unit 23 — on the CPLD XC2C64A, MAX6656 microcircuits; The memory of the starting configurations 24 is on microchips SPI-memory М25Р64 and Flash-memory S29GL512P.

Software: Linux operating system, with a kernel no lower than 2.6.32; Compilers C; Software package consisting of:

1. A set of PCI utilities from the standard RedHat Linux distribution, namely:

a. lspci - prints to standard output detailed information about all PCI buses and devices on them.

b. setpci - allows you to read and write data to the PCI configuration address space.

2. A set of scripts that use the lspci and setpci utilities and allow for word-by-word data exchange with FPGAs by writing / reading to the addresses of the configuration address space.

3. A set of scripts based on the lspci and setpci utilities that configure the DMA FPGA mechanism.

4. A set of programs that allow you to write and read the DMA-memory area, which is allocated when loading the Linux kernel on the host by setting the command line switch boot kernel memmap.

5. To communicate with the node over the EtherNet network, two Linux service commands were used:

a. arp -s 192.168.85.212 00-aa-00-62-s6-09, where the arguments are the network and MAC addresses of the reconfigurable computing devices of the slave I / O and Navy controllers KP 8, and serves to communicate the network address and the physical MAC address of the device.

b. ping -1 4 192.168.85.212, where the argument is the length of the packet of sent data, this command also displays a protocol on the availability of this device in the monitoring network.

6. A set of monitoring programs allows you to control the power of reconfigurable computing devices of the slave I / O and Navy controllers KP 8, as well as setting thresholds for temperature protection and removal of the current state of the air temperature.

Thus, the above information allows us to conclude that the proposed reconfigurable computing system solves the problem and meets the claimed technical result - the creation of a high-performance computing system with a tunable architecture on computing FPGAs, due to the possibility of combining computing FPGAs into various computing structures, increasing the computing power of the reconfigurable part on FPGAs by simply connecting additional FPGAs similar computing modules, redistributing the computing power of the reconfigurable part on the FPGA of the computing nodes, in accordance with the nature of the tasks performed, and increasing the data exchange rate between the computing FPGAs and the control processor by using the high-speed PCI-Express interface, as well as ensuring high reliability of the computing system, for through the use of a system for monitoring the state of technical equipment.

Claims (1)

A reconfigurable computing system comprising a master server 2 connected through an EtherNet control switch 1 of a computing system via a network interface 3 and EtherNet network interfaces 7 ₁ , ..., 7 _K with a group of K slave computing nodes 4 ₁ , ..., 4 _K , each of which contains a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , containing a group of M computing FPGAs 20 ₁ , ..., 20 _M each, and computers 8 with a PCIe bus on the motherboard, characterized in that the Ethernet monitoring network switch is additionally introduced into it you islitelnoy system 5 that is connected via network interfaces EtherNet 6 to the master server 2 and the group of K Ethernet network monitoring ports 18 _1, ..., 18 _K slave computational units 4 _1, ..., _K 4, a part of each of which 4 _i additionally introduced a two-port interface card 9 connected via an internal high-speed serial PCI-Express interface 10 to computer 8 of the slave computing node 4 _i , an Ethernet monitoring switch 14 of the slave computing nodes 4 _i , connected to computer 8 of the slave computing node 4 _i via the network int EtherNet 12 interface, to the Ethernet monitoring port 18 _i and a group of N Ethernet monitoring ports 26 ₁ , ..., 26 _N , PCI Express 11 switch of the 4 _i slave, and the input port of the PCI Express 11 switch is connected to the interface board 9 high-speed serial PCI-Express interface 15, and N ports 16 ₁ , ..., 16 _N high-speed serial PCI-Express interface of a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which 13 _{j the} com mode control unit is additionally introduced PCI-Express 30 mutator, interface FPGA 22, FPGA configuration memory 24 and configuration and monitoring unit 23, PCI-Express switch of reconfigurable computing devices 19, the interface FPGA 22 connected to the PCI-Express 30 switch mode control unit, FPGA configuration memory 24, the configuration and monitoring unit 23, the PCI-Express switch of the reconfigurable computing devices 19 is connected to the control unit of the PCI-Express 30 switch mode, to the high-speed input port 16 _j , to the output port 28 _{j of the} serial interface P CI-Express reconfigurable computing devices 13 _j , via high-speed serial interface PCI-Express 17 to interface FPGA 22 and high-speed serial interfaces PCI-Express 21 ₁ , ..., 21 _M to a group of M computing FPGAs 20 ₁ , ..., 20 _M , which are connected by a common configuration and monitoring bus 25 to the configuration and monitoring unit 23 and are sequentially interconnected and the interface FPGA 22 by a ring high-speed serial information exchange channel 27, the interface FPGA 22 is also connected to the network via via Ethernet monitoring port 26 _j reconfigurable computing devices 13 _j , and in each slave computing device 4 _{i, the} output ports 28 ₁ , ..., 28 _{N of the} serial PCI-Express interface of reconfigurable computing devices 13 ₁ , ..., 13 _{N are} grouped 29 _i high-speed output ports of the PCI-Express serial interface of slave computing nodes 4 _i , which are used to increase the computing power of computing nodes 4.

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