LU87146A1 - BROADBAND SIGNAL DEVICE - Google Patents

Description

83 / B 52 732 ’’ J ^ L f | GRAND-DUCHÉ DE LUXEMBOURG -r-yS — Λ ..... 1 ................ i ................ .f ^ ·· Λ, · ΓΤ ^ εΡ ^ ηΟ 1 \

Monsieur le Miastre Dü> 1 * du .......... 2.9 ........ £ é..vr.ï.SX ........ 1 ... 9..8 8 de l'Économie ettdes Class ^ îyloy ^ qjï ^ \ T *, j, zSESS Service de la Pronriétôl ^ eÜycîuelle - «* - 4

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Demande de Brevet d'invention -------------------------------------------- -------------------------------------------------- ------------- (1) I. Requête ........... La ...... aQ..Gié.t.é .... ..dit.Q..S ........ S IEMEMS ...... ÄKTIEH.GESELLSCHAFT BERLIN and______ (2) ........... MÜNCHEN, Wittelsbacher .... ..Place 2, D-8000 MUNICH ........ (République _______________ Fédérale d1Al1emagne) / représentée par Mon sleur Jacque s de Mîiyser, agissant en qualité ...... le mandataire ....... .............................. .................... ........... ^ dépose (nt) ce .............. vingt-neuf ....... février 1900 quatre-vingt huit________________ (4) à ............. 1.5 .................. heures, au Ministère de l'Économie et des Classes Moyennes, à Luxembourg: 1 . la présente requête pour l'obtention d'un brevet d'invention concernant: .................... broadband signal coupling device. "_________________________________________ (5) 2. la description en langue .......... âl lsniande_____________________________________________de l'invention en trois exemplaires; 3. - .3 ............... ..................... planches de dessin, en trois exemplaires; · 4th la quittance des taxes versées au Bureau de l'Enregistrement à Luxembourg, le 26 février 1988 ; 5. la délégation de pouvoir, datée de____________________________________________________________________________________ le___________________________________; 6. le document d'ayant cause (authorization); déclare (nt) en assumant la responsabilité de cette déclaration, que Î '(es) inventeur (s) est (sont) : (6) ............- Dr ......... Ruediqer Hofmann, Fürstenfelder Weg 12, ____________________________ ............... ........ D-803-1 ....... GILCHING ........ (République Fédérale d'Allemagne) ____________ revendique (nt) pour la susdite demande de brevet la priorité d 'une (des) demande (s) de (7) .......... brevet_________________________ ________________________________________________________________________________________ déposée (s) en (8) République ..... Fédéra ..ri 'Rl l prrwgn le (9) ................. 1.4 ..... ..octobre ....... 1,9,8. ,, 7 ............................... ........................................____________________________________________________________________________________________________________________ sous le N ° (10) .. ...... P..3 ... 7..3..4..8.22 ... «.. l .................... .................................................. .................................................. .................................................. .................................................. ...

au nom de (11) la ..... déposante ..................................... .................................................. .................................................. ...... · ....____________________________________________________________________________ élit (élisent) domicile pour lui (elle) et, si désigné, pour son mandataire, à Luxembourg ................. ................................................

...... 35 boulevard ...... Royal ................................... .................................................. .................................................. .................................................. .......................... (12) sollicite (nt) la délivrance d'un brevet d'invention pour l'objet décrit et représenté dans les annexes susmentionnées, avec ajournement de cette délivrance à ____________________ L ........................................ .................................................. .................................................. ................... mois. (13)

Le-dépOsaulAmandataire: .............................................. .................................................. .................................................. .................................................. .................................................. ............ (14) (LA — Π. Procès-verbal de Dépôt

La susdite ^ emande de brevet d'invention a été déposée au Ministère de l'Économie et des Classes Moyennes, Service de la Propriété IntelJjBetBeôe ^ Luxeinbourg, en date du: 29 février 1988 / \ v »..... ·% Λ / i £ · Λ Pr. le Ministre de l'Économie et des Classes Moyennes, à 1.5 ________________ heure / £ jL ^. d.

IJ II Le chef du serve la ^ ropriété intellectuelle, \> 'Sf ^ A68007 ____ f / \ _ EXPLICATIONS RELATIVES AU FORMOfcMREDMHtPOT. ! / (1) s'il ya lieu "Demande de certificat d'addition au brevet principal, à la demande de brevet principal No ............ du ......, .. ... ”- (2) inscrire les nom, prénom, profession, address du demandeur, lorsque celui-ci est un particulier ou les dénomination sociale, formme juridique, adresse du siège social, lorsque le demandeur est une personne morale - (3rd ) inscrire les nom, prénom, adresse du mandataire agréé, conseil en propriété industrial, muni d'un pouvoir spécial, s'il ya lieu: "représente par ............ agissant en qualité de mandataire "• ^ 88 / B 52 732

DEMANDING PRIORITY

♦ the patent / Gbm. - Registration ln: the FEDERAL REPUBLIC OF GERMANY from: OCTOBER 14, 1987 _ (No.P3734822.1) _

PATENT APPLICATION

in

Luxembourg

Applicant: Siemens Aktiengesellschaft Berlin and Munich: * 8000 MUNICH (Federal Republic of Germany)

Concerning : "Broadband signal coupling device." • · ι Λ

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‘T i i! i! Siemens Aktiengesellschaft

Berlin and Munich 5

Broadband signal coupling device

Recent developments in telecommunications technology lead to integrated service transmission u. Switching systems for narrowband and broadband communication services, which provide fiber as a transmission medium in the area of the subscriber access lines, via which both the narrowband communication services, such as 64 kbit / s digital telephony in particular, and broadband communication services, such as in particular 140 Mbit / s-picture telephony are performed, but in the switching centers (preferably having common control devices) narrowband signal coupling devices and broadband signal coupling devices are provided side by side (DE-PS 24 21 002).

20th

In connection with a broadband signal-time-division multiplex switching device, the coupling points of which are used in time-division multiplexing for a plurality of connections, it is known to connect two lines in each case with the aid of a gate element which is designed as a bistable D flip-flop , crosspoint individual memory cell is switched on and off, this crosspoint individual memory cell, the clock input of which is supplied with a corresponding clock signal, is controlled in only one coordinate direction, namely at its D input, an-3Q (Pfannschmidt: "Working speed limits of coupling networks for Broadband digital signals ", Diss., Braunschweig 1978, Figure 6.7, furthermore Figure 6.4). In view of a time-division multiplexing factor of about 4 to 8 that can be achieved at a bit rate of 140 Mbit / s and the complex circuitry required for this, pure space switching devices are currently preferred for the transmission of broadband signals, in which the switching through the individual coupling points

! ' 87 P17 7 2 DE

l «- 2 - 1 connections are spatially separated from each other alone.

A pure broadband signal space switching arrangement can be designed as a coupling 5-point matrix provided with input amplifiers and output amplifiers in C-MOS technology, in the coupling points of which the coupling elements are each controlled by a decoder-controlled, coupling point-specific hold memory cell, the coupling elements in each case as C- MOS transfer gate (C-MOS transmission gate) are formed (ISS184 Conference Papers 10 23C1, Fig. 9) î the crosspoint-specific hold memory cells of a pure space switching matrix can be from a row decoder and from a column decoder each via a row or column-specific control line can be controlled in two coordinates (Pfannschmidt, loc. cit., Figure 6.4).

15

In a wideband signal space coupling device with a crosspoint matrix in FET technology, the coupling elements can have n-channel transistors 20 (see also ISS'84 Conf. Papers 31. With the drain-source path between a matrix input line and a matrix output line). C.3, FIG. 12), which are each controlled by a crosspoint-specific memory cell controlled by two control decoders in two coordinates with two cross-coupled inverter circuits, one of which is connected on the input side to the associated inverting decoder output 25 of the one control decoder via a first n- Channel transistor is connected and the other is connected on the input side to the associated non-inverting decoder output of the same control decoder via a second n-channel transistor, where _ both jv-channel transistors yes, in turn on their control electrode 30 with the output signal of the associated decoder output of the other control decoder are acted upon (Rev. ECL 25 (1977) 1-2, 43 ... 51, Fig. 1; IEEE J. of Solid-State Circuits SC-9 (1974) 3, 142 ... 147, Fig. 1 (a) $ Electronics and Communications in Japan, 53-A (1970) 10, 54 ... 62, Fig .5 (b) j EP-A-0 073 920, FIG 4).

35 Every reversal (rewriting) of such a known memory cell requires the injection of a write current of a certain size for a certain time, which entails corresponding write loss performance and rewrite durations.

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A

- 3 - 1 In contrast, the object of the invention is to show a way in which the individual crosspoint-specific memory cells can be implemented in a broadband coupling device in a particularly expedient manner which is associated with low write loss powers and short 5 switching times.

The invention relates to a broadband signal coupling device with a crosspoint matrix in FET technology, the coupling elements of which are controlled by two crosspoint-controlled, crosspoint-individual 10 hold memory cells, each of which is formed with two cross-coupled MOS inverter circuits, one of which is connected on the input side to the one non-inverted drive signal of the drive line leading one drive direction is connected via a first drive transistor and the other input side of which is connected to a drive line leading the inverted drive signal of the same drive direction via a second drive transistor, both drive transistors in turn on their control electrode with the associated drive signal of the other drive direction are acted upon; This space-20 coupling device is characterized according to the invention in that between the two C-MOS inverter circuit transistors of the one channel type and the associated supply potential source - or between the two load transistors of the two cross-coupled n-channel inverter circuits and the associated supply 25 potential source - An additional load transistor of the same

Channel type is inserted, the control electrode with which the non-inverted - or the inverted - drive clock signal of the other drive direction mentioned leading Eruist eruist, _ and / or 30 that between the two C-MOS inverter circuit transistors of the other channel type and the associated supply potential source - or between the two driver transistors of the two cross-coupled n-channel inverter circuits and the associated supply potential source - an additional driver transistor of the same channel type is inserted, the control electrode of which is connected to a control line carrying the inverted control clock signal of the other control direction mentioned is.

87 P 1 7 7 2 DE

The invention has the advantage of making current in the crossover phases of the crosspoint individual stop memory cells provided in a crosspoint matrix, each of which can be controlled in two coordinate directions, and thus to be able to avoid any losses which otherwise occur.At the same time, they are particularly short Reversal times connected.

In a further embodiment of the invention, the drive transistors and the additional load transistor can be of the opposite channel type, the drive transistors at their control electrode also being acted upon by the non-inverted drive clock signal of the other drive direction mentioned. In another embodiment of the invention, the drive transistors and the additional driver transistor can be of the opposite channel type, the drive transistors at their control electrode also being acted upon by the inverted drive clock signal of the other drive direction mentioned.

Further special features of the invention will become apparent from the following explanation of the invention with reference to the drawing. 1 shows the diagram of a broadband switching device and FIG. 2, FIG. 3, FIG. A and FIG. 5 show details of its circuitry implementation according to the invention.

25th

In the drawing FIG. 1, a broadband signal coupling device is schematically sketched in the scope necessary for understanding the invention, at whose inputs leading to column lines sl. ^ Sj ... sn _ a crosspoint matrix, el ... ej ... en input driver circuits El ... Ej ... En are provided and their outputs reached by row lines zl ... zi ... zm the crosspoint matrix al ... ai ... am with output amplifier circuits Al ...

Ai ... On are provided. The crosspoint matrix has crosspoints KP11 ... KPij. ..KPmn, the coupling elements of which, as indicated for the coupling element Kij in the coupling point KPij in more detail, are each controlled by a coupling point-specific holding memory cell Hij (at the coupling point KPij)

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}> - 5 - 1, whose output s', s "leads to the control input of the respective coupling element (Kij at the coupling point KPij).

The hold memory cells ... Hij ... are, according to FIG. 1, by 5 two control decoders, namely a row decoder DX and a column decoder DY, via corresponding control lines xl ... xi ... xm; yl ... yj ... yn controlled in two coordinates. For this purpose, as can be seen from FIG. 1, the two control decoders DX, DY of input registers Reg X, Reg Y ago 10 each with a matrix row (row or column) of

Crosspoints common crosspoint row or crosspoint column address can be acted upon, to which they each emit a "1" control signal on the control line corresponding to the respective crosspoint row address. The coincidence of a line control signal "1" and one Column drive signal "1" at the intersection of the relevant matrix line with the relevant matrix column when a corresponding connection is established then activates the hold memory cell located there, for example the memory 20 cell Hij, with the result that the hold memory cell concerned Memory cell (Hij) controlled coupling element, in the example the coupling element Kij, becomes conductive.

So that the coupling element Kij considered in the example is blocked again when the connection in question is cleared down, the control decoder DY is again loaded with the relevant column address by the input register Reg Y, so that the column decoder DY in turn outputs a column control signal "l" on its output line yj. outputs, and at the same time the Zeiieiyiecoder DX -30 from its input register Reg X forth for example with an empty address or with the address of a line of unconnected crosspoints, so that it outputs a line drive signal "0" on its output line xi; the coincidence of column drive signal "1" and row drive signal "0" then causes the hold memory cell Hij to be reset, with the result that the coupling element Kij controlled by it is blocked.

The coupling elements provided in the coupling points ... KPij ...

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- 6 - 1 ... Kij ... can be realized in a manner known per se, as is also the case, for example, in EP-AQ 219 848, EP-A-0 221 490, EP-A-0 238 834, DE-P 3 631 634 or DE-P 3 634 154 is known and therefore need not be explained further here. ' FIG. 2, FIG. 3 and FIG. 4 illustrate how the holding 5 memory cells ... Hij ... can be implemented in terms of circuitry:

As can be seen from FIG. 2, FIG. 3 and FIG. 4, the crosspoint-individual holding cells Hij, which can be controlled in two coordinates, are each provided with two cross-coupled C-MOS modules.

Inverter circuits Tp *, Tn1; Tp ", Tn" formed, one (Tp1,

Tn ') is connected on the input side to a control line xi which carries the non-inverted control signal of a control direction via a first control transistor (Tnh1 in FIG. 2 and FIG. 4, 15 Tph' in FIG. 3) and the other (Tp ", Tn") is connected on the input side to one the inverted drive signal of the same drive direction, the drive line xT is connected via a second drive transistor (Tnh "in FIG. 2 and FIG. 4, Tph" in FIG. 3), the two drive transistors in turn being acted on by 20 of their control electrode with the associated drive signal of the other drive direction.

In the holding memory cell Hij outlined in FIG. 2 there is an additional load transistor Tpl of the same channel type between the two C-MOS inverter circuit transistors Tp ', Tp "of the one channel type (p-channel) and the associated supply potential source UDD (+ 5V) inserted, the control electrode of this additional load transistor Tpl being connected to the non-inverted drive clock signal of the other drive direction-30 yj leading the other drive direction. The drive transistors Tnh1 and Tnh "are n-channel transistors; the drive transistors Tnh1, Tnh "and the additional load transistor Tpl are thus of the opposite channel type.

35 As a result of the "1" signal occurring on the drive clock line yj during a drive (write phase) of the latch cell Hij, e.g. + 5V controlled the additional load

ί ·; ^. 87 P 1 7 7 2 DE

-τι transistor Tpl in the blocking state and thus switches for the

Duration of the write phase the operating voltage of the cross-coupled C-MOS inverter circuits Tp1, Tn ’; Tp ", Tn", so that the cross-coupled C-MOS inverter circuits are currentless. At the same time, during the control phase the hold memory cell Hij is set to the switching state corresponding to this control signal by the control signal which does not invert on the control line xi and which occurs inverted on the control line χΓ; The hold memory cell Hij remains in the switching state preset in this way during the write phase if a "0" signal (OV) occurs again on the control line yj when the write phase ends and the additional load transistor Tpl becomes conductive again.

In the holding memory cell Hij outlined in FIG. 3, an additional driver transistor Tnt of the same channel type, the control electrode of which is inserted between the two C-MOS inverter circuit transistors Tn * and Tn "of the n-channel type and the associated supply potential source (ground) is connected to a drive line ÿj carrying the inverted drive clock signal of the other drive direction mentioned The hold memory cell Hij according to FIG. 3 then operates analogously to the hold memory cell according to FIG.

Due to the "0" signal of, for example, the control clock line yj occurring during a control (write phase) of the holding memory cell Hij Controlled by 0 V, the additional driver transistor Tnt goes into the blocking state and thus switches the operating voltage of the cross-coupled C-MOS inverter switching signal Tp ', Tn' for the duration of the write phase; Tp ", .Itx", ^ ib, - so that the. _ 30 cross-coupled C-MOS inverter circuits are de-energized. At the same time, the hold memory cell Hij is set in the switching state corresponding to this drive signal during the drive phase by the drive signal which does not invert on the drive line xi and inverted on the drive line 3ΓΓ, 35 in which the hold memory cell Hij thus preset during the write phase remains, if thereafter at the end of the write phase on the control line yj again a "1" signal

: · * * "87 P 17? 2 DE

- 8 - 1 (+ 5V) occurs and the additional driver transistor Tnt becomes conductive again.

As can be seen from FIG. 4, it is also possible to provide both an additional load transistor and an additional driver transistor: According to FIG. 4 ', between the two C-MOS inverter circuit transistors Tp1, Tp "of the p-channel type and the associated supply potential source Uqq inserts an additional load transistor Tpl of the same channel type, the control electrode 10 of which is connected to a drive line yj carrying the non-inverted drive clock signal, and it is between the two C-MOS inverter circuit transistors Tn ', Tn "of the n- Channel type and the associated supply potential source (ground), an additional driver transistor Tnt also of the n-channel type is inserted, the 15 control electrode of which is connected to a control line ÿj carrying the inverted control clock signal of the relevant control direction. The drive transistors Tnh1, Tnh "and the additional load transistor Tpl are of the opposite channel type, i.e. the drive transistors Tnh 'and Tnh" are n-channel transistors.

20 In addition to the complementary signal control of the hold memory cell Hij via the two drive lines xi, xT of the one drive direction, there is also a complementary signal timing of the hold memory cell with the non-inverted and the inverted drive via the two drive lines yj, yj. ? 5 clock signal of the other control direction instead.

In this context, it should be noted that the inverted control signal 7Γ or yj required for such a complementary control, as is also indicated in FIG. 2, FIG. 3 and FIG. 4, is led through the coupling device 30 on a separate line can; as an alternative to this, it is also possible to obtain the respective inverted control signal (xT or yj) individually by inverting the respective non-inverted control signal (xi or yj) at each coupling point, which need not be described here, however, since this is for understanding the 35 invention is not required.

During an actuation (write phase) of the holding memory cell Hij, the additional load transistor Tpl passes through the

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- 9 - 1 drive clock line yj occurring "1" signal from e.g. + 5V controlled, into the blocking state, and at the same time the additional driver transistor Tnt, 'by the "0" signal of e.g., occurring on the control 5 clock line ÿj during the control (write phase) of the latch memory cell Hij 0 V controlled, in the blocking state. For the duration of the write phase, the operating voltage of the cross-coupled C-MOS inverter circuits Tp1, Tn1; Tp ", Tn" switched off on both sides, so that the cross-coupled C-MOS inverter circuits are currentless. At the same time, during the control phase, the hold memory cell Hij is set to the switching state corresponding to this control signal by the drive signal which does not invert on the control line xi and inverted on the control line xT, in which the hold memory cell 15 Hij thus preset during the write phase remains if then, when the write phase ends, a "0" signal (0 V) appears again on the control line yj and a "1" signal (+ 5V) again occurs on the control line yj and the additional load transistor Tpl and the additional driver transistor Tnt become conductive again .

20 The complete separation of the two cross-coupled C-MOS inverter circuits Tp ·, Tn1; Tp ", Tn" of both supply voltage terminals (UqD and ground) allows a particularly short and at the same time safe actuation phase (write phase) of the holding memory cell Hij.

25th

The invention is not restricted to hold memory cells implemented in C-MOS technology; as well as according to FIG. 2, FIG. 3 and FIG. 4 in a hold memory cell realized in C-MOS technology between two j-ie two C-MOS inverter circuit transistors of the one channel type and the associated supply potential source and an additional load transistor one channel type and / or between the two C-MOS inverter circuit transistors of the other channel type and the associated supply potential source an additional driver transistor also of the other channel-35. typs can be inserted, can rather according to the invention also in a single-channel technology realized memory cell between the two load transistors of the two cross-coupled »

87P 1 7 7 20E

-ΙΟΙ Inverter circuits and the associated supply potential source, an additional load transistor of the same channel type may be inserted, the control electrode of which is connected to an An-5 control line carrying the corresponding actuation clock signal of the other actuation direction mentioned, and / or there can be between the two driver transistors and the associated supply potential source, an additional driver transistor of the same channel type may be inserted, the control electrode of which is also connected to the control line with a control signal which carries the corresponding control clock signal of the other control direction mentioned. The drawing FIG 5 shows an embodiment:

According to FIG. 5, the crosspoint-specific hold memory cell Hij, which can be controlled in two coordinates, is formed with two cross-coupled 15 n-channel inverter circuits Tnd1, Tne'j Tnd ", Tne", one (Tnd1, Tne1) of the input side of which is the non-inverted control signal a drive line xi carrying the drive direction is connected via a first drive transistor Tnh 'and the other (Tnd ", Tne") is connected on the input side to a drive line xT carrying the inverted drive signal of the same drive direction via a second drive transistor Tnh *, the two drive transistors in turn, the control clock signal of the other control direction is applied to their control electrode.

25th

In the holding memory cell Hij outlined in FIG. an additional driver transistor Tnt of the same channel type is inserted between the two n-channel (enhancement) transistors Tne1, Tne ”and the associated supply potential source (ground), the control electrode of which - with an inverted drive clock signal other control direction leading control line ÿj is connected. The hold memory cell Hij in accordance with FIG. 5 then works analogously to the hold memory cell in accordance with FIG. 3: 35 by the "0" signal of e.g., occurring on the drive clock line yj during an actuation (write phase) of the hold memory cell Hij. 0 V controlled the additional

'87 P 1 7 7 2 DE

- π -

Driver transistor Tnt in the blocking state and thus switches off the operating voltage of the cross-coupled n-channel inverter circuits Tnd1, Tne'j Tnd ", Tne" for the duration of the write phase, so that 5 the cross-coupled n-channel inverter circuits are de-energized. At the same time, during the drive phase, the hold memory cell Hij is set by the drive signal non-inverted on the drive line xi and inverted on the drive line xT to the switching state corresponding to this drive signal, in which the hold memory cell Hij thus preset during the write phase remains. if afterwards the end of the write phase on the control line yj instead of a "1" signal (+ 5V) controlling the control transistors Tnh ', Tnh "in the leading state, a 15" 0 "signal (0 V) blocking the control transistors occurs and vice versa an Ml ”signal on the control line ÿj again, so that the additional driver transistor Tnt becomes conductive again.

Alternatively or additionally, an additional load transistor of the same channel type can also be inserted between the two 20 n-channel (depletion) load transistors Tnd1, Tnd "and the associated supply potential source UpD, the control electrode of which is also connected to the control line yj carrying the inverted control clock signal is, without this 25 would have to be shown in the drawing.

4 claims

5 FIG

30 35

Claims (4)

1. wideband signal coupling device with a crosspoint matrix in FET technology, the coupling elements of which are controlled by crosspoint-specific hold memory cells 5 (Hij) controlled in two coordinates, each with two cross-coupled MOS inverter circuits (Tp *, Tn'j Tp ", Tn ") are formed, one (Tp1, Tn1) of which is connected on the input side to a control line (xi) carrying the non-inverted control signal of the one control direction via a first control transistor (Tnh1) 10 and the other (Tp", Tn ") of which is connected to one on the input side the inverted control signal of the same control direction-leading control line (> αΓ) is connected via a second control transistor (Tnh ”), wherein both control transistors (Tnh1, Tnh”) are in turn applied to their control electrode with the associated control signal of the other control direction, characterized that between the two C-MOS inverter circuit transistors (Tp '$ Tp ”) of one channel yps and the associated supply potential source (UQD) an additional load transistor (Tpl) is also inserted of the one channel type, the control electrode of which is connected to the drive line (yj) carrying the non-inverted drive clock signal of said other drive direction, and / or that between the two C-MOS inverter circuit transistors (Tn'j Tn ”) of the other channel type and the associated supply potential source (ground) an additional driver transistor (Tnt) of the other channel type is also inserted, the control electrode of which is used to invert the drive Clock signal of the other control device mentioned ^. Leading control line __ 30 (yj) is connected. 1 claims 2. Broadband signal coupling device with a crosspoint matrix in FET technology, the coupling elements of which are controlled by crosspoint-specific holdpoint memory cells 35 (Hij) controlled in two coordinates, each with two cross-coupled MOS inverter circuits (Tnd1, Tne '; Tnd ”, Tne ") are formed, one (Tnd1, Tne ') of the input side of which is the non-inverted'. · * * 87 P Î 7 7 2 DE. · imspr ^ - 13 - 1 tied control signal of the control line leading a control direction (xi) is connected via a first drive transistor (Tnh1) and the other (Tnd ", Tne") is connected on the input side to a drive line (3ΓΓ) carrying the inverted drive signal of the same drive direction 5 via a second drive transistor (Tnh ”), both drive transistors (Tnh1, Tnh ") are in turn supplied with the associated control signal of the other control direction on their control electrode, 10 characterized in that between the two loads transistors of the two cross-coupled n-channel inverter circuits and the associated supply potential source, an additional load transistor of the same channel type is inserted, the control electrode of which is connected to the drive line (ÿj) carrying the inverted drive clock signal of said other drive direction, and / or that between the two driver transistors (Tne1; Tne ") of the two cross-coupled n-channel inverter circuits and the associated supply potential source (ground), an additional driver. 20 transistor (Tnt) of the same channel type is inserted, the control electrode of which with a drive line carrying the inverted drive clock signal of the other drive direction mentioned ( yj) is connected. 3. wideband signal coupling device according to claim 1, characterized in that the control transistors (Tnh * 5 Tnh ") and the additional load transistor (Tpl) are of the opposite channel type, the control transistor Qren_ίTnh, 5 Tnh") on ibrar. Control electrode 30 also are applied to the non-inverted control clock signal (yj) of said other control direction. 4. wideband signal coupling device according to claim 1, characterized in that the drive transistors (Tph'j Tph ") and the additional driver transistor (Tnt) are of the opposite channel type, the drive transistors (Tph15 Tph") also on their control electrode with the inverted Driving clock signal (yj) of the other driving direction mentioned.