KR970063927A

KR970063927A - Data-writable ECL T flip-flop

Info

Publication number: KR970063927A
Application number: KR1019960004756A
Authority: KR
Inventors: 최호준
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-02-27
Filing date: 1996-02-27
Publication date: 1997-09-12
Also published as: KR0167735B1

Abstract

The present invention relates to an integrated ECL T flip-flop capable of writing data at low power

The present invention relates to an ECL T flip flop for inputting a previous output as an inverting input and a previous inverting output as an input for toggling from a rising edge of a clock signal to a current output signal and an inverting output, A slave stage for inputting an output, inverting the input previous output and outputting it as an output signal, a slave stage for inputting an output signal of the master stage in a high state of the clock signal and outputting it as an output signal of the current flip- And a data writing unit driven by an enable signal to write external data to the master and slave nodes

Description

Data-writable ECL T flip-flop

Since this is a trivial issue, I did not include the contents of the text.

Figure 3 is a block diagram of an ECL T flip-flop according to an embodiment of the present invention.

4 is a detailed circuit diagram of the ECL T flip-flop of FIG. 3;

Claims

The previous output QO is input to the inverting input DB and the previous inverted output QDB is input to the input D to output the current output signal QO and the inverted output QOB at the rising edge of the clock signal CK, ), Which is connected to a first current source (I11) to input a previous output in the low state of the clock signal (CK) and inverts the previous output input to generate an output signal (A, AB) And outputs the output signals A and AB of the master stage 10 in the high state of the clock signal CK to the current flip- (DB) and the input (D) of the master stage 10 and the inverting input (DB) of the master stage 10 are driven by the slave stage 20 which outputs the output signals QO and QOB of the master stage 10 and the enable signal EN applied from the outside, A data writing unit 30 for writing external data ED and external inverted data EDB to the input D and the inverting input DB of the slave stage 20, T flip-flop, characterized in that it comprises.

The data input unit (30) according to claim 1, wherein the data writing unit (30) is driven by an enable signal (EN) and outputs the external data (ED) and the inverted data (DB) A first data writing means 31 for writing the external data ED into the master stage 10 by means of the enable signal EN and outputting the external data ED to the inverting input DB and the input D of the master stage 10, And second data writing means (32) for writing the inverted data (EDB).

3. The semiconductor memory device according to claim 2, wherein the first data write means (31) is configured to output the external data (ED) to the input (D) and the inverted input (DB) of the slave stage (20) A data input section 31a for applying the inverted data EDB and an inverted data EDB to the input section 31a when the enable signal EN is applied from the outside, And a driving unit (31b) for driving the master stage (10) if not applied.

The data input unit (31a) of the first data writing means (31) is connected to the output terminal (A) of the master stage (10) by the inverted data (EDB) A first transistor Q31 for applying external data ED to the input D of the slave stage 20 and a second transistor Q31 for applying external data ED to the base, And a second transistor (Q32) connected to the output terminal (AB) for applying the external inversion data (EDB) to the inverting input (DB) of the slave stage (20).

4. The semiconductor memory device according to claim 3, wherein the drive part (31b) of the first data writing means (31) is connected to the base (EN) (ENB) is applied to the base, the collector is connected to the master stage (10), and the emitter is connected to the base (10). The third transistor (Q33) And a fourth transistor (Q34) connected to the first current source (I11) for driving the master stage (10).

3. The semiconductor memory device according to claim 2, wherein the second data write means (32) comprises a second data write means (32) for supplying external data (ED) to the input (D) and the inverted input (DB) of the slave stage (20) And a data input unit 32a for applying the inverted data EDB to the input unit 32a when the enable signal EN is applied from the outside and the input unit 32a when the enable signal EN is applied from the outside, And a driving unit (32a) for driving the slave stage (20) when the T flip flop (20) is not connected.

The data input unit (32a) of the second data writing means (32) is connected to the output terminal (QO) of the slave stage (20) by the inverted data (EDB) A fifth transistor Q35 for applying external data ED to the inverting input DB of the master stage 10 and a fifth transistor Q35 for applying data ED from the outside to the base and a collector of the slave stage 20 And a sixth transistor (Q36) connected to the inverting output terminal (QOB) for applying the external inversion data (EDB) to the input (D) of the master stage (20).

The drive circuit according to claim 6, characterized in that the drive part (32b) of the second data write means (32) is applied with the enable signal (EN) to the base, the collector to the data input part (32a) and the emitter to the second current source A seventh transistor Q37 for driving the input unit 32a and an inverted enable signal ENB applied to the base and a collector connected to the slave stage 20, And an eighth transistor (Q38) connected to the current source (I21) for driving the slave stage (20).

※ Note: It is disclosed by the contents of the first application.