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KR970067929A - Method for forming a metal layer of a semiconductor - Google Patents

Method for forming a metal layer of a semiconductor Download PDF

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Publication number
KR970067929A
KR970067929A KR1019960009080A KR19960009080A KR970067929A KR 970067929 A KR970067929 A KR 970067929A KR 1019960009080 A KR1019960009080 A KR 1019960009080A KR 19960009080 A KR19960009080 A KR 19960009080A KR 970067929 A KR970067929 A KR 970067929A
Authority
KR
South Korea
Prior art keywords
forming
metal layer
metal
interlayer insulating
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960009080A
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Korean (ko)
Inventor
김영우
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960009080A priority Critical patent/KR970067929A/en
Publication of KR970067929A publication Critical patent/KR970067929A/en
Withdrawn legal-status Critical Current

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Abstract

본 발명은 반도체 소자의 금속층 형성벙법을 제공하는 것으로 비아콘택홀 내에서 노출되는 SOG막을 금속층간 절연막으로 둘러 싸이게 형성하여 SOG막과 금속층이 직접 접촉하지 않게 되므로 로우페일을 감소시켜 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a method of forming a metal layer of a semiconductor device, wherein an SOG film exposed in a via contact hole is surrounded by a metal interlayer insulating film to prevent direct contact between the SOG film and a metal layer, There is an effect that can be improved.

Description

반도체 소자의 금속층 형성방법Method for forming a metal layer of a semiconductor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1A 내지 2E도는 본 발명에 따른 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도.1A to 2E are sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention.

Claims (4)

반도체 소자의 금속층 형성방법에 있어서 실리콘 기판상에 BPSG막을 형성하고, 상기 BPSG막상에 패턴화된 제1금속층을 형성한 후 그 전체 구조 상부면에 제1금속층간 절연막을 형성하는 단계와 상기 단계로부터 상기 제1금속층상에 형성된 상기 제1금속층간 절연막의 상부에 감광막패턴을 형성한 후 그 전체 구조 상부에 SOG막을 형성하는 단계와 상기 단계로부터 상기 감광막패턴이 노출되도록 상기 SOG막을 식각한 후 상기 감광막패턴을 제거하여 상기 제1금속층간 절연막이 노출되도록 하는 단계와 상기 단계로부터 상기 제1금속층이 노출되도록 상기 제1금속층간 절연막을 식각한 후 상기 SOG막 및 제1금속층상에 제2금속층간 절연막을 형성하는 단계와 상기 단계로부터 상기 제1금속층이 노출되도록 상기 제2금슥층간 절연막을 식각한 후 제2금속층을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층 형성방법.A method of forming a metal layer of a semiconductor device, comprising: forming a BPSG film on a silicon substrate; forming a patterned first metal layer on the BPSG film; forming a first metal interlayer insulating film on the entire upper surface of the BPSG film; Forming a photoresist pattern on the first metal interlayer insulating film formed on the first metal layer and then forming an SOG film on the entire structure, and etching the SOG film to expose the photoresist pattern, Removing the first metal interlayer insulating film by removing the pattern and etching the first metal interlayer insulating film to expose the first metal layer from the SOG film and the second metal interlayer insulating film on the first metal layer, And etching the second inter-metal dielectric layer to expose the first metal layer, The method of forming a metal layer of a semiconductor device which comprises the steps of. 제1항에 있어서 상기 제1금속층간 절연막은 1000 내지 2000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속층 형성방법.The method of claim 1, wherein the first inter-metal dielectric layer is formed to a thickness of 1000 to 2000 angstroms. 제1항에 있어서 상기 제2금속층간 절연막은 6000 내지 12000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속층 형성방법.The method of claim 1, wherein the second inter-metal dielectric layer is formed to a thickness of 6000 to 12000 ANGSTROM. 제1항에 있어서 상기 제1금속층은 8000 내지 12000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속층 형성방법.The method of claim 1, wherein the first metal layer is formed to a thickness of 8000 to 12000 ANGSTROM.
KR1019960009080A 1996-03-29 1996-03-29 Method for forming a metal layer of a semiconductor Withdrawn KR970067929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009080A KR970067929A (en) 1996-03-29 1996-03-29 Method for forming a metal layer of a semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009080A KR970067929A (en) 1996-03-29 1996-03-29 Method for forming a metal layer of a semiconductor

Publications (1)

Publication Number Publication Date
KR970067929A true KR970067929A (en) 1997-10-13

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ID=66222500

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960009080A Withdrawn KR970067929A (en) 1996-03-29 1996-03-29 Method for forming a metal layer of a semiconductor

Country Status (1)

Country Link
KR (1) KR970067929A (en)

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Legal Events

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960329

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid