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KR970052582A - Field oxide film formation method of a semiconductor device - Google Patents

Field oxide film formation method of a semiconductor device Download PDF

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Publication number
KR970052582A
KR970052582A KR1019950069487A KR19950069487A KR970052582A KR 970052582 A KR970052582 A KR 970052582A KR 1019950069487 A KR1019950069487 A KR 1019950069487A KR 19950069487 A KR19950069487 A KR 19950069487A KR 970052582 A KR970052582 A KR 970052582A
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KR
South Korea
Prior art keywords
film
nitride film
etching
oxide film
forming
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KR1019950069487A
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Korean (ko)
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KR0172729B1 (en
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019950069487A priority Critical patent/KR0172729B1/en
Publication of KR970052582A publication Critical patent/KR970052582A/en
Application granted granted Critical
Publication of KR0172729B1 publication Critical patent/KR0172729B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 필드 산화막 형성방법에 관한 것으로서, 특히 넓은 활성 영역을 확보할 수 있는 필드 산화막 형성방법에 관한 것으로, 본 발명에 따르면, 질화막 패턴을 구비하여 국부 산화를 시키는 반도체 소자의 필드 산화막 형성방법에 있어서, 질화막 패턴의 양측에 질화막 스페이서를 형성하여, 산화 공정시 버드 빅 현상을 방지할 수 있어 소자의 액티 영역을 증대할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a field oxide film formation method of a semiconductor device, and more particularly to a field oxide film formation method capable of securing a wide active area. According to the present invention, a field oxide film of a semiconductor device having a nitride film pattern for local oxidation is provided. In the forming method, by forming nitride film spacers on both sides of the nitride film pattern, it is possible to prevent the bud big phenomenon during the oxidation process, thereby increasing the active region of the device.

Description

반도체 소자의 필드 산화막 형성방법Field oxide film formation method of a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (a) 내지 (e)는 본 발명의 실시예1에 따른 반도체 소자의 필드 산화막 형성방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a method of forming a field oxide film of a semiconductor device according to Embodiment 1 of the present invention.

Claims (4)

반도체 기판 상부에 열산화막, 제1 질화막 및 절연용 산화막을 형성하는 단계; 상기 절연용 산화막과 제1 질화막을 소정 크기로 패터닝하는 단계; 상기 결과물 상부에 스페이서용 산화막을 증착하고, 블랭킷 식각하여 패터닝된 절연용 산화막과 제1 질화막의 양측벽에 산화막 스페이서를 형성하는 단계; 상기 패터닝된 절연용 산화막의 최상단이 노출되도록 감광막을 매립하는 단계; 상기 노출된 절연용 산화막과 산화막 스페이서를 습식 식각하는 단계; 상기 노출된 기판 영역을 감광막을 마스크로 하여 비등방성 식각하는 단계; 상기 감광막을 제거하는 단계; 상기 구조물 전면에 제2 질화막을 형성하고, 블랭킷 식각하여 식각이 이루어진 제1 질화막 패턴 양측벽에 상기 식각이 이루어진 기판 부위가 매립되도록 질화막 스페이서를 형성하는 단계; 상기 노출된 기판면을 필드 산화하는 단계; 및 상기 기판상에 잔존하는 열산화막과, 제1 질화막 패턴과, 제2 질화막 스페이서를 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.Forming a thermal oxide film, a first nitride film, and an insulating oxide film on the semiconductor substrate; Patterning the insulating oxide film and the first nitride film to a predetermined size; Depositing an oxide film for spacers on the resultant, and forming oxide spacers on both sidewalls of the insulating oxide film and the first nitride film patterned by blanket etching; Embedding a photoresist film so as to expose a top end of the patterned insulating oxide film; Wet etching the exposed insulating oxide layer and the oxide spacer; Anisotropically etching the exposed substrate region using a photosensitive film as a mask; Removing the photosensitive film; Forming a nitride film spacer on the entire surface of the structure, and forming a nitride film spacer so that the substrate portion on which the etching is performed is buried on both sidewalls of the first nitride film pattern on which the etching is performed by blanket etching; Field oxidizing the exposed substrate surface; And removing the remaining thermal oxide film, the first nitride film pattern, and the second nitride film spacer on the substrate. 제1항에 있어서, 상기 절연용 산화막은 1,500 내지 2,000Å 두께로 증착하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method of claim 1, wherein the insulating oxide film is deposited to a thickness of 1,500 to 2,000 GPa. 제1항에 있어서, 상기 제2 질화막의 두께는 1,000 내지 2,000Å인 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.The method of forming a field oxide film of a semiconductor device according to claim 1, wherein the second nitride film has a thickness of 1,000 to 2,000 kPa. 반도체 기판 상부에 열산화막, 폴리실리콘막과 제1 질화막을 순차적으로 형성하는 단계; 상기 제1 질화막을 필드 산화막 예정 부위가 노출되도록 식각하여 제1 질화막 패턴을 형성하는 단계; 상기 제1 질화막 패턴에 의하여 하부의 폴리실리콘막을 소정 깊이만큼 잔존하도록 과소 식각하는 단계; 전체 구조물 상부에 산화막을 증착하고, 블랭킷 식각하여 산화막 스페이서를 형성하는 단계; 상기 패터닝된 제1 질화막 패턴이 노출되도록 감광막을 매립하는 단계; 상기 노출된 산화막 스페이서를 습식 식각하는 단계; 상기 산화막 스페이서의 식각으로 노출된 폴리실리콘막과 열산화막 및 기판 영역을 상기 감광막을 마스크로 하여 비등방성 식각하는 단계; 상기 감광막을 제거하는 단계; 상기 구조물 전면에 제2 질화막을 형성하고, 블랭킷 식각하여 식각이 이루어진 제1 질화막 패턴 양측벽에 상기 식각이 이루어진 기판 부위가 매립되도록 질화막 스페이서를 형성하는 단계; 상기 노출된 기판면을 필드 산화하는 단계; 및 상기 기판상에 잔존하는 열산화막과, 제1 질화막 패턴과, 제2 질화막 스페이서를 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 필드 산화막 형성방법.Sequentially forming a thermal oxide film, a polysilicon film, and a first nitride film on the semiconductor substrate; Etching the first nitride film to expose a predetermined portion of a field oxide film to form a first nitride film pattern; Underetching the polysilicon film below by the first nitride film pattern to a predetermined depth; Depositing an oxide layer on the entire structure and forming a spacer by etching a blanket; Embedding a photoresist film to expose the patterned first nitride film pattern; Wet etching the exposed oxide spacers; Anisotropically etching the polysilicon film, the thermal oxide film, and the substrate region exposed by the etching of the oxide spacer using the photosensitive film as a mask; Removing the photosensitive film; Forming a nitride film spacer on the entire surface of the structure, and forming a nitride film spacer so that the substrate portion on which the etching is performed is buried on both sidewalls of the first nitride film pattern on which the etching is performed by blanket etching; Field oxidizing the exposed substrate surface; And removing the remaining thermal oxide film, the first nitride film pattern, and the second nitride film spacer on the substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069487A 1995-12-30 1995-12-30 Method for forming field oxide film of semiconductor device KR0172729B1 (en)

Priority Applications (1)

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KR1019950069487A KR0172729B1 (en) 1995-12-30 1995-12-30 Method for forming field oxide film of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950069487A KR0172729B1 (en) 1995-12-30 1995-12-30 Method for forming field oxide film of semiconductor device

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KR970052582A true KR970052582A (en) 1997-07-29
KR0172729B1 KR0172729B1 (en) 1999-03-30

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