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KR970002722B1 - Sar receiver processor of atm - Google Patents

Sar receiver processor of atm Download PDF

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Publication number
KR970002722B1
KR970002722B1 KR1019940028197A KR19940028197A KR970002722B1 KR 970002722 B1 KR970002722 B1 KR 970002722B1 KR 1019940028197 A KR1019940028197 A KR 1019940028197A KR 19940028197 A KR19940028197 A KR 19940028197A KR 970002722 B1 KR970002722 B1 KR 970002722B1
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South Korea
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sar
signal
data
atm
counter
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KR1019940028197A
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Korean (ko)
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KR960016266A (en
Inventor
윤성욱
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대우전자 주식회사
배순훈
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5638Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H04L2012/5657Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL3/4

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

An SAR transmission process device for the ATM communication type where embodies the ATM adaptive layer(AAL) 3/4 segment and reassembly sublayer(SAR) to the hardware. The total length of the data where is stored in the FIFO, makes a multiple of 48 bytes. The said process device consist of a message length operation part, a counter and controller, a FIFO controller, a pad generating means, a selection means where selects the FIFO data, the pad or the trailer.

Description

ATM 통신방식의 SAR 수신처리장치SAR receiver processing system of ATM communication system

제 1 도는 본 발명에 따른 SAR 수신처리장치를 도시한 블럭도,1 is a block diagram showing a SAR receiving processing apparatus according to the present invention;

제 2 도는 본 발명에 따른 SAR 수신처리장치를 설명하기 위하여 도시한 것으로서,2 is a view illustrating a SAR receiving processing apparatus according to the present invention.

(a)는 AAL계층의 데이타 흐름 구조를 도시한 도면,(a) shows a data flow structure of an AAL layer;

(b)는 SAR-PDU 데이타의 포맷을 도시한 도면,(b) shows a format of SAR-PDU data;

제 3 도는 일반적인 ATM 셀의 구조를 도시한 것으로,3 illustrates the structure of a typical ATM cell.

(a)는 ATM 셀 전체의 구조를 도시한 도면,(a) shows the structure of the entire ATM cell;

(b)는 사용자망접면(UNI)의 ATM 셀 헤더 구조를 도시한 도면,(b) illustrates an ATM cell header structure of a user network interface (UNI),

(c)는 망노드접면(NNI)의 ATM 셀 헤더 구조를 도시한 도면이다.(c) shows the ATM cell header structure of the network node interface (NNI).

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,3 : FIFO 2 : SAR 수신처리장치1,3: FIFO 2: SAR receiver

21 : 디플립플롭 22 : 카운터 및 제어부21: flip-flop 22: counter and control unit

23 : CRC & FIFO 리드회로 24 : SAR 헤더처리부23: CRC & FIFO lead circuit 24: SAR header processing unit

25 : SAR 트레일러처리부 26 : 조립완료신호발생부25: SAR trailer processing unit 26: Assembly completion signal generation unit

27 : 에러처리부 28 : 길이계산회로27: error processing unit 28: length calculation circuit

본 발명은 비동기 전달모드(ATM : Asynchronous Transfer Mode) 통신방식에서 ATM계층과 상위 사용자 서비스계층을 연결하여 사용자 서비스 정보와 ATM 셀 포맷을 정합시키며 전송오류를 처리하는 ATM 적응계층(AAL : ATM Adaptation Layer)에 관한 것으로, 특히 ATM계층으로부터 수신한 48바이트의 셀 데이타에 SAR 헤더와 SAR 트레일러를 분리하여 에러를 검사하며 데이타를 재조립하여 수렴(CS : Convergence Sublayer)부계층으로 올려보내는 절단 및 조립(SAR : Sagmentation And Resasembly Sublayer)부계층의 수신 처리장치에 관한 것이다.The present invention connects an ATM layer and a higher user service layer in an asynchronous transfer mode (ATM) communication method, matches user service information with an ATM cell format, and processes an ATM error (AAL: ATM Adaptation Layer). In particular, the 48-byte cell data received from the ATM layer separates the SAR header and the SAR trailer, checks for errors, and reassembles and reassembles the data to the convergence (CS) Convergence Sublayer (CS) sublayer. SAR: Sagmentation And Resasembly Sublayer).

최근들어, 통신수단이 급속히 디지탈화되고 광통신의 발달로 인하여 넓은 대역의 전송이 가능해짐에 따라 사용자의 다양한 서비스 요구를 충족시키기 위하여 광대역 ISDN(B-ISDN : Broadband Integrated Services Digital Network)이 등장하였다.Recently, as the means of communication has been rapidly digitalized and the development of optical communication enables transmission of a wide band, broadband ISDN (Broadband Integrated Services Digital Network) has emerged to meet various user's service needs.

즉, B-ISDN은 "광대역 정보통신(이병기, 강민호, 이종희 공저; 교학사; 1994; 서울; p239∼314)"에 기술된 바와 같이 원격검침, 데이타 단말, 전화, 팩시밀리등 협대역 서비스부터 영상전화, 영상회의, 고속 데이타전송, 영상신호전송등과 같은 광대역 서비스까지를 공통적으로 취급하여 전달하기 위한 것으로, 비동기 전달모드(ATM)통신방식을 근본으로 하여 구현된다.That is, B-ISDN is a video telephony service from narrowband services such as remote meter reading, data terminal, telephone, facsimile, etc. It is designed to handle and deliver broadband services such as video conferencing, high-speed data transmission, and video signal transmission in common, and is implemented based on the asynchronous transmission mode (ATM) communication method.

ATM 통신방식이란 ATM 셀(cell)을 비동기식 시분할 다중화(ATDM : Asynchronous Time Division Multiplexing)하여 통신하는 방식으로 셀단위로 전송한다는 점에서 종래의 패킷(packet) 통신방식과 유사하나 ATM 통신방식에서는 실시간 및 항등비트율의 신호까지를 취급하며 국부적인 지역망을 물론 거대한 공중망에 사용되기 위하여 국제표준화 기구에 의해 표준화된 통신방식이다.The ATM communication method is similar to the conventional packet communication method in that ATM cells are transmitted by cell unit by Asynchronous Time Division Multiplexing (ATDM). It handles even the signal of the constant bit rate and is standardized by the International Organization for Standardization to be used not only in local area networks but also in huge public networks.

이러한 ATM 통신방식은 제 3 도의 (a) 내지 (c)에 도시된 바와 같은 ATM 셀을 기본으로 통신하는 바, 사용자의 긴 메시지는 ATM 셀로 분할되어 송신되고, 수신된 ATM 셀들은 다시 하나의 메시지로 재조립되어 상위 사용자에게 전달된다.This ATM communication method is based on ATM cells as shown in (a) to (c) of FIG. 3, where a user's long message is divided into ATM cells and transmitted, and the received ATM cells are again one message. Is reassembled and forwarded to the parent user.

즉, 제 3 도의 (a)에 도시된 바와 같이, ATM 셀은 5바이트(혹은 옥텟)의 헤더구간과 48바이트의 사용자 정보구간으로 구분되고, 5바이트의 헤더는 제 3 도의 (b) 및 (c)에 도시된 바와 같이 사용자망접면(UNI : User Network Interface)에서의 헤더 구조와 망노드접면(NNI : Network Node Interface)에서의 헤더구조로 구분되며, 사용자망접면(UNI)에서의 헤더구조는 제 1 바이트가 4비트의 일반흐름제어(GFC : Generic Flow Control)와 4비트의 가상경로 식별번호(VPI : Virtual Path Identifier)로 이루어지고, 제 2 바이트가 4비트의 가상경로 식별번호(VPI)와 4비트의 가상채널 식별번호(VCI : Virtual Channel Identifier)로 이루어지며, 제 3 바이트는 8비트의 가상채널 식별번호(VCI)로 이루어지고, 제 4 바이트는 4비트의 가상채널 식별번호(VCI)와 3비트의 유료 부하형태(PT : Payload Type)와 1비트의 셀포기순위(CLP : Cell Loss Priority)로 이루어지고, 제 5 바이트는 8비트의 헤더오류제어(HEC : Header Error Control)로 이루어진다.That is, as shown in (a) of FIG. 3, an ATM cell is divided into a header section of 5 bytes (or octets) and a user information section of 48 bytes, and the header of 5 bytes is shown in FIGS. As shown in c), the header structure is divided into a header structure at the user network interface (UNI) and a header structure at the network node interface (NNI), and a header structure at the user network interface (UNI). The first byte consists of 4 bits of Generic Flow Control (GFC) and 4 bits of Virtual Path Identifier (VPI), and the second byte consists of 4 bits of Virtual Path Identifier (VPI). ) And a 4-bit Virtual Channel Identifier (VCI), the third byte consists of an 8-bit Virtual Channel Identifier (VCI), and the fourth byte is a 4-bit Virtual Channel Identifier (VCI). VCI), 3-bit payload type (PT) and 1-bit cell abandonment ranking (CLP) : Cell Loss Priority, and the fifth byte is composed of 8-bit header error control (HEC).

또한, 제 3 도의 (c)의 도시된 바와 같은 망노드접면(NNI)에서의 헤더구조를 살펴보면, 앞서 설명한 사용자망접면(UNI)의 첫번째 바이트에 있는 일반흐름제어(GFC)가 가상경로 식별번호(VPI)로 사용되는 것을 제외하고는 사용자망접면(NNI)의 헤더구조와 동일한 것을 알 수 있다.Also, looking at the header structure of the network node interface (NNI) as shown in FIG. 3C, the general flow control (GFC) in the first byte of the user network interface (UNI) described above is a virtual path identification number. It can be seen that it is the same as the header structure of NNI except that it is used as (VPI).

이러한 ATM 통신방식은 다음 [표 1]에서와 같이 계층적인 구조를 이루고, 각각의 계층별로 표준화된 기준을 가지고 있다.This ATM communication method has a hierarchical structure as shown in [Table 1] and has standardized standards for each layer.

[표 1] TABLE 1

"""""""" 10 9 5 4 """""""" 10 9 5 4

&&

&&

"""""" ""

Claims (1)

ATM 통신방식의 AAL 3/4 프로토콜에 따른 SAR 수신처리장치에 있어서, 지연된 전송완료(SAR-UNITDATA-invoke) 신호를 수신하여 소정의 카운트값을 카운트하고 CRC 및 FIFO 제어신호들을 발생하는 카운터 및 제어부(22); 상기 전송완료(SAR-UNITDATA-invoke) 신호를 수신하여 상기 카운터 및 제어부(22)의 제어신호에 따라 세그먼트 데이타를 순차적으로 읽어와 48바이트 단위로 CRC 처리하여 에러를 검출 및 정정하며 데이타를 전달하는 CRC 및 FIFO 리드회로(23); 상기 카운터 및 제어부(22)의 제어신호(s-h)에 따라 48바이트의 데이타에서 SAR 헤더를 분리한 후 에러가 발생했는지를 검사하는 SAR 헤더처리부(24); 상기 카운터 및 제어부(22)의 제어신호(s-t)에 따라 48바이트의 데이타에서 SAR 트레일러를 분리한 후 에러가 발생했는지를 검사하는 SAR 트레일러처리부(25); 상기 카운터 및 제어부(22)가 하나의 세그먼트에 대해 카운트를 완료하고 발생한 카운트완료(complete) 신호와 수신된 세그먼트의 헤더에 포함된 세그먼트형태 데이타(rcv-st)를 입력하여 하나의 메시지를 조립완료한 후 조립완료(CPCS-UNITDATA-invoke) 신호를 발생하는 조립완료신호발생부(26); 상기 SAR 헤더처리부(24), SAR 트레일러처리부(25), CRC 및 FIFO 리드회로(23)로부터 에러검출신호를 입력하여 메시지 조립후 사용자 어보트(SAR-U-Abort) 신호 또는 프로토콜 어보트(SAR-U-Abort) 신호를 발생하는 에러처리부(27); 및 SAR 트레일러처리부(25)로부터 길이표시(LI) 데이타를 입력하여 메세지의 전체 길이를 계산하여 길이 계산회로(28)를 구비하여 하위 ATM계층으로부터 수신한 48바이트의 세그먼트에서 2바이트의 SAR 헤더와 2바이트의 SAR 트레일러를 분리하여 에러를 검사하고, 각 관련된 세그먼트들을 조립하여 하나의 메시지로 복원한 후 CPCS계층으로 올려보내는 것을 특징으로 하는 ATM 통신방식의 SAR 수신처리장치.A SAR receiving processing apparatus according to AAL 3/4 protocol of ATM communication system, comprising: a counter and a controller for receiving a delayed SAR-UNITDATA-invoke signal to count a predetermined count value and generating CRC and FIFO control signals (22); Receives the SAR-UNITDATA-invoke signal, sequentially reads segment data according to the counter and control signals of the controller 22, CRC processes the data in 48-byte units, detects and corrects errors, and delivers data. A CRC and FIFO lead circuit 23; A SAR header processor (24) for checking whether an error has occurred after separating the SAR header from 48 bytes of data according to the counter and the control signal (s-h) of the control unit (22); A SAR trailer processing unit (25) for checking whether an error has occurred after separating the SAR trailer from 48 bytes of data according to the counter and the control signal (s-t) of the control unit (22); The counter and the control unit 22 completes counting for one segment and inputs the generated count complete signal and the segment type data (rcv-st) included in the header of the received segment to complete assembling one message. An assembly completion signal generator 26 generating a CPCS-UNITDATA-invoke signal; After inputting an error detection signal from the SAR header processing unit 24, the SAR trailer processing unit 25, the CRC and the FIFO lead circuit 23, a user abort signal or protocol abort (SAR) is assembled. An error processing unit 27 generating a -U-Abort) signal; And a length calculation circuit 28 for inputting the length indication (LI) data from the SAR trailer processing unit 25 to calculate the total length of the message, and having a length calculation circuit 28 for the two-byte SAR header in the 48-byte segment received from the lower ATM layer. SAR communication system of the ATM communication method characterized in that the two-byte SAR trailer to check the error, and to assemble each of the relevant segments to restore a single message and to upload to the CPCS layer.
KR1019940028197A 1994-10-31 1994-10-31 Sar receiver processor of atm KR970002722B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101435805B1 (en) * 2007-11-07 2014-08-29 엘지전자 주식회사 Method and apparatus for correcting error of the received message in terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101435805B1 (en) * 2007-11-07 2014-08-29 엘지전자 주식회사 Method and apparatus for correcting error of the received message in terminal

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