KR970008446B1 - A static memory device and method of fabricating the same - Google Patents

Abstract

a semiconductor substrate with a trench having a bottom surface and both side walls; a first N+ doping region formed in the semiconductor substrate; a second P+ doping region formed in the semiconductor substrate by including the first doping region; a third P+ doping region formed in the semiconductor substrate which is adjacent to the top of the trench; a first insulating layer which is formed inside the trench and on the upper surface of the semiconductor substrate and has an open aperture revealing the first doping region; a gate electrode layer formed on the surface of the first insulating layer; a second insulating layer formed on the upper surface of the gate electrode layer; a third insulating layer formed on the side of the gate electrode layer; a semiconductor layer which is formed on the bottom of the trench and is contacted to the first doping region; and a forth N+ doping region formed on the upper part of the trench and on the upper surface of the second insulating layer.

Description

Semiconductor device and manufacturing method thereof

1 is a circuit diagram illustrating a latch memory cell.

2 is a circuit diagram showing a pair of cross coupled PMOS transistors and an NMOS transistor.

3 is a cross-sectional view illustrating a conventional semiconductor device corresponding to FIG. 2.

4 is a circuit diagram illustrating a pair of series-coupled PMOS transistors and NMOS transistors.

FIG. 5 is a cross-sectional view illustrating a semiconductor device according to the present invention corresponding to FIG. 4.

6A through 6F sequentially illustrate cross-sectional views of intermediate structures according to a process sequence of a semiconductor manufacturing method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a pair of series-coupled PMOS transistors and NMOS transistors included in a unit memory cell of a static random access memory (SRAM) and a method of manufacturing the same. .

FIG. 1 is a circuit diagram illustrating a latch memory cell that is the basis of an SRAM memory cell. The latch memory cell includes two PMOS transistors Q1 and Q2 and two NMOS transistors Q3 and Q4.

In FIG. 1, the PMOS transistor Q1 and the NMOS transistor Q3 are connected in series between the highest power supply voltage V _CC and the lowest power supply voltage V _SS . In other words, the source S1 of the PMOS transistor Q1 and the drain D3 of the NMOS transistor Q3 are coupled. The lowest power supply voltage V _SS is usually referred to as ground potential. The source S1 of the PMOS transistor Q1 is also coupled to the input terminal V _IN . Meanwhile, the PMOS transistor Q2 and the NMOS transistor Q4 are also connected in series between the highest power supply voltage V _CC and the lowest power supply voltage V _SS , and the source S2 of the PMOS transistor Q2 is output. It is coupled to the terminal V _OUT .

The gate G1 of the PMOS transistor Q1 is coupled to the gate G3 of the NMOS transistor Q3 and coupled to the output terminal V _OUT , and the gate G2 of the PMOS transistor Q2 is connected to the NMOS transistor ( It is coupled to the gate G4 of Q4) and coupled to the input terminal V _IN .

In such a circuit, the PMOS transistor Q1 and the PMOS transistor Q2 act as loads, and the data signal is applied to the input terminal V _IN . For example, when a data signal of logic " high " is applied to the input terminal V _IN , the PMOS transistor Q2 is in a high impedance state while the NMOS transistor Q4 is conductive. Therefore, the potential of the output terminal V _OUT becomes equal to the lowest power supply voltage V _SS , whereby a logic "low" signal is output. The logic " low " signal at output terminal V _OUT is also applied to the gate of PMOS transistor Q1 to conduct PMOS transistor Q1 while leaving NMOS transistor Q3 in a high impedance state, resulting in _Allow input terminal (V _IN ) to be logic "high". Thus, the data signal is latched into a latch memory cell consisting of four transistors while the highest supply voltage V _CC is supplied.

As can be seen from the above, since the latch memory cell that forms the basis of the SRAM memory is composed of a plurality of transistors, in order to achieve high integration of the SRAM, a structure capable of more effectively integrating transistors should be proposed.

Structures that meet these requirements include the reduction of the required area of the unit memory cell by configuring either the PMOS transistor or the NMOS transistor as a vertical MOS transistor.

FIG. 3 illustrates one of these structures, which is disclosed in US Pat. No. 5,016,070, and a circuit diagram corresponding thereto is shown in FIG.

As can be seen in FIG. 2, the structure of FIG. 3 is an implementation of the PMOS transistor Q2 and the NMOS transistors Q3 among the transistors included in the latch memory cell shown in FIG. This structure is the same as implementing the PMOS transistor Q1 and the NMOS transistors Q4 shown in FIG. 1 when the input terminal V _IN and the output terminal V _OUT are alternately connected.

Next, a conventional semiconductor device will be described with reference to FIG. 3.

In FIG. 3, a field insulating layer 302 is selectively formed on the semiconductor substrate 300 to separate elements formed therein from selectively adjacent devices. A trench is formed in an active region defined by the field insulating layer 302, and an N + doped region 303 is formed below the bottom surface of the trench in the semiconductor substrate 300, and is formed on the surface of the semiconductor substrate 300. An insulating layer 304 having an opening exposing the N + doped region 303 is formed. Two N + doped regions 301 are formed on both sides of the trench in the semiconductor substrate 300, and the gate of the NMOS transistor is maintained on the upper surface of the insulating layer 304 and on the inner wall of the trench. The electrode layer 306 is formed. An insulating layer 305 is formed on the sidewall of the trench of the gate electrode layer 306 of the NMOS transistor, and an insulating layer 307 having a predetermined opening is formed on the upper surface. The gate electrode layer 308 of the PMOS transistor is formed on the upper surface of the insulating layer 307 and in the trench where the upper surface of the N + doped region 303 becomes its bottom surface and the insulating layer 305 becomes its sidewall. . Thus, the gate electrode layer 308 of the PMOS transistor is connected to the N + doped region 303 through an opening formed in the insulating layer 304. An insulating layer 309 is formed on the gate electrode layer 309 of the PMOS transistor, but an opening is formed at the same position as the insulating layer 307. A semiconductor region 311 is formed at the center of the insulating layer 309 as a channel of the PMOS transistor, and P + doped regions 310 and 312 are formed at both sides thereof as a source / drain of the PMOS transistor. The P + doped region 312 corresponding to the P + doped region 312 is connected to the gate electrode layer 306 of the NMOS transistor through an opening formed in the insulating layers 307 and 308.

In such a structure, the N + doped region 301, the gate electrode layer 306 of the NMOS transistor, and the N + doped region 303 constitute the NMOS transistor Q3 shown in FIG. 2, and the insulating layer 304 is an NMOS. The semiconductor substrate 300, which acts as a gate insulating film of the transistor Q3 and is adjacent to the sidewalls of the trench, acts as a channel region of the NMOS transistor Q3. Meanwhile, the P + doped regions 310 and 312 and the gate electrode layer 308 of the PMOS transistor constitute the PMOS transistor Q2 shown in FIG. 2, and the P + doped regions 310 and 312 respectively form the PMOS transistor Q2. It becomes a source / drain region. Here, the insulating layer 309 serves as a gate insulating film of the PMOS transistor Q2, and the semiconductor layer 311 serves as a channel region of the PMOS transistor Q2.

However, this structure has a disadvantage in that the PMOS transistor is not formed as a vertical transistor, as can be seen in the figure, and thus, the cell size cannot be effectively reduced.

Accordingly, it is an object of the present invention to provide a semiconductor device which can be effectively reduced in cell size and manufactured by an easier process.

Another object of the present invention is to provide a method of manufacturing the semiconductor device.

In order to achieve the above object, the semiconductor device according to the present invention comprises a semiconductor substrate having a trench having a bottom surface and both side walls; A first doped region formed in the semiconductor substrate adjacent to the bottom of the bottom surface of the trench and having a first conductivity type; A second doped region formed in the semiconductor substrate including the first conductive doped first region and having a second conductive type; At least one third doped region formed in a semiconductor substrate adjacent to a portion adjacent the upper portion of the trench and having a second conductivity type; A first insulating layer having an opening exposing the first doped region and formed on an inner surface of the trench and an upper surface of the semiconductor substrate; A gate electrode layer formed on the surface of the first insulating layer while maintaining the trench structure and exposing the first doped region; A second insulating layer formed on the upper surface of the gate electrode layer; A third insulating layer formed on a side surface of the gate electrode layer while maintaining the trench structure and exposing the first doped region; A semiconductor region connected to the first doped region and formed in the lower side of the trench; And a fourth doped region formed on an inner upper side of the trench and on an upper surface of the second insulating layer, the fourth doped region having a first conductivity type.

In a preferred embodiment, the semiconductor substrate adjacent to the sidewall of the trench is doped with impurities for the channel of the second conductive MOS transistor, and the semiconductor region is doped with impurities for the channel of the first conductive MOS transistor. It is.

In order to achieve the above another object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a first doped region by doping a first conductive type impurities in a semiconductor substrate; Selectively etching a semiconductor substrate positioned at a central portion and a lower portion of the first doped region to form a first trench having a bottom surface and sidewalls; Forming a first insulating layer on the resultant while maintaining the first trench structure; Forming a gate electrode material layer filling the interior of the first trench and positioned over the first insulating layer; Forming a second insulating layer over the gate electrode material layer; The second insulating layer, the gate electrode material layer, and the first insulating layer included in the first trench are sequentially and selectively etched to form a bottom surface of the semiconductor substrate and both side walls of the gate electrode material layer. Forming a second trench having; Forming a second doped region by doping a first conductive type impurity on a semiconductor substrate corresponding to a bottom surface of the second trench; Forming a third doped region by doping a second conductive impurity in the second doped region; Forming a third insulating layer on both side walls of the second trench; Forming a semiconductor material layer filling the second trench on a surface of the second insulating layer and the third insulating layer; And forming a third doped region by doping a second conductive impurity into the semiconductor material layer adjacent to the upper portion of the second trench.

In example embodiments, the method may further include selectively etching the semiconductor material layer after forming the fourth doped region.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a circuit diagram showing a pair of series-coupled PMOS transistors and NMOS transistors, and shows a corresponding circuit diagram of the semiconductor device to be implemented by the present invention.

Comparing the circuit shown in FIG. 4 with the circuit shown in FIG. 4, it can be seen that the circuit shown in FIG. 4 is part of the latch memory cell shown in FIG. 1. In addition, it can be seen that when the circuit shown in FIG. 4 and the similar circuit are connected to each other to form a latch memory cell.

FIG. 5 is a cross-sectional view illustrating a semiconductor device according to the present invention corresponding to FIG. 4.

Referring to FIG. 5, a field insulating layer 501 is selectively formed on the semiconductor substrate 500 to define an active region in which an element is to be formed. A trench having a bottom surface and sidewalls is formed in the semiconductor substrate 500 corresponding to the active region, and N + doped regions 502 are formed in the semiconductor substrate 500 adjacent to both sides of the trench. . A P + doped region 504 is formed in the semiconductor substrate 500 corresponding to the bottom surface of the trench, and an N + doped region 503 including the P + doped region 504 therein is formed under the semiconductor substrate 500.

In addition, an insulating layer 505 is formed on the surface of the semiconductor substrate 500 while maintaining an opening for exposing the P + doped region 504 and maintaining the trench structure. Similarly, the gate electrode layer 507 is formed while having an opening exposing the P + doped region 504 and maintaining the trench structure. The lower part of the gate electrode layer 507 is electrically insulated from the regions formed around the insulating layer 505, and the insulating layer is formed on the sidewalls of another trench formed by the gate electrode side 507. 506 is formed, and an insulating layer 508 is formed on the upper surface of the gate electrode layer 507.

A semiconductor region 509 is formed on the inner lower side of the trench formed by the gate electrode layer 507 while being connected to the P + doped region 504, and on the inner surface of the trench and on the upper surface of the gate electrode layer 507. The doped region 510 is formed.

In such a structure, the semiconductor region 509 serves as a channel of the PMOS transistor Q1 shown in FIG. 4, and the P + doped region 510 serves as a drain D1 of the PMOS transistor Q1. The P + doped region 504 acts as a source S1 of the PMOS transistor Q1. The gate electrode layer 507 serves as the common gates G1 and G3 of the PMOS transistor Q1 and the NMOS transistor Q3. The insulating layer 506 serves as a gate insulating film of the PMOS transistor Q1 and insulates the gate electrode layer 507. The layer 505 serves as a gate insulating film of the NMOS transistor Q3. The N + doped regions 502 serve as the source S3 of the NMOS transistor Q3, and the N + doped regions 503 serve as the drain D3 of the NMOS transistor Q3. It is connected to the P + doped region 504 to be the source S1. Although not shown in the drawing, the input terminal V _IN for applying the input signal may be formed under the N + doped region 503, and the output terminal V _OUT may form the gate electrode layer 507. Can be extended.

In addition, the semiconductor substrate 500 adjacent to the sidewall of the trench may be formed of polysilicon doped with impurities for the channel of the NMOS transistor Q3, and the semiconductor region 509 may be a channel of the PMOS transistor Q1. It may be composed of polysilicon doped with impurities for.

The semiconductor device having such a structure is not only applied to the latch memory cells included in the SRAM, but as shown in FIG. 4, when the output terminal V _OUT and the input terminal V _IN are interchanged with each other, Since it becomes a general CMOS transistor, it can be used for various logic circuits based on a CMOS transistor.

Next, the semiconductor manufacturing method according to the present invention will be described with reference to FIGS. 6A to 6F.

First, referring to FIG. 6A, after forming a predetermined semiconductor substrate 500, a field insulating layer 501 is selectively formed on the semiconductor substrate 500 to distinguish the active region from the device isolation region. Here, the semiconductor substrate 500 is usually made of a P-type semiconductor material such as a P-type silicon wafer.

Thereafter, N-type impurities are selectively doped into the semiconductor substrate 500 to form an N + doped region 502A. N + doped region 502A is formed to be formed long in the lateral direction as can be seen in the figure.

Subsequently, as shown in FIG. 6B, using a general photolithography process, selectively etching the semiconductor substrate 500 located below and in the center portion of the N + doped region 502A has a bottom surface and both side walls. Form a trench. When the trench is formed in this manner, the N + doped region 502A is divided into two N + doped regions 502.

An insulating layer 505A, such as a thermal oxide film, is then formed on the resultant while maintaining the trench structure.

Referring to FIG. 6C, after the insulating layer 505A is formed, a gate electrode material layer 507A is formed which fills the interior of the trench and is positioned over the insulating layer 505A, and then on the surface thereof. An insulating layer 508A is formed.

Then, as shown in FIG. 6D, a portion of the insulating layer 508A, the gate electrode material layer 507A, and the insulating layer 505A, which is inside and above the trench, is formed through the photolithography process. And selectively etching to form another trench that exposes the semiconductor substrate 500 corresponding to the bottom surface of the trench. By the etching process, the shape of the gate electrode layer 507 is completed.

Subsequently, the N + doped region 503A is formed by doping the exposed semiconductor substrate 500 with N-type impurities. Here, the N + doped region 503A has its diffusion depth and width larger than the P + doped region 504 formed by a subsequent process.

Referring to FIG. 6E, after the N + doped region 503A is formed, the P + doped region 504 is surrounded by the N + doped region 503 by doping the P-type impurities. That is, the portion of the N + doped region 503A to which the P type impurity is doped is converted to the P + doped region 504. Herein, the P + doped region 504 is controlled to have a smaller diffusion depth and width than the N + doped region, so that only the P + doped region 504 is exposed and the N + doped region 503 is not exposed.

Next, an insulating layer 506 is formed on the electrode layer 507 of the gate corresponding to the sidewall of the trench, and polysilicon is formed on the surface composed of the insulating layer 505, the insulating layer 506, and the insulating layer 508. A semiconductor material layer 509A is formed. Here, the semiconductor material layer 509A fills the inside of the trench.

Then, a P-type impurity is doped into the semiconductor material layer 509A corresponding to the upper portion of the trench and patterned through a photolithography process to form a P + doped region 510 and become a channel region of the PMOS transistor. To form an area 509.

As described above, the present invention allows the manufacture of a semiconductor device such as a CMOS transistor in a smaller area, and the manufacturing cost is reduced by achieving high integration of a semiconductor device such as an SRAM.

Although the present invention has been described with reference to specific embodiments, the present invention is not limited to the above embodiments, and modifications and improvements are possible within the scope of ordinary knowledge of those skilled in the art. In particular, the P-type and the N-type can be formed interchangeably.

Claims (3)

A semiconductor substrate having a trench having a bottom surface and side walls; A first doped region formed in the semiconductor substrate adjacent to the bottom of the bottom surface of the trench and having a first conductivity type; A second doped region formed in the semiconductor substrate including the first conductive doped first region and having a third conductive type; At least one third doped region formed in a semiconductor substrate adjacent to a portion adjacent the upper portion of the trench and having a second conductivity type; A first insulating layer having an opening exposing the first doped region and formed on an inner surface of the trench and an upper surface of the semiconductor substrate; A gate electrode layer formed on the surface of the first insulating layer while maintaining the trench structure and exposing the first doped region; A second insulating layer formed on the upper surface of the gate electrode layer; A third insulating layer formed on a side surface of the gate electrode layer while maintaining the trench structure and exposing the first doped region; A semiconductor region connected to the first doped region and formed in the lower side of the trench; And a fourth doped region formed on an inner upper side of the trench and on an upper surface of the second insulating layer, the fourth doped region having a first conductivity type. Forming a first doped region by doping the first conductive dopant into the semiconductor substrate; Selectively etching a semiconductor substrate positioned at a central portion and a lower portion of the first doped region to form a first trench having a bottom surface and sidewalls; Forming a first insulating layer on the resultant while maintaining the first trench structure; Forming a gate electrode material layer filling the interior of the first trench and positioned over the first insulating layer; Forming a second insulating layer over the gate electrode material layer; The second insulating layer, the gate electrode material layer, and the first insulating layer included in the first trench are sequentially and selectively etched to form a bottom surface of the semiconductor substrate and both side walls of the gate electrode material layer. Forming a second trench having; Forming a second doped region by doping a first conductive type impurity on a semiconductor substrate corresponding to a bottom surface of the second trench; Forming a third doped region by doping a second conductive impurity in the second doped region; Forming a third insulating layer on both side walls of the second trench; Forming a semiconductor material layer filling the second trench on a surface of the second insulating layer and the third insulating layer; And forming a fourth doped region by doping a second conductive impurity into the semiconductor material layer adjacent to the upper portion of the second trench. 3. The method of claim 2, further comprising selectively etching the semiconductor material layer after forming the fourth doped region.