KR970004259B1 - Apparatus of ic interface - Google Patents

Abstract

An integrated circuit interface bus control unit embodies a circuit in order to set each mode simultaneously inputting address and data, and controls an integrated circuit. The IC interface bus control unit includes: a key input means for performing address designation and a data input, and setting a data read/write state; a microcomputer for checking a selection state of the key input means, and controlling a data read/write and an operation state; a display means for displaying a present status by a control of the microcomputer; a memory for storing a final data and a user-desired data by a control of the microcomputer; a reset means for initializing the microcomputer when selecting the inititial or reset terminal.

Description

Integrated circuit interface bus control device and method thereof

1 is a block diagram of a conventional integrated circuit interface bus controller.

2 is a block diagram of an integrated circuit interface bus controller of the present invention.

3 is an exemplary view showing a memory map in FIG.

FIG. 4 is a diagram showing the structure of a key input unit and each key in FIG.

6 is an exemplary view of the write / lit format of the present invention.

7 is a signal flow diagram for mode selection of the present invention.

FIG. 8 is an exemplary diagram showing a change in each mode in FIG.

9 is a waveform diagram according to the operation of the present invention.

10 is an exemplary view showing a light mode operation of the present invention.

11 is an exemplary view showing a read mode operation of the present invention.

* Description of the symbols for the main parts of the drawings *

1: display unit 2: microcomputer

3: reset section 4: key input section

5: Memory 6: Address input terminal

7: Data input terminal 8: Mode selection terminal

The present invention relates to I ² C bus control, and more particularly, to an integrated circuit interface bus controller and a method for easily controlling all integrated circuits controlled by an I ² C bus.

Manufacturers who have developed integrated circuits, typically controlled by an I ² C bus, provide a program to control each integrated circuit.

As shown in FIG. 1, a configuration diagram of a conventional bus control apparatus for an integrated circuit test includes a keyboard 101 for selecting a control mode, a computer 102 for executing a control program in accordance with the selection of the keyboard 101, and And a monitor (103) for displaying data information for controlling the integrated circuit (105) by the output signal of the computer (102), and the control data output from the computer (103) for the integrated circuit (IC) (105). It consists of an integrated circuit control interface 104 for transmitting to.

Referring to the operation of the conventional device as follows.

In order to check or control the operation of the developed integrated circuit 105, the integrated circuit 105 is mounted on a demo board or chassis, and a key is input to select a control mode on the keyboard 101. Run the provided control program.

At this time, when the control program is executed on the computer 102, the control screen is displayed on the monitor 103, and when the user selects an operation according to the control mode using the keyboard 101 and sets the integrated circuit interface on the computer 102. At 104, control data is output.

Accordingly, when the integrated circuit control interface 104 transmits control data received from the computer 102 to the integrated circuit 105, the integrated circuit control interface 104 controls the internal data of the integrated circuit 105.

However, these conventional devices require a lot of equipment to control integrated circuits and are difficult to control when one chassis is equipped with integrated circuits controlled through several I ² C buses. When the circuits are mixed, there is a difficult problem of controlling each integrated circuit.

SUMMARY OF THE INVENTION The present invention has been made with an integrated circuit interface bus control apparatus and method for controlling an integrated circuit by implementing a circuit to input an address and data and to set each mode in order to solve the conventional problems as described above. This will be described in detail with reference to the accompanying drawings.

In order to achieve the above object, the present invention designates address and data, key input means for reading / writing and setting of data, and checking the selection state of the key input means to read / write and operate the data. A microcomputer controlling the microcomputer; display means for displaying a current control state under control of the microcomputer; a memory for storing final data and data to be stored by the user under control of the microcomputer; And reset means for initializing the operation of the microcomputer.

2 is an embodiment according to the present invention, as shown therein, address and data are designated by the address input terminal 6 and the data input terminal 7, and read / write and status of the data by the mood select terminal 8. A key input unit 4 for setting the key, a microcomputer 4 for checking the selection state of the key input unit 4, and controlling the read / write and operation states of the data, and control of the microcomputer 2 The display unit 1 for displaying the current control state by the controller; a memory 5 for storing final data and data to be stored by the user under control of the microcomputer 2; and the microcomputer by selection of a reset terminal. It consists of the reset part 3 which sets the operation of (2) initially.

The key input section 4 has a contact structure as shown in FIG. 4, and each contact consists of a numeric key and a mode setting key as shown in FIG. 5. The address input terminal 6 and the data input terminal 7 ) Are the numeric keys "0" to "F", and the mode selector (8) is for write format, lead format, SL / SU / A _H / A _L / F _R setting, RD, +,-, store, recall key. Is done.

The display unit 1 may be composed of an LCD or an LED, and in the present invention, it is assumed that the display unit 1 is composed of a 7-segment LED.

The operation and the effect of the present invention configured as described above will be described in detail with reference to the third circle, FIGS. 6 to 11 as follows.

First, the microcomputer 2 is initialized by the reset unit 3 to which power is supplied. The microcomputer 2 reads the write format, read format, each address, frequency, and data during initialization. Then, the transmission frequency is set and data stored in the memory 5 is transferred to the integrated circuit through the I ² C bus.

As shown in FIG. 3, the memory 5 includes a write format, a lit format, a slab address SL, a sub address SU, an additional high address A _H , an additional row address A _L , It consists of an area for storing the frequency F _r , an area for storing user data, and an area for storing final data.

Then, by pressing the reset terminal, the reset unit 3 performs the same operation as described above by initializing the microcomputer 2.

At this time, when the initialization operation is finished, the microcomputer 2 scans the key input unit 4 having the structure as shown in FIG. 4 and checks the address input terminal 6 and the data input terminal 7 to determine whether there is a scan pulse. When there is no scan pulse, the mode selection terminal 8 is checked.

As a result, each time the user presses each key, the display unit 1 displays the current state under the control of the microcomputer 2 and the current state at the moment when the user inputs the last data into the data input terminal 7 which is a numeric key. In addition, data transmission and reception are performed through the bus line.

That is, when the microcomputer 2 determines the key input and selects the write format key from the mode selection terminal 8, the microcomputer ² displays the final format among the write formats of I ² C as shown in FIG. Selecting the key displays the final format among the lit formats as shown in FIG. 6 (b). Selecting the addressing key (SL / SU / A _H / A _L / F _f ) selects the slab address / sub of the integrated circuit to be controlled. When the address / additional address high / low and frequency are displayed and the lit key RD is selected, the slab data is read in the designated read format and displayed in the designated lit format.

At this time, when the current format is selected by selecting the right format key, the lit format key, the address key, and the read key, the current state can be reset by selecting the increase / decrease key (+) (-). By selecting the key (+) (-), the write format status is changed sequentially as in FIG. 8 (a). In the case of the lit format, the read format status is changed sequentially as in FIG. 8 (b). In this case, as shown in FIG. 8 (C), SL, SU, A _H , S _L , and F _r are sequentially changed by changing the addressing state.

Here, after specifying the write / read format or address, each data is set in 2 digit units using the data input terminal 7, which is a numeric key, and A _H and A _L do not appear unless the read / write format is used for addressing.

When the store computer is selected in the mode selection terminal 8, the microcomputer 2 stores the data so far controlled and the storage address designated by the numeric keys on the display unit 1 as shown in FIG. When 0- 'is displayed and the recall key (RCL) is selected,' RC L- 'is displayed on the display unit 1 as shown in FIG. 8 (bar), and the address designated by the address input terminal 6, which is a numeric key, is displayed. The data stored in the memory 5 is read back and output.

Accordingly, after addressing to the address input terminal 6 and data input to the data input terminal 7 and all the data has been input, the microcomputer ² transfers the data through the I ² C bus and the mode selection terminal. When the lead key RD of (8) is inputted, it is displayed on the display unit 1 as shown in FIG.

The above operation is performed by the signal flow diagram as shown in FIG.

The present invention provides a key scanning process for recognizing an input key and processing data, a display process for displaying the current state as well as input and output data, and a data input / output process for writing or writing data through a bus line; The above operation is controlled by performing a software control process for inputting and outputting final data and user data.

In this case, the present invention performs I ² C control by using the I ² C interface in the microcomputer ² and automatically inputs a command of 1 byte when data is input to the data input terminal 7. In the transmission mode, the slab The address, subaddress and data are transmitted by one byte, and in the read mode, one byte of data is read.

That is, as shown in the waveform diagram of FIG. 10, after the start state is set, data is transmitted. When the transmission is completed and the recognition signal ACK is enabled, the data transmission is stopped.

Here, if an error occurs in the data transmission, the display unit 1 is brought into a 7-segment LED at the lower end by the control of the microcomputer 2 in a blinking state.

Referring to the write and read operation in the above operation is as follows.

First, as shown in FIG. 11 for the data write operation;

If the error count value is "5", the slab address is transmitted and it is determined to be an error. If it is an error, the error count value is decreased, and if the error count value is "0", if it is not "0", the slab address is transmitted and it is an error. The discriminating operation is repeated to set the error flag when the error count value is "0".

After the slab address is transmitted, it is determined whether it is an error. If it is not an error, it is determined whether the write format is "1, 2, 3, 4". Determine if an error.

At this time, if it is not an error, it is determined whether the write format is "9". If it is "9", it is determined whether it is an error after transmitting an additional address high. If not, it is determined that it is an error after transmitting an additional address row. It is then determined whether it is an error.

Accordingly, if it is not an error, it is determined whether n data have been transmitted, and if so, the flag is reset.

In addition, as shown in FIG. 12, when the error count value is "5", the data read operation determines whether the read format is "1, 2, 3, 4" and the read format is "1, 2, 3, 4". Otherwise, it transmits the slab address in the write mode and determines whether it is an error.

At this time, if the error is determined after the slab address transmission, the error count value is abbreviated, and the error count value is "0", and if it is not "0", the read format is "1, 2, 3, 4" and the " When it is not 1, 2, 3, 4 ", the write mode transmits the slab address and repeats the operation of identifying the error. If the error count value is" 0 ", the write module sets the error flag.

After the slab address in the write mode is transmitted, it is determined whether it is an error. If it is not an error, the slab address is transmitted. If it is not an error, the slab address is transmitted. At this time, if it is not an error, it is determined whether the read format is "9". If it is "9", it is determined that it is an error after transmitting an additional address high. If not, it is determined that it is an error after transmitting an additional address row. It is determined whether it is an error by sending an address. If it is not an error, it is determined after reading data.

Accordingly, if the read data is not an error, it is determined whether n data have been read, and when n data is read, the error flag is reset.

Another embodiment of the present invention is to adjust the data of the memory jig (Jig) or the chassis to store the contents of the master memory in another memory by selecting the memory transfer key of the expansion button by mounting the master memory on the kit and stored in the memory It can be used as an adjustment jig to transfer data after designating address of memory by using expansion buffer.

As described in detail above, the present invention can be easily carried by minimization and light weight, and can be applied to factory automation since it can check all integrated circuits controlled by the I ² C bus without a computer and adjust data at the same time. It can be effective.

Claims (5)

A key input means for performing addressing and data input, as well as setting data read / write and status, and a microcomputer for checking the selection state of the key input means to control read / write and operation status of the data, and Display means for displaying the current control state under control of the microcomputer, memory for storing final data and data to be stored by the user under control of the microcomputer, and initializing the operation of the microcomputer at the time of initial or reset terminal selection An integrated circuit interface bus control apparatus comprising: a reset means. 2. The integrated circuit interface bus control apparatus according to claim 1, wherein the microcomputer senses a scan pulse of the key input means to read an address and data if there is a scan pulse and to determine a control mode if there is no scan pulse. The integrated circuit interface bus control apparatus according to claim 1, wherein the key input means comprises an address input terminal for address designation, a data input terminal for data input, and a mode selection terminal for control mode setting. Key scanning process for recognizing input keys and processing data, status display and operation process for displaying the current state and data input / output by key operation, and writing or reading data through bus lines Integrated circuit interface bus control method comprising a data input and output process. The integrated circuit interface bus control method according to claim 4, further comprising a memory control process for repeatedly using the same data set by controlling the input / output of the final data and the user data.