[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

KR960704349A - A METHOD OF TREATING A SEMI-CONDUCTOR WAFER - Google Patents

A METHOD OF TREATING A SEMI-CONDUCTOR WAFER

Info

Publication number
KR960704349A
KR960704349A KR1019960700128A KR19960700128A KR960704349A KR 960704349 A KR960704349 A KR 960704349A KR 1019960700128 A KR1019960700128 A KR 1019960700128A KR 19960700128 A KR19960700128 A KR 19960700128A KR 960704349 A KR960704349 A KR 960704349A
Authority
KR
South Korea
Prior art keywords
layer
diffusion layer
polymer
deposition
wafer
Prior art date
Application number
KR1019960700128A
Other languages
Korean (ko)
Other versions
KR100334855B1 (en
Inventor
데이비드 돕슨 크리스토퍼
키르매즈 애드리안
Original Assignee
데이비드 돕슨 크리스토퍼
일렉트로테크 이큅먼츠 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 데이비드 돕슨 크리스토퍼, 일렉트로테크 이큅먼츠 리미티드 filed Critical 데이비드 돕슨 크리스토퍼
Publication of KR960704349A publication Critical patent/KR960704349A/en
Application granted granted Critical
Publication of KR100334855B1 publication Critical patent/KR100334855B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

반도체 웨이퍼를 처리하는 방법은 웨이퍼의 표면 형상을 평면화하기 위해 웨이퍼사에 쇼트-체인 폴리머를 증착시키는 단계와, 제어된 속도로 폴리머에서 습기를 제거하기 위해 폴리머층의 표면상에 확산층을 증착시키는 단계를 포함한다.A method of processing a semiconductor wafer includes depositing a short-chain polymer on a wafer yarn to planarize the surface shape of the wafer, and depositing a diffusion layer on the surface of the polymer layer to remove moisture from the polymer at a controlled rate. It includes.

Description

반도체 웨이퍼 처리 방법(A METHOD OF TREATING A SEMICONDUCTOR WAFER)A METHOD OF TREATING A SEMICONDUCTOR WAFER

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 확산층의 증착을 제외한 평면화 처리과정의 단계를 예시한다.Figure 1 illustrates the steps of the planarization process excluding the deposition of the diffusion layer.

Claims (11)

제어된 속도로 폴리머에서 습기가 제거되도록 폴리머층의 표면상에 확산층을 증착시키는 단계를 추가로 포함하는 것을 특징으로 하는 전술된 유형의 방법.And depositing a diffusion layer on the surface of the polymer layer such that moisture is removed from the polymer at a controlled rate. 제1항에 있어서, 상기 확산층은 투과성 부재로서 가능하는 것을 특징으로 하는 방법.The method of claim 1, wherein the diffusion layer is possible as a transparent member. 제1항 또는 제2항에 있어서, 상기 확산층은 -20~60℃의 온도 범위에서 증착되는 것을 특징으로 하는 방법.The method of claim 1 or 2, wherein the diffusion layer is deposited in a temperature range of -20 ~ 60 ℃. 제3항에 있어서, 상기 확산층은 0℃ 부근에서 증착되는 것을 특징으로 하는 방법.4. The method of claim 3, wherein the diffusion layer is deposited near 0 ° C. 전술한 항들중 어느 한 항에 있어서, 상기 확산층은 PECVD에 의해 증착되는 것을 특징으로 하는 방법.The method of any one of the preceding claims, wherein the diffusion layer is deposited by PECVD. 전술한 항들중 어느 한 항에 있어서, 상기 확산층은 500 Å정도인 것을 특징으로 하는 방법.The method of any one of the preceding claims, wherein the diffusion layer is on the order of 500 Hz. 전술한 항들중 어느 한 항에 있어서, 예비 가열 단계를 추가로 포함하는 것을 특징으로 하는 방법.The method of any one of the preceding claims, further comprising a preheating step. 제7항에 있어서, 상기 확산층은 크래핑층으로 연속적으로 크래핑되며, 그 후에 웨이퍼가 가열되는 것을 특징으로 하는 방법.8. The method of claim 7, wherein the diffusion layer is continuously scraped into the scraping layer, after which the wafer is heated. 전술한 항들중 어느 한 항에 있어서, 폴리머층의 증착은 하부층 즉 시드층의 증착이 선행되는 것을 특징으로 하는 방법.The method of any one of the preceding claims, wherein the deposition of the polymer layer is preceded by the deposition of an underlying layer, ie, a seed layer. 전술한 항들중 어느 한 항에 있어서, 상기 폴리머층과 확산층의 증착을 위한 "콜드"챔버 및 하부층과 크래핑층의 증착을 위한 "핫" 챔버의 두 가지 챔버를 사용하는 것을 특징으로 하는 방법.The method of any one of the preceding claims, wherein two chambers are used: a "cold" chamber for the deposition of the polymer layer and the diffusion layer and a "hot" chamber for the deposition of the bottom layer and the clipping layer. 전술한 항들중 어느 한 항에 있어서, 하부층을 증착시킨 후에, N2O, O2또는 기체 플라즈마를 포함한 O2로 웨이퍼를 처리하는 단계를 추가로 포함하는 것을 특징으로 하는 방법.The method of any one of the preceding claims, further comprising treating the wafer with O 2 , including N 2 O, O 2, or gas plasma, after depositing the underlying layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960700128A 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer KR100334855B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9409713.6 1994-05-14
GB9409713A GB9409713D0 (en) 1994-05-14 1994-05-14 A method of treating a semi-conductor wafer
PCT/GB1995/001057 WO1995031823A1 (en) 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer

Publications (2)

Publication Number Publication Date
KR960704349A true KR960704349A (en) 1996-08-31
KR100334855B1 KR100334855B1 (en) 2002-11-13

Family

ID=10755170

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960700128A KR100334855B1 (en) 1994-05-14 1995-05-10 A method of treating a semi-conductor wafer

Country Status (8)

Country Link
EP (1) EP0708982A1 (en)
JP (1) JPH09501020A (en)
KR (1) KR100334855B1 (en)
CN (1) CN1128582A (en)
CA (1) CA2167085A1 (en)
GB (1) GB9409713D0 (en)
TW (1) TW307020B (en)
WO (1) WO1995031823A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2734402B1 (en) * 1995-05-15 1997-07-18 Brouquet Pierre PROCESS FOR ELECTRICAL ISOLATION IN MICROELECTRONICS, APPLICABLE TO NARROW CAVITIES, BY DEPOSITION OF OXIDE IN THE VISCOUS STATE AND CORRESPONDING DEVICE
DE19712233C2 (en) * 1996-03-26 2003-12-11 Lg Philips Lcd Co Liquid crystal display and manufacturing method therefor
US7923383B2 (en) 1998-05-21 2011-04-12 Tokyo Electron Limited Method and apparatus for treating a semi-conductor substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2009518C (en) * 1990-02-07 2000-10-17 Luc Ouellet Spin-on glass processing technique for the fabrication of semiconductor device
DE69327176T2 (en) * 1992-07-04 2000-05-31 Trikon Equipments Ltd., Littleton-Upon-Severn TREATMENT METHOD FOR A SEMICONDUCTOR DISC.

Also Published As

Publication number Publication date
KR100334855B1 (en) 2002-11-13
CA2167085A1 (en) 1995-11-23
CN1128582A (en) 1996-08-07
WO1995031823A1 (en) 1995-11-23
TW307020B (en) 1997-06-01
GB9409713D0 (en) 1994-07-06
JPH09501020A (en) 1997-01-28
EP0708982A1 (en) 1996-05-01

Similar Documents

Publication Publication Date Title
SE8103043L (en) SET TO MAKE P-DOPPED SILICONE MOVIES AND THESE MANUFACTURED DONES
KR960035890A (en) Modification of Titanium Carbo nitride Layer
KR960030314A (en) Low Temperature Deposition of Silicon Dioxide Using Organosilane
KR880003403A (en) Chemical Vapor Growth and Its Apparatus
ES2169543T3 (en) ANTI-ADHERENT COATING RESISTANT TO ELEVATED TEMPERATURE AND SCRATCHES.
KR880010479A (en) How to make a titanium / titanium nitride bilayer
DE69736969D1 (en) Method of treating the surface of semiconductive substrates
TW348272B (en) Method and apparatus for depositing planar and highly oriented layers
KR900006474A (en) Plasma processing method and products thereof
KR890017776A (en) Metal Processing Process for Semiconductor Devices
KR920003445A (en) Heat treatment film forming apparatus and method
WO2000077830A8 (en) A method for the preparation of an epitaxial silicon wafer with intrinsic gettering
KR920008838A (en) Silicon single crystal substrate manufacturing method
KR960704349A (en) A METHOD OF TREATING A SEMI-CONDUCTOR WAFER
KR930013201A (en) Deposition method for product coating
KR930006823A (en) Manufacturing Method of Semiconductor Device
ATE279784T1 (en) METHOD FOR BORON DOPING WAFERS USING A VERTICAL FURNACE SYSTEM
KR970052190A (en) Metal layer formation method of semiconductor device
KR910020813A (en) Method of Forming Fine Metal Wiring in Semiconductor Manufacturing
KR970052433A (en) Metal layer formation method of semiconductor device
KR970003667A (en) Method for forming conductive layer of semiconductor device
SE0203332D0 (en) Apparatus for performing a surface treatment of a substrate under vacuum
KR970052107A (en) Manufacturing Method of Semiconductor Device
JPS6489423A (en) Manufacture of epitaxial si substrate
JPS57111212A (en) Surface coating method of substrate with metallic nitride

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
N231 Notification of change of applicant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130321

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20140319

Year of fee payment: 13

EXPY Expiration of term