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KR960027883A - PDU Analysis Circuit in SSCOP Sublayer - Google Patents

PDU Analysis Circuit in SSCOP Sublayer Download PDF

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Publication number
KR960027883A
KR960027883A KR1019940038191A KR19940038191A KR960027883A KR 960027883 A KR960027883 A KR 960027883A KR 1019940038191 A KR1019940038191 A KR 1019940038191A KR 19940038191 A KR19940038191 A KR 19940038191A KR 960027883 A KR960027883 A KR 960027883A
Authority
KR
South Korea
Prior art keywords
fifo
control unit
control signal
signal
reading
Prior art date
Application number
KR1019940038191A
Other languages
Korean (ko)
Other versions
KR0129179B1 (en
Inventor
윤성욱
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019940038191A priority Critical patent/KR0129179B1/en
Publication of KR960027883A publication Critical patent/KR960027883A/en
Application granted granted Critical
Publication of KR0129179B1 publication Critical patent/KR0129179B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/563—Signalling, e.g. protocols, reference model
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

본 발명은 비동기 전달모드(ATM: Asynchronous Transfer Mode)통신방식을 기본전달수단으로 하는 B-ISDN에서 사용하는 신호프로토콜을 구현하는 회로에 관한 것으로, 소정의 메시지 도착신호에 의해 다운카운팅하며 제어신호를 출력하게 된다운카운터(10)와; 상기 다운카운터(10)의 제어신호에 의해 수신 AAL FIFO(12)에 저장된 메시지를 읽어들이는 FIFO 읽기제어부(14)와; 상기 다운카운터(10)의 제어신호에 의해 수신큐 FIFO(18)에 상기 FIFO읽기 제어부(14)에 의해 읽힌 데이터를기록할 수 있게 해주는 FIFO 기록제어부(16); 상기 FIFO 읽기제어부(14)로부터 소정의 워드를 읽어 들이는 다수개의 32비트레지스터(20,22,24); 상기 각각 레지스터(20,22,24)에 저장된 워드를 읽어 들여 소정의 상태변수들을 디먹스(DEMUX)하여 상태변수저장부(28)에 저장하게 된 디먹스(26)로 구성된 PDU해석회로이다.The present invention relates to a circuit for implementing a signal protocol used in the B-ISDN as a basic transfer means using an Asynchronous Transfer Mode (ATM) communication method, and down-counting by a predetermined message arrival signal and controlling a control signal. A counter 10 to output; A FIFO read control unit 14 for reading a message stored in the received AAL FIFO 12 according to the control signal of the down counter 10; A FIFO recording control unit (16) which enables the data read by the FIFO read control unit (14) to be written to the reception queue FIFO (18) by the control signal of the down counter (10); A plurality of 32-bit registers (20, 22, 24) for reading a predetermined word from the FIFO read control unit (14); The PDU analysis circuit is composed of a demux 26 that reads the words stored in the registers 20, 22, and 24, and demuxes certain state variables to store them in the state variable storage unit 28.

Description

SSCOP부계층에서 PDU해석회로PDU Analysis Circuit in SSCOP Sublayer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 SSCOP부계층의 PDU생성회로를 도시한 구성블럭도이다.4 is a block diagram showing a PDU generation circuit of the SSCOP sublayer according to the present invention.

Claims (1)

소정의 메시지 도착신호에 의해 다운카운팅하며 제어신호를 출력하게 된 다운카운터(10)와; 상기 다운카운터(10)의 제어신호에 의해 수신AAL FIFO(12)에 저장된 메시지를 읽어들이는 FIFO 읽기제어부(14)와; 상기 다운카운터(10)의 제어신호에 의해 수신큐 FIFO(18)에 상기 FIFO 읽기제어부(14)에 의해 읽힌 데이터를 기록할 수 있게 해주는 FIFO 기록제어부(16); 상기 FIFO 읽기제어부(14)로부터 소정의 워드를 읽어 들이는 다수개의 32비트 레지스터(20,22,24); 상기 각각 레지스터(20,22,24)에 저장된 워드를 읽어 들여 소정의 상태변수들을 디먹스(DEMUX)하여 상태 변수저장부(28)에 저장하게 된 디먹스(26)로 구성된 PDU해석회로.A down counter 10 which counts down by a predetermined message arrival signal and outputs a control signal; A FIFO read control unit 14 for reading a message stored in the received AAL FIFO 12 according to the control signal of the down counter 10; A FIFO recording control unit (16) which enables the data read by the FIFO read control unit (14) to be written to the reception queue FIFO (18) by the control signal of the down counter (10); A plurality of 32-bit registers (20, 22, 24) for reading a predetermined word from the FIFO read control unit (14); And a demux (26) configured to read the words stored in the registers (20, 22, and 24), and demux predetermined state variables and store the demux (26) in the state variable storage unit (28). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038191A 1994-12-28 1994-12-28 A circuit for decoding pdu in sscop sublayer KR0129179B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038191A KR0129179B1 (en) 1994-12-28 1994-12-28 A circuit for decoding pdu in sscop sublayer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038191A KR0129179B1 (en) 1994-12-28 1994-12-28 A circuit for decoding pdu in sscop sublayer

Publications (2)

Publication Number Publication Date
KR960027883A true KR960027883A (en) 1996-07-22
KR0129179B1 KR0129179B1 (en) 1998-04-08

Family

ID=19404450

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038191A KR0129179B1 (en) 1994-12-28 1994-12-28 A circuit for decoding pdu in sscop sublayer

Country Status (1)

Country Link
KR (1) KR0129179B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100415141B1 (en) * 2000-04-06 2004-01-14 주식회사 로이트 Analysis tool of generalized protocol to analyze PDU of various protocol

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101466977B1 (en) * 2010-12-07 2014-12-02 현대중공업 주식회사 GIS for Switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100415141B1 (en) * 2000-04-06 2004-01-14 주식회사 로이트 Analysis tool of generalized protocol to analyze PDU of various protocol

Also Published As

Publication number Publication date
KR0129179B1 (en) 1998-04-08

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