KR960011559B1 - Semiconductor integrated circuit with initializing circuit - Google Patents

Abstract

None.

Description

Semiconductor Integrated Circuits with Initialization Circuits

1 is a functional block diagram of an initialization circuit according to the present invention.

2 is a timing diagram showing a power-up operation characteristic of a chip in FIG.

3 is a circuit diagram showing an embodiment of power-up circuit 2 in FIG.

4 is a circuit diagram showing an embodiment of a timer 8 in FIG.

5 schematically shows the internal construction of the counter 10 in FIG.

6 is a timing diagram showing characteristics of an output signal of the output operation of FIG.

7 is a circuit diagram showing the detailed circuit configuration of FIG.

8 is a diagram illustrating a circuit configuration in which an output signal of an initialization circuit is applied on an internal path of a RAS signal.

9 is a timing diagram showing the characteristics of the output signal in the output operation of FIG.

10 is another embodiment showing a circuit configuration in which an output signal of an initialization circuit is applied on an internal path of a RAS signal.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which an initialization circuit is embedded to perform an initialization operation independently without depending on a system.

In the case of a semiconductor integrated circuit, all the circuits inside the chip during power-on by the system are initialized to a predetermined state so as to be operable. Therefore, in order to be initialized to such a predetermined state, a chip is provided with means for enabling initialization from an input signal by the system.

In this regard, U.S. Patent No. 4,365,174 discloses a technique in which a pulse counter is provided inside a chip to count an input signal during a power-up operation so as to output a specific pulse to operate the chip in a desired state. This technique accurately detects the voltage level of the power supply voltage supplied from the power-up system to drive the power-up operation of the chip. In a conventional memory device having a dynamic cell type structure requiring an initialization cycle, when a power-up defect occurs due to a main clock in the device during power-up, It is necessary to reset the power applied from the outside as the power supply voltage VCC so that the device can operate normally. In other words, if a main clock occurs, no action except power-reset can occur. In addition, after the power is applied, the internal node of the device needs to be initialized as a warming-up cycle.

Accordingly, an object of the present invention is to provide a semiconductor integrated circuit incorporating an initialization circuit.

Another object of the present invention is to provide a semiconductor integrated circuit which enables normal operation after power-up by forcibly cycling the main clock inside the chip even when the main clock is generated.

Another object of the present invention is to provide an initialization circuit for generating an initialization cycle performed by the system within the device, from which the power-shutdown is performed by initializing the power node inside the chip and forcibly cycling the power-up main clock. The present invention provides a semiconductor integrated circuit that always operates normally.

In order to achieve the objects of the present invention optimally, the present invention is characterized in that it is a semiconductor integrated circuit containing an initialization circuit for cycling the initialization cycle by the generation of a clock inside the device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same parts in the figures represent the same reference signs wherever possible.

In the following description, numerous specific details are set forth to provide a more general understanding of the invention, such as an initialization circuit, a counter and timer constituting the initialization circuit, and an embodiment in which the initialization circuit is applied to an input buffer. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

Among the terms to be described below, the term "initialization circuit" is defined as a circuit that drives the initialization operation of the internal power-up circuits of the chip, and at the same time, the initialization operation normally takes place without the help of the system in the event of power-up failure.

The functional block configuration of the initialization circuit according to the present invention is shown in FIG. The configuration characteristic of FIG. 1 is that the initialization circuit according to the present invention comprises a power-up circuit, a counter and a timer. Looking at the configuration of Figure 1 as follows. A power-supply circuit 2 for enabling the operation of each circuit in the chip from the time of supply of an externally supplied power supply voltage, a NAND gate 4 for inputting the output signal? VCCH of the power-supplement circuit 2, and the NAND gate An inverter 6 connected to the output terminal of 4, a timer 8 for inputting the output signal ψTE of the inverter 6, an initialization signal ψINIT outputted from the timer 8, this initialization signal ψINIT and an initialization signal ψINIT are inverted through the inverter 12. The signal and ψVCCH and ψVCCH are inputted through the inverter 14 respectively to count the timer output signal, and the counter 10 is made up of the output signal Qx serving as one input of the NAND gate 4.

FIG. 2 is a timing diagram of the signals of FIG. Referring to the timing diagram of FIG. 2, the characteristics of the signals of FIG. 1 are as follows. The output signal? VCCH of the power-supply circuit 2 is a signal that is active, that is, enabled high when the power supply voltage VCC reaches a constant voltage level. The output signal? INIT of the timer 8 is a signal for cycling at a constant cycle when the output signal? TE of the inverter 6 becomes active after the power supply voltage VCC is applied. In this case, the number of times the ψINIT signal cycles is determined by the number of unit counters constituting the counter 10. Specifically, the number of unit counters is (2 ^(N-1) -1), where N is the number of unit counters. The output signal of the inverter 6,? TE, is an enable signal of the timer 8 and is a signal that is active while Qx and? VCCH become high. Qx, the output signal of the counter 10, is initially maintained at the power supply voltage VCC level, but after the ψINIT cycles by (2 ^(N-1) -1) circuits, it goes low to stop the operation of the timer 8. to be.

Referring to FIG. 2, operation characteristics of FIG. 1, which is an initialization circuit according to the present invention, are as follows. When the power supply voltage VCC is applied to the chip, that is, when the power-supply voltage of the chip is output, the output signal ψVCCH of the power-supply circuit 2 becomes high when the power supply voltage VCC becomes the desired level (process 16 in FIG. 2). . In this case, the output signal Qx of the counter 10 is initialized to the power supply voltage VCC. Thus, NAND gate 4 is at low output and inverter 6 is at high output, and ψTE is enabled high (process 18 in FIG. 2). From this, the timer 8 is driven and output as a signal for triggering the initialization signal? INIT (step 20). The counter 10 counts the number of triggers of the initialization signal? INIT and outputs the output signal Qx low when a predetermined number of times is reached (step 22 of FIG. 2). When the Qx signal is output low, the NAND gate 4 outputs high, from which the output signal ψTE of the inverter 6 is output low (process 24 in FIG. 2). The triggering operation of the initialization signal? INIT of the timer 8 is stopped and maintained high by the? Signal of going low (step 26 in FIG. 2). Looking at the detailed circuit configuration of the respective circuits of Figure 1 which is the initialization circuit according to the present invention will be described later.

3 is a circuit diagram showing an embodiment of power-up circuit 2 in FIG. FIG. 2 is a conventional structure in this technical field, in which the output value of the output node 30 is determined based on the RC time constant value between the resistor 28 and the capacitor 32. As shown in FIG. The voltage level of ψVCCH may be varied according to the intention of the chip designer or the user in consideration of the size of the resistor 28 or the capacitor 32. On the other hand, such a power-supply circuit is a voltage level detector disclosed in the application No. 91-23343 (name of the invention: a refresh timer corresponding to a plurality of operating voltages) filed in the Republic of Korea by the applicant of December 18, 1991 It can be implemented using a start-up circuit as.

4 is a circuit diagram showing an embodiment of the timer 8 in FIG. The configuration of FIG. 4 is characterized by triggering the initialization signal ψINIT by using the voltage level of the connection node 64 triggering the level from high to low and from low to high by the output operation of the inverter chains 40, 46, 52. do. Here, ψTE is input as an input signal of the inverter 60. When this ψTE is input as high, the inverter 60 outputs low and the NMOS transistor 62 is turned off. In response to the voltage level of the connecting node 64, The initialization signal? INIT can be triggered. When ψTE is input low to the inverter 60, the inverter 60 outputs high, and the Enmo MOS transistor 62 is turned on, so the initialization signal ψINIT remains high. On the other hand, such a configuration can be easily implemented using an oscillator known in the art.

FIG. 5 schematically illustrates the internal structure of the counter 10 in FIG. 1, that is, the connection relationship between the unit counters constituting the counter 10. 5 shows a configuration in which the unit counter is implemented in five stages. In the configuration of FIG. 5, ψVCCH is a signal from power-up circuit 2 of FIG. 1, ψINIT is a signal from Tamer 8 of FIG. 1, and ψINIT is a signal from inverter 12 of FIG. In addition, the unit counters 70, 72, 74, 76, and 78, which are all composed of five, form a counter stage. In FIG. 5, the output signal Qx of the unit counter 78 is initially kept high, and then the input signal ψINIT is configured to be disabled after cycling as many times as desired. That is, the number of times the initialization signal? INIT cycles is determined by the number of unit counters.

FIG. 6 is a timing diagram illustrating characteristics of output signals of each unit counter constituting the counter 10 in the output operation of FIG. 5. As shown in FIG. 6, the output signal Q0 of the unit counter 70 is divided by two times the clock period of the ψINIT signal in response to the cycling of the initialization signal ψINIT. The output signal Q1 of the unit counter 72 is also divided from this Q0 by two times the clock period of the Q0 signal. From this Q1, the output signal Q2 of the unit counter 74 is also divided by two times the clock period of the Q1 signal. As a result, the output signal Qx of the unit counter 78 is the output signal Q3 of the unit counter 76. It is divided by 2 times the clock cycle. The clock period of the output signal Qx of the unit counter 78 becomes the desired width.

FIG. 7 is a circuit diagram showing a detailed circuit configuration of each unit counter in FIG. Looking specifically at the configuration of FIG. 7 shows one of the unit counters 72, 74, and 76 of FIG. 5, except for this one, the other two unit counters have the configuration of FIG. Meanwhile, the unit counters 70 and 78 in the configuration of FIG. 5 can be realized by replacing NOR gates 92 and 106 with NAND gates in the configuration of FIG. In this configuration, the output signal of FIG. Is omitted. On the other hand, such a counter can also be easily implemented by using the counter disclosed in the aforementioned 91-23343.

Each of the detailed circuits as described above can easily realize the initialization circuit of FIG. 1, and the configuration of each of the detailed circuits can be implemented in various ways in consideration of the logic and circuit characteristics of the signal. It will be well known to those skilled in the art.

FIG. 8 is a diagram illustrating an example of a circuit configuration in which an output signal? INIT of an initialization circuit is applied on an inner path of a? RAS signal, that is, a configuration of a? RAS generating circuit. Referring to the configuration of FIG. 8, the low address strobe signal supplied from the system end It is characterized in that the enable and disable of? RAS as a master clock (master) shaped as an internal signal through the input buffer 112 is configured to be controlled and driven by the initialization circuit according to the present invention.

Looking at the configuration of Figure 8, Is entered With input buffer 112, The output signal of the input buffer 112 is formed on the path between the connection nodes 120 to which the output signal is supplied and is controlled by the output signal? TE of the inverter 6 of FIG. A transmission gate 114, a ψINIT transmission gate 118 formed on a path through which the initialization signal ψINIT is input to the connection node 120 and controlled by the ψTE signal, and an input terminal connected to the connection node 120 to output a master clock ψRAS; An inverter 122. here The transmission gate 114 and the ψINIT transmission gate 118 are each implemented as a known transmission gate composed of a PMOS transistor and an NMOS transistor that share channels with each other by a smooth switching operation during signal transmission. Such a configuration feature is that it is possible to directly generate a ψRAS signal as ψINIT which is an initialization signal when desired.

FIG. 9 is a timing diagram showing the characteristics of the output signal ψRAS including the case where the power-sleep main clock of the chip is generated in detail in the output operation of FIG. 8. As shown, when ψTE and ψINIT are generated and input to the circuit of FIG. 8 by the initialization circuit of FIG. 1 according to the present invention at the time of power-up of the chip, the ψRAS signal is automatically generated regardless of the occurrence of the main clock. Is generated. That is, when the ψTE signal is generated high, the timer 8 of FIG. 1 is driven so that the ψINIT signal is cycled and input to the eighth degree. At this time, the ψINIT transmission gate 118 becomes conductive, and the ψINIT signal is input to the connection node 120 according to the conductive path. Then, the cycling operation of the ψRAS signal is enabled in response to the cycling input of the ψINIT signal through the inverter 122 having an input terminal connected to the connection node 120. As is apparent from the prior art, for example, when a main clock occurs, a power reset operation must be forcibly performed depending on an external system, whereas in the present invention, the chip is initialized without relying on an external system. Independently, the initialization operation of the chip can be performed. That is, the initialization operation of the chip is achieved as desired by the generation of the ψRAS signal synchronized with the ψINIT signal. On the other hand, after the chip is initialized according to the timing process shown in FIG. 9, input of the ψINIT signal to the connection node 120 is blocked by disabling the ψTE signal and the ψRAS signal is It is a well known fact that the synchronous operation operates in synchronization with the output signal of the input buffer 112.

FIG. 10 is a circuit diagram illustrating another embodiment of a circuit configuration in which an output signal of an initialization circuit is applied on an inner path of the RAS signal, that is, a RAS generation circuit. The configuration of FIG. 10 is as follows. In other words, Is entered With input buffer 112, The output signal of the input buffer 112 is formed on the path between the connection nodes 134 to which the output signal is supplied and is controlled by the output signal? TE of the inverter 6 in FIG. A transmission gate 126, a NAND gate 128 for inputting the ψTE signal and an initialization signal ψINIT, a PIMO transistor 132 controlled by an output signal of the NANDgate 128 and pulling down a power supply voltage VCC to the connection node 134, and ψINIT An MOS transistor 136 which is controlled by the signal inverted by the inverter 130 and pulls down the voltage of the connection node 134, and an inverter 138 which is connected to the connection node 134 with an input terminal and outputs a master clock? RAS. Referring to FIG. 10, in FIG. 8, in FIG. 10, the generation of the ψRAS signal is indirectly generated by ψINIT and ψTE, whereas in FIG. That is, in FIG. 10, the ψRAS signal is directly generated by the PIO transistor 132 and the ENMO transistor 136. At this time, the operation characteristic of FIG. 10 is made the same as that of FIG. 8, and the timing characteristic is also the same as the timing process shown in FIG.

The ψRAS generating circuits shown in FIGS. 8 and 10 are merely As embodiments configured to apply the output signal of the initialization circuit according to the present invention on the output path of the input buffer, it is obvious that each of these configurations may have various modifications according to the device characteristics of each chip.

As described above, in the semiconductor integrated circuit according to the present invention, since the initialization operation of the chip can be independently performed without the help of an external system by incorporating the circuit into the initialization on the same chip, a bad phenomenon such as a main clock occurs. Even if it is, the initialization of the chip can be realized. In addition, from the point of view of the chip user, efforts such as operating a system for chip initialization are eliminated.

Claims (2)

A semiconductor integrated circuit comprising: a power-supply circuit for enabling the operation of circuits in a chip from a supply point of a power supply voltage supplied from a system, and inputting an initialization signal and an output signal of the power-supply circuit, respectively; A counter for counting signals, a logic circuit for combining the power-supply circuit and an output signal of the counter, and a timer for outputting the initialization signal in response to the output signal of the logic circuit, the main clock in the initialization operation. Wherein the initialization signal is generated regardless of the system. The semiconductor integrated circuit according to claim 1, wherein the logic circuit comprises a NAND gate combining the power-supply circuit and an output signal of a counter, and an inverter connected to an output terminal of the NAND gate.