KR960002065B1 - Fabricating method of semiconductor device - Google Patents

Abstract

The method for manufacturing a semiconductor device having a silicide film formed on a silicon layer, comprises the step of: forming a buffer film on the silicon; forming a silicon and a conduction layer including a high melting point metal on the buffer film; and carrying out heat treatment of the resulting structure. The silicide film of regular thickness is uniformly formed without generation of lumps on an active region of element or on a gate electrode.

Description

Manufacturing Method of Semiconductor Device

1A-1D of FIG. 1 are process steps for manufacturing a semiconductor device according to the prior art.

2A-2E of FIG. 2 are manufacturing process diagrams of a semiconductor device according to one embodiment of the present invention.

3A-3E of FIG. 3 are manufacturing process diagrams of a semiconductor device according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a silicide layer for lowering the resistance of a conductive layer.

As the integration technology of semiconductor devices has been further developed and the achievement of ultra-high integrated circuits (VLSI) of 1 micron or less, the demand for reduction of resistance and capacitance in connection with wiring becomes more prevalent, especially metal oxide (MOS). In the semiconductor structure, the RC delay due to the wiring structure exceeds the delay due to the switching of the gate. The higher the RC (resistance X capacitance) value of the wiring, the more the circuit's operating speed is limited by this RC delay.In particular, the low resistivity wiring structure is a decisive factor in the integration and reliability of semiconductor devices. Therefore, research on this is being actively conducted. In general, much lower aluminum is expected to be useful as a wiring material instead of polysilicon, which has a high RC time constant as a function of design roll, but has a low melting point, eutectic temperature and annealing. However, due to the high temperature process such as oxidation process, it is not possible to make proper wiring material. Therefore, high melting point metals such as tungsten (W), tantalum (Ta), titanium (Ti) and molybdenum (Mo) have been used. They are used in the pure metal state, or in the high melting point metal silicide state (WSi2, TiSi2, MoSi2, TaSi2), and polylayers, which are multi-layered structures in which low-resistance materials such as high melting point metal silicides are formed on doped polysilicon. Sometimes used in the form of polycide).

However, the high melting point metals have a very high melting temperature, but the oxide film is poor and in some cases volatile. Furthermore, impurities contained in the high melting point metal raw material may obtain a constant threshold voltage in the MOS transistor. The disadvantage is that it can't be. This is because the same problem occurs even when the gate uses a high melting point metal silicide alone as the wiring layer, so that the polyside structure is mainly used. By doing in this way, the conductive layer of low resistance can be implement | achieved, maintaining the favorable interface characteristic etc. with the silicon oxide film which polysilicon has.

On the other hand, as a method of forming silicide, largely accompanied by a subsequent heat treatment step, 1) deposition of pure metal on single crystal or polycrystalline silicon 2) co-evaporation of silicon and high melting point metal from two sources simultaneously Method 3) Sputter deposition from mixed silicide targets or sputtering together from separate targets is mainly used.

On the other hand, as the contact area of the VLSI decreases, the contact resistance increases, and as the surface resistance of the shallow junction of the source / drain regions increases, these resistance values are reduced and at the same time, the wiring resistance of the polysilicon is also reduced. Salicide technology has been used for this purpose.

Hereinafter, the prior art will be described with reference to the accompanying drawings 1 (a)-(d).

As shown in (a), the gate insulating film 12 and the polysilicon 13 are sequentially stacked on the semiconductor substrate 11. As shown in (b), a pattern of a gate electrode is formed by a conventional photolithography technique, ion implantation is performed to form a source and a drain region 14, an insulating film is deposited on the entire surface, and an insulating film is formed by reactive ion etching. The spacer 15 is formed on the sidewall of the gate electrode 13.

Subsequently, as shown in (c), a high melting point metal 16 is deposited on the entire surface of the MOS structure, followed by heat treatment. At this time, as shown in (d), the high melting point metal 16 reacts with the exposed polysilicon 13 of the gate electrode and the exposed silicon of the source and drain regions 14 to form a silicide 17, and the insulating film spacer 15 Will remain unreacted. After the silicide 17 is formed, the high melting point metal remaining on the spacer is selectively etched.

However, according to the related art, since the silicon in the device active region and the silicon in the gate electrode react with the high melting point metal deposited thereon, silicide is formed, so that impurities present in the polysilicon as the gate electrode move or are uneven on the surface. Due to the naturally grown natural oxide film, an uneven silicide film is grown and agglomerated by subsequent heat treatment processes.Since the silicon of the device active region is consumed in the source and drain regions, the remaining junction depth is shown in FIG. 1d. (18) decreases to increase the leakage current, and the subsequent heat treatment causes grain growth of the silicide, and the surface of the silicide becomes rough and agglomerated by the grooving phenomenon, thereby deteriorating the characteristics of the semiconductor device.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device including a silicide film having a uniform thickness in which no agglomeration occurs on the device active region or the gate electrode by solving the problems of the prior art.

A semiconductor device manufacturing method according to the present invention for achieving the above object is a method of manufacturing a semiconductor device in which a silicide film is formed on a silicon layer, the method comprising: forming a buffer film on the silicon; And a third step of forming a conductive layer containing silicon and a high melting point metal in the second step, and a third step of heat-treating the objects subjected to the first and second steps.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

Embodiment 1 will be described with reference to FIGS. 2 (a)-(e).

As shown in (a), the gate insulating film 22, the first conductive film 23, and the first insulating film 24 are sequentially stacked on the entire surface of the silicon substrate 21. The first insulating film 24 is an oxide film or a nitride film.

Subsequently, as shown in (b), the gate pattern is formed by ion photolithography and ion implantation is performed to form the source and drain regions 26. Subsequently, a second insulating film 25 made of a nitride film or an oxide film is formed on the entire surface of the substrate, and then the insulating film spacer 25 is formed by etching the reactive ion etching method.

Subsequently, as shown in (c), only the first insulating film 24 of (b) is selectively removed, and a buffer film 27 is formed on the entire surface of the substrate. In this case, the buffer film 27 is formed of an oxide film or a titanium nitride (TiN) film, or nitrogen molecules or ions are formed by an ion implantation method. Subsequently, the second conductive film 28 is formed on the entire surface of the substrate from pulley silicon or amorphous silicon into which impurities are not injected.

Subsequently, as shown in (d), a second insulating film on the insulating film spacer 25 is coated by a conventional etching method or a flowable insulating film on the entire surface of the substrate and by a flow / etch back method or a conventional planarization method. Only the film 28 is selectively removed, and a high melting point metal 29 is formed on the entire surface of the substrate.

Subsequently, as shown in (e), when heat treatment is performed to perform silicidation, the high melting point metal 29 and the lower second conductive layer 28 and / or the buffer layer 27 react to form a silicide layer ( 30). At this time, when the oxide film is formed in the buffer layer 27 to 70 ~ 80Å, the oxide film is dissolved (dissolved) disappears. In the case of forming the TiN film or the silicon layer with nitrogen ions (molecules) as the buffer film 27, the TiN film (not shown) is formed under the silicide layer 30. Even if a TiN film exists under the silicide layer 30, the TiN film and the silicide layer are used as one conductive film.

Example 2

Example 2 is the same from Example 1 to the formation process of the buffer film 27 of FIG. Therefore, after the buffer layer 27 is formed, polysilicon or amorphous silicon including a high melting point metal is formed on the entire surface of the substrate, and then only the conductive layer on the spacer is selectively removed in the same manner as in Example 1. Heat treatment is performed to form a silicide layer.

Example 3

Example 3 will be described with reference to FIGS. 3A-3E.

As shown in (a), the gate insulating film 32, the first conductive film 33, the first buffer film 34, and the second conductive film 35 are sequentially stacked on the entire surface of the silicon substrate 31. The first buffer film 34 is the same as the first embodiment and is formed in the same manner. The second conductive layer 35 is formed of polysilicon or amorphous silicon to which impurities are not injected.

Subsequently, as shown in (b), the gate pattern is formed by ion photolithography and ion implantation is performed to form the source and drain regions 37. Subsequently, after forming the first insulating film 36 made of a nitride film or an oxide film on the entire surface of the substrate, the insulating film spacer 36 is formed by etching the reactive ion etching method.

Subsequently, as shown in (c), a second buffer film 38 is formed on the entire surface of the substrate. In this case, the second buffer film 38 is formed of an oxide film or a titanium nitride (TiN) film like the first buffer film 34 or a nitrogen molecule or ion is formed by an ion implantation method. Subsequently, the third conductive film 39 is formed on the entire surface of the substrate from pulley silicon or amorphous silicon into which impurities are not injected.

Subsequently, as shown in (d), an insulating film capable of flowing through a conventional etching method or a front surface of the substrate is coated, and the insulating film spacer 36 and the gate electrode are formed by flow / etch back or by a conventional planarization method. Only the third conductive film 39 on the image is selectively removed, and the high melting point metal 40 is formed on the entire surface of the substrate.

Subsequently, as shown in (e), a heat treatment is performed to react with the high melting point metal 40 and the second conductive film 35 and / or the first and second buffer films 34 and 38 to silicide the silicide layer. Get 41. In this case, when the oxide film is formed to be 70 to 80 kV using the first buffer film 34 and the second buffer film 38, the oxide film is dissolved and disappeared. The first buffer film 34 and the second buffer film 38 are formed of a TiN film (not shown) under the silicide layer 41 when the TiN film or the silicon layer is formed of nitrogen ions (molecules). . Even if a TiN film exists under the silicide layer 41, the TiN film and the silicide layer are used as one conductive film.

Example 4

Example 4 forms the first buffer layer 34 in FIG. 3A of Example 3, and then forms polysilicon or amorphous silicon including a high melting point metal as the second conductive layer. Thereafter, the same process as in Example 3 was performed to form the second buffer layer 38 as shown in FIG. 3C, and then polysilicon or amorphous silicon including high melting point metal was formed on the entire surface of the substrate as the third conductive layer. The third conductive film plate on the gate electrode of the insulating film spacer is selectively removed and subjected to heat treatment by a conventional photolithography method or a planarization method to form a silicide layer as shown in FIG. 3E of the third embodiment.

As seen from the above embodiments, the silicide layer formed through the buffer film is very uniform without being partially agglomerated, so that the sheet resistance of the gate poly according to the prior art averages 5.952 / square and its standard deviation is 1.672. According to the present invention, the average of sheet resistance is 3.536 / square and the standard deviation is reduced to 0.160 / square, thereby improving the operation characteristics of the device.

Claims (9)

A semiconductor device manufacturing method in which a silicide film is formed on a silicon layer, the method comprising: forming a buffer film on the silicon layer; and forming a conductive layer containing silicon and a high melting point metal on the buffer film. And a third step of heat-treating the object having passed through the first and second steps. The method of manufacturing a semiconductor device according to claim 1, wherein the buffer film of the first step is formed of any one of an oxide film, a titanium nitride film, or a silicon ion implanted film in a silicon layer. The method of claim 1, wherein the silicon of the second process is any one of polysilicon and amorphous silicon. The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal of the second step is any one selected from the group consisting of W, Ta, Ti, Mo, and the like. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon of the second step is free of impurities. The method of claim 1, wherein the conductive layer of the second process is formed by first depositing silicon and then depositing a high melting point metal. The method of claim 1, wherein the conductive layer of the second step is formed by sputtering (sputtering) a mixture of silicon and a high melting point metal, or by sputtering the silicon and a high melting point metal as a target independently of each other A method for manufacturing a semiconductor device. A first step of forming a gate electrode pattern and forming insulating film spacers on both sidewalls by sequentially stacking a gate insulating film, a first conductive film, and a first insulating film on a silicon substrate; and a second remaining film on the first conductive film. A second process of selectively removing only one insulating film and forming a buffer film on the exposed silicon substrate and the first conductive film, a third process of forming a second conductive film on the buffer film, and a second conductive film on the spacer And a fourth step of selectively removing and forming a high melting point metal on the entire surface of the silicon substrate, and a fifth step of performing silicidation by heat-treating the buffer film and the second conductive film. Way. The first step of stacking a gate insulating film, a first conductive film, a first buffer, and a second conductive film on a silicon substrate in turn, forming a gate electrode pattern, and forming insulating film spacers on both sidewalls; A second process of forming a third conductive film on the buffer film after forming the third conductive film, and a third process of selectively removing the second conductive film and the third conductive film on the spacer and forming a high melting point metal on the entire surface of the substrate. And a fourth step of subjecting the buffer film to the second conductive film and the third conductive film to be silicided.