KR960000542B1 - Frame timing signal detecting method and system using synchronization signal - Google Patents

Abstract

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Description

Frame Timing Signal Extraction Method and System Using Synchronous Signal in Digital Wireless Communication System

1 is a view of the prior art.

FIG. 2 is a concrete circuit diagram of the symbol timing signal acquisition unit 107 of FIG.

3 is a block diagram according to the present invention.

4 is a concrete circuit diagram of FIG.

5 is a correlation characteristic diagram of a synchronization signal of FIG. 4.

The present invention relates to a method for extracting a frame timing signal in a digital wireless communication system, and more particularly, to a method and system for extracting a frame timing signal using a synchronization signal in a wireless communication system having a synchronization signal in a data slot.

In general, when demodulating data from a received signal, a digital wireless communication system first extracts a symbol timing signal of the data (Symbol Timing Recovery), restores the digital data using the signal, and then finds a synchronization signal from the restored data. It is used as a frame timing signal. Conventionally, as shown in FIG. 1, the frequency converter 120 multiplies the modulated signal of the receiver terminal a by an intermediate frequency generated by the symbol waveform generator 104 in the multiplier 101. In addition, the signal of the receiver (a) is shifted by 90 ° in the phase shifter (π / 2) 103 to multiply the modulated signal of the receiver (a) by the multiplier 102 and convert the signal into a baseband signal. And the low frequency filter 130 removes twice the intermediate frequency and unnecessary components included in each output of the multiplier (101, 102). The low pass filter by a symbol timing signal capture unit 107 for extracting symbol time from the outputs of the low pass filters 105 and 106 of the low pass filter unit 130 and a sampling signal output from the symbol timing signal capture unit 107. A sampling unit 140 for sampling the output of the base 130, a data buffer 110 for buffering the sampled data of the sampling unit 140, and a frame from a synchronization signal generated from the data buffer 110. And a frame timing capture section 112 for extracting timing signals, and a reference sync signal storage section 111 for providing a reference sync signal to the frame timing capture section 112.

As shown in FIG. 1, when there is an input signal modulated by the receiving terminal a, the multipliers 101 and 102 multiply the output of the symbol waveform generator 104 and convert the signal into an I and Q signal. That is, the symbol waveform generator 104 is multiplied by the intermediate frequency signal generated by the symbol timing signal acquisition unit 107 and the multipliers 101 and 102 and converted into a baseband I, Q signal. The timing signal capturing unit 107 extracts a symbol timing signal from the outputs of the low pass filters 105 and 106 and supplies it to the data buffer 11 of the sampling unit 140. The sampling unit 140 samples one symbol per symbol according to the extracted symbol timing signal and stores the data in the data buffer 110. The frame timing acquisition unit 112 receives the output of the data buffer 110 and extracts the frame timing signal by comparing with the synchronization data stored in the data reference synchronization signal storage 111. In general, however, a digital wireless communication system transmits data by sampling n (n = 4-8) times per symbol for accurate data recovery. That is, n data are transmitted per symbol. The receiving end receives these data, and in the symbol timing signal capturing unit 107 of FIG. 1, performs sampling on the center of one symbol to restore digital data consisting of ones and zeros. Next, the data is obtained by obtaining a correlation value of the reference synchronization signal, and the position having the maximum value is regarded as the frame synchronization time.

However, the conventional symbol timing signal acquisition unit 107 is composed of a very complicated circuit. One example is shown in FIG. Specifically, the baseband I and Q signals output from the low pass filter 130 of FIG. 1 are input to the respective samplers 202 and 205 so that the clock generated by the voltage controlled clock generator 207 CLK) is applied to squared circuits 206 and 208 after being delayed in delays 203 and 204. The signals applied to the square circuits 206 and 208 are subtracted from the adder 210 and then passed through the loop filter 209 to the voltage control clock generator 207. That is, the clock of the voltage controlled clock generator 207 is applied to the samplers 202 and 025 after a suitable + and-delay time in the delayers 203 and 204, while the clock signal that is not delayed in the delays 203 and 204 is a symbol. Applied to the waveform generator 201 to generate a signal of the symbol timing signal terminal 135 and a signal of the intermediate frequency signal terminal 136, and the symbol timing signal terminal 135 generated by the symbol waveform generator 201. Is applied to the sampling unit 140 and the data buffer 110 of FIG. 1, and the signal of the intermediate frequency signal terminal 136 is transmitted to the frequency converter 120 of FIG.

As described above, the symbol timing signal acquisition unit 107 is not only conceptually complicated but also requires a considerable amount of circuit configuration. In addition, since this circuit is a kind of phase locked loop method, parameter adjustment of each part is difficult, and there is a drawback that the performance is sensitively changed depending on the selection of the parameter.

Accordingly, an object of the present invention is to provide a method and system for efficiently extracting a frame timing signal directly by a synchronization signal in a wireless communication system having a synchronization signal in a time slot.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, and it should be noted that elements having the same functions in the drawings use the same reference numerals.

3 is a block diagram according to an embodiment of the present invention, in which a multiplier (101, 102) multiplies an intermediate frequency generated by the voltage controlled oscillator (304) by the modulated signal input to the receiver (a) to convert an I, Q baseband signal. A converter 120, a low pass filter 130 that removes twice the intermediate frequency and unnecessary components at the output of the frequency converter 120, a sampling clock generator 307 for generating a sampling clock signal, The ADC unit 300 for sampling the baseband analog signal, which is the output of the low pass filter 130, according to a sampling clock generated by the sampling clock generator 307 and converting the analog signal into a digital signal, and the ADC unit ( A data buffer 110 for storing data digitalized at 300, a frame timing capture unit 112 for extracting a frame timing signal by comparing the output signal of the data butter 110 according to a reference synchronization signal, and the frame tie The reference acquisition signal 112 is configured to provide a reference synchronization signal storage unit 111.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIG. 3. When the modulated signal input to the receiver terminal a is input to the multipliers 101 and 102, the voltage controlled oscillator 304 of the frequency converter 120 may be used. It is multiplied by the intermediate frequency signal output from the multiplier (101, 102) and converted into baseband analog I, Q signals (b, b '). Since the signals generated by the multipliers (101, 102) are twice the intermediate frequency signal and the undesired wave, the low band filter (130) consisting of the low band filters (105, 106) removes these signals, and then the pure baseband analog I, It is output as Q signals c and c '. The baseband analog I, Q signals c and c ', which are output signals of the low pass filter 130, are inputted to the ADCs 308 and 309 of the ADC 300 to be generated by the sampling clock generator 307. The asynchronous sampling clock 135 converts the digital data (d, d '), where the converted digital data is applied to the data buffer 110 by the asynchronous sampling clock 135. That is, the data buffer 110 stores the output of the ACD unit 300 according to the output of the sampling clock generator 307. When the output of the data buffer 110 is input to the frame timing capturing unit 112, the frame timing capturing unit 112 receives the data (e, e ') and stores the synchronization data (stored in the reference synchronization signal storage unit 111). f, f '), and extract the (Correlation) frame timing signal. Therefore, a significant difference between the present invention and the prior art is that when the data is transmitted in a general wireless communication system, the receiver may already extract the symbol timing signal at the time of reception by n oversample (typically 4-8 times) per symbol. Since the sampling clock frequency is known, only an error of a maximum 1 / n symbol period occurs, and the error caused by this is insignificant. That is, the conventional technology is to extract the symbol timing signal by hardware by receiving n times oversampled data, and to recover frame timing by recovering one digital data per symbol based on the signal.

However, the present invention is designed to capture (correlation) frame timing by calculating a software correlation value from n times oversampled data without extracting a symbol timing signal. Therefore, a large amount of hardware can be reduced, thereby making it possible to manufacture a simpler wireless communication system. The calculation of the software correlation above is a well known and simple method.

4 is a block diagram illustrating a specific embodiment using the present invention, and input signals through two paths (a and a ') are transmitted to RSSI-1, 2 (401 and 402) of the reception strength measurement unit 400. Referring to FIG. The received intensity is measured, and the measured value is input to the signal processor 450 and subjected to a predetermined process. When a signal having a strong strength is selected by the received signal selection switch 403 (a or a ') according to the processed value of the signal processor 450 and input to the multipliers 101 and 102 of the frequency converter 120. The output of the voltage controlled oscillator 304 is converted into baseband I, Q analog signals (b, b '). The output signals (b, b ') of the multipliers (101, 102) of the frequency converter (120) are doubled the intermediate frequency signal and the unwanted wave by the low pass filters (105, 106) of the low pass filter (130). The amplifiers are then amplified by the amplifiers 408 and 410 and are converted into digital data (d, d ') by the ADCs 308 and 309 of the ADC unit 300 and stored in the data buffer 110. The data (e, e ') stored in the data buffer 110 is generated by the digital reception receiving filter 415, the signal (f, f') from which ISI (Inter Symbol Interference) is removed is generated, and thus the frame timing capture unit. Is applied to 112. The frame timing capturing unit 112 compares the signal f, f '' of the reception filter 415 with the reference synchronization signal g, g 'stored in the reference synchronization signal storage unit 11 (Correlation). The frame timing signal is extracted, and data (i, i ') in the slot is restored based on the signal. The output signal i, i 'of the frame timing acquisition unit 112 outputs the desired final received data j from which the influence of the channel change is removed by the beater equalizer 417.

FIG. 5 is an example showing that a good correlation characteristic is obtained according to the correlation characteristec of the system in the specific embodiment of FIG.

As mentioned above, the symbol timing signal capture portion (FIG. 2) is not only conceptually complicated but also requires a considerable amount of hardware. In addition, since this circuit is a kind of phase locked loop, each part has a difficult parameter adjustment, and the performance is sensitively changed depending on the parameter selection. However, in the present invention, the hardware is removed and n times oversampling is performed. By extracting the frame timing signal by a method of directly calculating the correlation value of the synchronization signal in the frame using the acquired data, the circuit of the wireless communication system can be simplified with the synchronization signal in the slot.

Claims (3)

In the frame timing signal extraction system using the synchronization signal in the digital wireless communication system, the multiplier (101, 102) to the intermediate frequency generated from the voltage controlled oscillator (304) to the modulation signal input to the receiving end (a) of the digital wireless communication system The frequency converter 120 is multiplied by and converted to an I, Q baseband signal, and the output of the frequency converter 120 is twice the intermediate frequency and the unwanted components. The sampling clock generator 307 which generates a clock signal for sampling the signal output through the filter 130, and the output analog I, Q baseband signals of the low frequency filter 130 are converted into ADCs 308, 309. ) Is inputted to the ADC 300 for sampling in accordance with the sampling clock generated by the sampling clock generator 307 to convert to digital data, and the digitalization by sampling in the ADC 300 The frame timing signal is extracted by comparing the data buffer 110 for storing data by the clock generated by the sampling clock generator 307 and the signal of the data buffer 110 with a reference signal for extracting the frame timing signal. Frame timing capture unit 112 and a reference synchronization signal storage unit 111 for providing a reference synchronization signal to the frame timing capture unit 112. Frame timing using a synchronization signal in a digital wireless communication system, characterized in that the Signal extraction system. A frame timing signal extraction system using a synchronization signal in a digital wireless communication system, comprising: a reception strength measuring unit (400) for measuring reception intensity from an input signal of a receiving end (a, a ') of the digital wireless communication system, and the receiving end The reception signal selection switch 403 for selecting an input of (a, a ') and the measurement output of the reception strength measurement unit 400 are processed to select a signal having a strong reception strength by the reception signal selection switch 403. Multipliers (101, 102) multiply the intermediate frequency generated by the voltage controlled oscillator (304) by the signal processing unit (450) for controlling and the modulation signal input to the receiving terminal (a) to convert to I, Q baseband signals. A converter 120, a low-pass filter 130 that removes the intermediate frequency and the unwanted components twice the output of the frequency converter 120, and a sampling clock generator 307 for generating a sampling clock signal Wow, An ADC unit 300 for sampling the output baseband analog signal of the base low pass filter unit 130 according to a sampling clock generated by the sampling clock generator 307 and converting the analog signal into digital data; and the ADC unit 300 The frame timing signal is compared with the data buffer 110 for storing the digitalized data at the sampling clock generator 307 according to a clock, and the output signal of the data butter 110 is compared with a reference signal for frame timing extraction. A frame timing capture unit 112 for extracting the?, A reference synchronization signal storage unit 111 for providing a reference synchronization signal to the frame timing capture unit 112, an output of the frame timing capture unit 112, and the reference; Synchronization signal in the digital wireless communication system, characterized in that Viterbi equalizer 417 to remove the adverse effect of the channel change by the reference synchronization signal of the synchronization signal storage 111 Frame timing signal extraction system using. A frame timing signal extraction system using a synchronization signal in a digital wireless communication system, comprising: a received signal strength measurement for measuring the strength of a signal received by the digital wireless communication system and a received signal according to a measured value of the received signal strength measurement process A frequency conversion process of converting a modulated signal input to the digital wireless communication system into a baseband signal of I and Q according to the selection of the selection process, and a frequency conversion output of twice the intermediate frequency. And an A / D conversion process for converting an unnecessary wave component, a baseband analog signal of I and Q removed in the unnecessary wave removal process, to digital data, and a conversion in the A / D conversion process. A timing signal extraction process for extracting the frame timing signal by comparing the digital data with the reference synchronization signal; A frame timing signal extraction method using a synchronization signal in a digital wireless communication system, characterized in that the Viterbi equalization process to remove the adverse effect of the channel change from the extraction value of the frame timing signal extraction process and the reference synchronization signal.