KR960008878Y1 - Relay tester - Google Patents

Abstract

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Description

Relay testing machine

1 is a configuration diagram showing the principle of a general electronic relay.

2 is a circuit diagram of a relay tester of the present invention.

3 (a) to (g) is an operation waveform diagram of the relay tester of the present invention.

* Explanation of symbols for main parts of the drawings

1: clock generator 2: timer IC

3: counter 4: relay

R ₁ : resistor C ₁ : condenser

Q ₁ : Transistor B: Buffer

LED: Light Emitting Diode

The present invention relates to a relay tester that can check the malfunction of the relay intermittently occurring during the continuous operation of the relay.

In general, a relay refers to a device that opens or closes an electric circuit according to various pressure signals such as temperature and light, as well as electrical signals such as voltage, current, power, and frequency.

Relays can be broadly classified into contact relays such as electronic relays and contactless relays such as semiconductor relays such as transistor relays and SCR relays.

1 is an electronic relay configuration diagram showing the principle of a general electronic relay.

Contacts a and b are selectively opened or closed by pushing or pulling the pole piece according to the signal applied to the relay coil.

The time that an open contact is closed or the closed contact is opened is determined by the gap between the relay's movable contact and the pole piece.

At present, the relay has a wide range of use and demands high reliability, high sensitivity, and long service life depending on the application.

During the continuous operation of the relay, a malfunction occurs intermittently.

The object of the present invention is to provide a relay tester capable of inspecting malfunctions that may occur during continuous operation of a relay used in various fields such as a control system or a semiconductor manufacturing device and an electronic and electrical product test device.

Hereinafter, described in detail with respect to the relay tester of the present invention with reference to the accompanying drawings.

2 is a circuit configuration diagram of the relay tester of the present invention, and FIG. 3 (a) to (g) is an operation waveform diagram of the relay tester of the present invention.

The relay tester of the present invention outputs an abnormal operation signal of the relay 4 by inputting the clock generator 1 generating the reference clock and the reference clock of the clock generator 1 output through the relay 4 as an input. A timer IC 2, such as a GLC 555, and a counter 3 are interconnected and configured to test the relay 4.

When explaining the operation, when applied to the relay (4) for testing the power supply (V) connected to a clock generator (I) is at a high signal of the clock transistor (Q ₁₎ when to operate the transistor (Q ₁₎ that is turned on, At this time, a current flows through the coil L inside the relay 4, and the switch SW inside the relay 4 is turned on.

Further, when applied to the clock generator (1) is at a low signal transistor (Q ₁₎ of the transistor (Q ₁₎ is turned off, the relay 4 switch on the inside (SW) is turned off.

FIG. 3 (a) shows the output waveform of the clock generator 1, and FIG. 3 (b) shows the output signal waveform of the relay 4.

When the output waveform of the relay 4, that is, the input of the timer IC 2 as shown in FIG. 3 (b), that is, increases the period of the waveform by adjusting R ₁ C ₁ , the input of the timer IC 2 becomes the third waveform. As in FIG. C, the output of the timer IC 2 remains high as in FIG.

3 (e) (f) (g) show an operation failure state in which the relay 4 does not operate.

The output pulse width is controlled by the resistor R ₁ and the capacitor C ₁ , and the timer IC 2 such as the GLC 555, which is composed of a monostable multivibrator, receives the output signal of the relay 4 and receives the output signal of the relay 4. At the falling time of the waveform of the capacitor (C ₁ ) begins to charge the voltage (V), and after the instantaneous discharge at the time of the next start of charging again.

Here, FIG. 3 (e) shows the operation failure state of the relay 4. In the operation failure state of the relay 4 in the part of FIG. 4, it is determined according to the capacitance of the resistor R ₁ and the capacitor C ₁ . After maintaining the high signal for the pulse width T, it falls to the low signal, and then rises again to the high signal at the time when the output waveform of the relay 4 falls.

If the operation of the relay 4 is normal, the waveform of FIG. 3 g keeps the high signal.

When the relay 4 is intermittently defective, the waveform of FIG. 3 (g) becomes a low signal, the light emitting diode LED emits light, and the counter 3 measures the number of occurrences of the defective operation of the relay 4. .

As described above, the relay tester according to the present invention can detect a malfunction occurring in the continuous operation of the relay before applying the relay to the system, thereby increasing the reliability of the relay.

Claims (1)

The clock generator 1 generating a reference clock signal and outputting the signal according to the operation of the relay 4 and the reference clock signal output through the relay 4 are charged according to the capacitance of the capacitor C ₁ . When the discharge is repeatedly outputted with a high level pulse and a reference clock signal according to the abnormal operation of the relay 4 is input, the pulse width T determined by the resistor R ₁ and the capacitor C ₁ is obtained. A relay abnormal operation detecting means comprising a timer IC 2 which outputs a low level pulse during the abnormal operation time period thereafter, and a counter means for counting the frequency of occurrence of abnormal signal output from the relay abnormal operation detecting means. Relay tester, characterized in that made.