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KR960006696B1 - Metal plug forming method - Google Patents

Metal plug forming method Download PDF

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Publication number
KR960006696B1
KR960006696B1 KR1019920027074A KR920027074A KR960006696B1 KR 960006696 B1 KR960006696 B1 KR 960006696B1 KR 1019920027074 A KR1019920027074 A KR 1019920027074A KR 920027074 A KR920027074 A KR 920027074A KR 960006696 B1 KR960006696 B1 KR 960006696B1
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South Korea
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tungsten
contact
depositing
region
contact portion
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KR1019920027074A
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Korean (ko)
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KR940016502A (en
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최경근
박홍락
고철기
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현대전자산업주식회사
김주용
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The method is to deposit the tungsten after the contact area is divided into N+ contact area(4) and P+ contact area(5) because the tungsten deposition rate differs from that of the substrate. The method comprises the steps : (a) opening the N+ contact area(4), (b) depositing of 500A tungsten(7) at 230-250deg.C, (c) opening the P+ contact area(5) and polysilicon contact area(6), (d) depositing tungsten(9) at 300deg.C, and (e) depositing aluminium(10).

Description

반도체 소자의 2단계 선택 금속 플러그 형성방법Method of forming a two-stage selection metal plug for semiconductor devices

제1도는 실리콘 기판상의 N+콘택부상 절연막의 소정부분을 오픈시킨후, 텅스텐을 증착하는 단계를 나타내는 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device showing a step of depositing tungsten after opening a predetermined portion of an N + contact-side insulating film on a silicon substrate.

제2도는 전체구조 상부에 감광막을 형성한후 P+콘택부 및 폴리실리콘상의 소정부분을 오픈시키는 단계를 나타내는 반도체 소자의 단면도.2 is a cross-sectional view of a semiconductor device showing a step of opening a predetermined portion on a P + contact portion and a polysilicon after forming a photoresist film over the entire structure.

제3도는 P+콘택부 및 폴리실리콘상의 콘택부에 텅스텐을 중착한 후 알루미늄 합금을 증착하는 단계를 나타내는 반도체 소자의 단면도.3 is a cross-sectional view of a semiconductor device showing a step of depositing aluminum alloy after depositing tungsten on a P + contact and a polysilicon contact;

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판, 2 : 소자분리 산화막,1: silicon substrate, 2: device isolation oxide film,

3 : 산화막, 4 : N+콘택부,3: oxide film, 4: N + contact portion,

5 : P+콘택부, 6 : 폴리실리콘,5: P + contact portion, 6: polysilicon,

7 : 선택 텅스텐, 8 : 감광막,7: tungsten optional, 8: photosensitive film,

9 : 선택 텅스텐, 10 : 알루미늄 합급.9: tungsten optional, 10: aluminum alloy.

본 발명은 반도체 소자의 2단계 선택금속 플러그 공정에 관한 것으로, 특히, 텅스텐금속이 실리콘 기판으로 침투하는 반응과, 텅스텐의 성장두께 차이를 일정하게 유지하기 위해, 콘택부를 N+콘택부와 P+콘택부로 구분한 후, 텅스텐을 증착하는 반도체 소자의 2단계 선택금속 플러그 공정에 관한 것이다. 일반적으로, 반도체소자 제조공정에서 선택 텅스텐은 저압화학 기상 증착 반응기를 이용하여 증착하였다. 이때 반응기체는 SiH4와 WF6을 사용하여 수송기체는 H2를 사용한다. 이때, 텅스텐 증착은 실리콘(Si)에 의한 WF6반응에서 텅스텐이 실리콘으로 침투(encroachment)하는 반응이다. 이 반응은 N+, P+콘택의 종류에 따라다르며, 특히 이러한 반응은 N+부위가 P+부위보다 훨씬 많이 일어난다. 이러한 원인은 근본적으로 N+, P+의 콘택에서 도판트의 전기음성도 차이 때문에 발생된다. 텅스텐은 증착시 반응 초기에는 WF6의 Si 환원 반응을 통해 시드층이 형성되며 시드층 형성속도는 Si 표면 상태에 따라 영향을 받는다. 즉, 어셉터보다는 도우너 타입의 도판트가 존재할 수록 시드층 형성이 초기에 진행된다. 그리하여 텅스텐 최종 성장두께도 차이가 난다. 일반적으로 실리콘 환원 반응은 온도의 함수이고, 증착온도 300℃에서 N+부위는 350Å, P+부위는 1000Å 정도의 침투(encroachment)가 일어나 약 250Å 정도 차이가난다. 이 현상은 자연산화막이 존재할 때 더욱 심하게 나타난다. 이 때문에 N+/P+접합에서 더욱 많은 접합누설 전류에 의한 실패를 유발하며, N+, P+부위에서 최종 두께 차이로 인한 실패는 다음과 같다. 즉 300℃에서 5000Å 두께 타깃으로 텅스텐을 증착할 때, N+콘택에서는 5000Å 정도로 정상적으로 성장하지만 P+콘택에서는 1000 내지 2000Å 정도로만 성장하지 않는 경우도 있다. 이 때문에 추후 공정인 알루미늄 스퍼터링 공정과 복합되어 전기적 특성악화를 유발시키는 문제점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-stage selective metal plug process of semiconductor devices, and in particular, in order to keep the tungsten metal penetrating into the silicon substrate and the difference in tungsten growth thickness constant, the contact portion may be N + contact portion and P +. After divided into contact portions, the present invention relates to a two-stage selective metal plug process for depositing tungsten. In general, tungsten selected in the semiconductor device manufacturing process was deposited using a low pressure chemical vapor deposition reactor. At this time, the reactor gas is SiH 4 and WF 6 and the transport gas is H 2 . In this case, tungsten deposition is a reaction in which tungsten penetrates into silicon in the WF 6 reaction by silicon (Si). This reaction is N +, depends on the type of the P + contact, particularly this reaction takes place much more than the N + region P + region. This is fundamentally due to the difference in the electronegativity of the dopant in the contacts of N + and P + . During the deposition of tungsten, the seed layer is initially formed through the Si reduction reaction of WF 6 and the seed layer formation rate is affected by the Si surface state. That is, as the donor type dopant is present rather than the acceptor, seed layer formation is initially performed. Thus, the final growth thickness of tungsten also differs. In general, the silicon reduction reaction is a function of temperature, and at 300 ° C., the N + region is 350 kV and the P + region is 1000 kV, so the encroachment is about 250 kPa. This phenomenon is more severe when natural oxides are present. Because of this, the failure caused by more junction leakage current in N + / P + junction, the failure due to the final thickness difference in the N + , P + region is as follows. In other words, when tungsten is deposited to a target of 5000 mW at 300 ° C., it grows normally at about 5000 mW in the N + contact, but may not grow at only about 1000 to 2000 mW in the P + contact. For this reason, there is a problem of causing electrical property deterioration in combination with a later aluminum sputtering process.

본 발명은 상술한 문제점을 해결하기 위해, 기판의 콘택 종류에 따라 달라지는 텅스텐 실리콘 침투 반응과 텅스텐의 성장두께 차이를 일정하게 유지하기 위해 콘택 부위를 N+부위와 P+콘택부위를 형성하여 250℃ 이하의 저온에서 텅스텐을 증착하며 100Å 이하의 실리콘 소모반응을 유지하였다. 즉, N+부위에 텅스텐을 증착한 후 P+콘택부위와 폴리실리콘 부위의 콘택을 형성한 후, 300℃ 정도의 온도에서 텅스텐을 증착하여 이미 증착된 N+부위에는 텅스텐 증착되지 않게 하고 P+부위와 폴리실리콘 콘택부위에만 텅스텐이 성장하게 하였다.그리하여 텅스텐이 실리콘으로 침투하는 현상과 N+, P+콘택부위가 동시에 노출될때 텅스텐 증착으로 발생되는 N+, P+콘택부위에서의 두께 차이를 극복하는 것을 목적으로 한다.In order to solve the above-mentioned problems, the contact region is formed at 250 ° C. to form a N + region and a P + contact region in order to maintain a constant tungsten silicon penetration reaction and a growth thickness difference of tungsten depending on the contact type of the substrate. Tungsten was deposited at the following low temperature and maintained silicon consumption of less than 100 Pa. That is, after deposition of tungsten on the N + region after forming the contact of the P + contact region and the polysilicon region, by the deposition of tungsten at a temperature of about 300 ℃ N + region that has already been deposited is no longer deposited tungsten, and P + Tungsten grows only on the site and the polysilicon contact area, so that tungsten penetrates into the silicon and the thickness difference between the N + and P + contact areas caused by tungsten deposition when the N + and P + contacts are exposed simultaneously. It aims to overcome.

이하, 첨부된 도면으로 본 발명을 더욱 상세하게 설명하기로 한다. 제1도는 종래의 방법으로 실리콘 기판(1)에 N-웰 영역 및 P-웰 영역과, 소자분리산화막(2) 및 트랜지스터를 형성하고, 그 상부에 산화막(3)을 형성한 후, N+콘택부(4) 상부의 산화막(3)의 소정부분을 식각하여 N+콘택을 개방한 후, 텅스텐을 500Å 정도 증착한 상태를 나타내는 반도체소자의 단면도이다. 이때, 텅스텐은 LPCVD 반응기를 이용하여 230 내지 250℃ 정도의 저온에서 WF6와 SiH4기체를 사용하여 증착한다.Hereinafter, the present invention will be described in detail with the accompanying drawings. 1 shows an N-well region and a P-well region, a device isolation oxide film 2 and a transistor in a silicon substrate 1 by a conventional method, and an oxide film 3 formed thereon, followed by N +. A sectional view of a semiconductor device showing a state in which a predetermined portion of the oxide film 3 on the contact portion 4 is etched to open N + contacts, and then tungsten is deposited about 500 kV. In this case, tungsten is deposited using WF 6 and SiH 4 gas at a low temperature of about 230 to 250 ° C. using an LPCVD reactor.

제2도는 제1도의 공정후, 전체구조 상부에 감광막(8)을 증착한후, 금속 콘택마스크 공정으로 P+콘택부(5) 상부 및 폴리실리콘(6) 상부를 식각하여, 콘택을 형성하는 상태를 나타내는 반도체 소자의 단면도이다.FIG. 2 shows that after the process of FIG. 1, the photoresist film 8 is deposited on the entire structure, the P + contact portion 5 and the polysilicon 6 are etched by a metal contact mask process to form a contact. It is sectional drawing of the semiconductor element which shows a state.

제3도는 제2도의 공정후, P+콘택부(5) 및 폴리실리콘부(6) 상부에 텅스텐을 소정의 두께로 증착한후, 전체구조 상부에 알루미늄 합금(10)을 증착하는 단계를 나타내는 반도체소자의 단면도이다. 이때, 이미 제1도에 도시한 바와 같이, 증착된 N+콘택부(4) 상에는 텅스텐이 성장되지 않으며, N+콘택부(4)에서의 실리콘 기판(1)으로의 텅스텐과의 침투 문제가 해결되며, 소자의 신뢰성도 향상된다. 이상에서 살펴본바와같이, 반도체 소자의 액티브 부위를 N+부위와 P+콘택부위로 나누어 증착함으로써 CVD 방법에 의해 선택 금속 증착시 실리콘 기판 부위로 선택 금속이 침투하는 현상을 억제할 수 있다. 따라서, P+/N 부위에 비해 취약한 N+/P 접합의 접합누설 전류의 실패를 줄이므로써 금속 플럭 공정의 신뢰성을 증가시키며, N+, P+콘택에서의 최종 텅스텐 성장 두께의 차이도 조절할 수 있다. 그리하여 추후 공정인 알루미늄 스퍼터링 공정의 신뢰성을 증가시킨다.FIG. 3 shows the step of depositing tungsten on the P + contact portion 5 and the polysilicon portion 6 to a predetermined thickness after the process of FIG. 2, and then depositing the aluminum alloy 10 on the entire structure. A cross section of a semiconductor device. At this time, as shown in FIG. 1, tungsten is not grown on the deposited N + contact portion 4, and a problem of penetration of tungsten from the N + contact portion 4 into the silicon substrate 1 is caused. The reliability of the device is also improved. As described above, by dividing the active region of the semiconductor device into an N + region and a P + contact region, it is possible to suppress the phenomenon that the selective metal penetrates into the silicon substrate region during the selective metal deposition by the CVD method. Therefore, the reliability of the metal floc process is increased by reducing the failure of junction leakage current of weak N + / P junctions compared to the P + / N region, and the difference in final tungsten growth thickness in N + and P + contacts is also controlled. Can be. This increases the reliability of the later aluminum sputtering process.

Claims (3)

실리콘기판에 N-웰 영역 및 P-웰 영역을 형성하고, 소자 분리 산화막과 트랜지스터를 형성하는 반도체 소자의 2단계 선택금속 플러그 공정에 있어서, N+콘택부(4) 상부의 산화막(3)의 소정부분을 식각하여 콘택을 형성한 후, 텅스텐(7)을 증착하는 단계와, 전체구조 상부에 감광막(8)을 증착한 후, P+콘택부(5) 및 폴리실리콘(6) 상부의 산화막(3)의 소정부분만을 식각하고, 텅스텐(9)을 증착한 후 알루미늄 합금(10)을 증착하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 2단계 선택금속 플러그 형성방법.In a two-step selective metal plug process of a semiconductor device in which an N-well region and a P-well region are formed on a silicon substrate, and an element isolation oxide film and a transistor are formed, the oxide film 3 on the N + contact portion 4 is formed. After etching a predetermined portion to form a contact, depositing tungsten (7), depositing a photoresist film (8) on the entire structure, and then an oxide film on the P + contact portion 5 and the polysilicon 6 (3) etching only a predetermined portion, and depositing tungsten (9) and then depositing an aluminum alloy (10). 제1항에 있어서, 상기 N+콘택부(4)는 230 내지 250℃ 정도의 낮은 온도로 증착하는 것을 특징으로 하는 반도체소자의 2단계 선택금속 플러그 형성방법.The method of claim 1, wherein the N + contact portion (4) is deposited at a low temperature of about 230 to 250 ℃. 제1항에 있어서, 상기 P+콘택부(5)는 300℃ 이상의 고온으로 증착하는 것을 특징으로 하는 반도체소자의 2단계 선택금속 플러그 형성방법.The method of claim 1, wherein the P + contact portion is deposited at a high temperature of 300 ° C. or higher.
KR1019920027074A 1992-12-31 1992-12-31 Metal plug forming method KR960006696B1 (en)

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