KR960004716B1 - Matching control device between the Asynchronous Transfer Mode (ATM) adaptation layer and the Asynchronous Transfer mode (ATM) layer - Google Patents
Matching control device between the Asynchronous Transfer Mode (ATM) adaptation layer and the Asynchronous Transfer mode (ATM) layer Download PDFInfo
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- KR960004716B1 KR960004716B1 KR1019930027885A KR930027885A KR960004716B1 KR 960004716 B1 KR960004716 B1 KR 960004716B1 KR 1019930027885 A KR1019930027885 A KR 1019930027885A KR 930027885 A KR930027885 A KR 930027885A KR 960004716 B1 KR960004716 B1 KR 960004716B1
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- 230000005540 biological transmission Effects 0.000 claims description 65
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- 238000010586 diagram Methods 0.000 description 6
- 230000006727 cell loss Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5649—Cell delay or jitter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/566—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM layer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
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Abstract
내용 없음.No content.
Description
제1도는 ATM 적응 계층과 ATM 계층간의 정합제어장치의 개략적인 블럭구성도.1 is a schematic block diagram of a match control device between an ATM adaptation layer and an ATM layer.
제2도는 송신동작에 따른 처리 흐름도.2 is a processing flowchart according to a transmission operation.
제3도는 수신동작에 따른 처리 흐름도.3 is a processing flowchart according to a receiving operation.
제4도는 송수신 동작에 따른 신호의 타아밍도.4 is a timing diagram of a signal according to a transmission / reception operation.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : ATM 생성블럭 12 : Tx 송신 버퍼11: ATM generation block 12: Tx transmit buffer
13 : 송신 제어 블럭 14 : Tx 수신 버퍼13: transmit control block 14: Tx receive buffer
15 : 수신 제어 블럭 16 : Rx 수신 버퍼15: Receive control block 16: Rx receive buffer
17 : Rx 수신 제어 블럭 18 : Rx 송신 제어 블럭17: Rx receive control block 18: Rx transmit control block
19 : Rx 송신 버퍼 20 : ATM 셀 처리 블럭19: Rx transmit buffer 20: ATM cell processing block
본 발명은 국제 표준 기구인 TSS(Telecommunication Standand Sector; 이하 TSS하 함)에서 광대역 종합정보통신망(이하 B-ISDN라 함)의 전송 방식인 ATM을 이용한 방식에 있어서 비동기 전송 모드(ATM) 적층 계층(ATM Adaptation Layer; 이하 AAL이라 함)과 비동기 전송 모드(ATM) 게층간의 송수신 셀 전송에 따른 정합제어장치에 관한 것이다.The present invention relates to an asynchronous transmission mode (ATM) layered layer (ATM) in a method using ATM, which is a transmission method of a broadband integrated information communication network (hereinafter referred to as B-ISDN) in an international standard organization (TSS). A matching control device according to transmission and reception cell transmission between an ATM Adaptation Layer (hereinafter referred to as AAL) and an Asynchronous Transfer Mode (ATM) layer.
B-ISDN에서 타입에 따른 서비스를 제공하기 위해서는 53 옥텟의 ATM 셀이 사용된다. 이러한 ATM 셀은 48 옥텟의 ATM적응 게층-프로토콜 데이타 유닛(Protocol Data Unit; 이하 PDU라 함)로 1차 변환된 후, 5 옥텟의 ATM 헤더와 결합하여 53 옥텟의 ATM 셀을 형성한 후, 물리 계층의 처리를 통하여 B-ISDN으로 전송된다.In order to provide type-specific services in B-ISDN, 53 octets of ATM cells are used. The ATM cell is first transformed into a 48 octet ATM adaptation layer-protocol data unit (hereinafter referred to as a PDU), and then combined with a 5-octet ATM header to form a 53 octet ATM cell. Through the processing of the layer is transmitted to the B-ISDN.
기존의 동기망에서의 데이타 전송시 사용되는 일정 간격의 타임슬롯의 할당에 의하여 전송되는 방식과는 달리 ATM망에서는 생성이 고정적으로 또는 가변적으로 생성되기에 기존의 방식에 의한 정합과는 달리 셀단위로 생성될 때마다 비동기적으로 계층간에 송수신을 해야 하며, 일예로 고정비트율의 서비스 전송에 대한 AAL 송수신장치에 대한 구성은 본 출원인이 기 출원한 특허출원(출원번호; 92-24193, 24194)에 명시되었다.Unlike the method of transmission by allocation of time slots at regular intervals used for data transmission in a conventional synchronous network, generation is fixedly or variably in an ATM network. Whenever it is generated by asynchronous transmission and reception between the layers, for example, the configuration of the AAL transceiver for a fixed bit rate service transmission is described in the patent application (application number; 92-24193, 24194) Specified.
본 발명의 목적은 모든 형태의 AAL과 ATM 계층간의 송수신을 지원하며, 특히 고정 비트율과 같은 서비스에 대하여 발생될 수 있는 셀 지연변동에 민감한 서비스에 대하여는 버퍼에서의 대기없이 1 셀 단위로 곧 바로 전송을 하므로 지연에 대한 감소와 상대 계층의 수신 상태를 통보받아 송수신하므로 버퍼의 오버플로우로 인한 전송에 다른 셀 손실을 방지할 수 있게 되므로 AAL과 ATM 계층간의 안정된 셀 전송을 할 수 있도록 한 AAL과 ATM 계층간의 정합제어장치를 제공하는데 있다.An object of the present invention is to support the transmission and reception between all types of AAL and ATM layers, and in particular, for a service that is sensitive to cell delay fluctuations that may occur for a service such as a fixed bit rate, it is directly transmitted in one cell unit without waiting in a buffer. AAL and ATM are designed to enable stable cell transmission between AAL and ATM layer, because it reduces and delays and receives and receives the reception status of the other layer, thus preventing other cell loss due to buffer overflow. It is to provide a matching control device between layers.
상기 본 발명의 목적을 달성하기 위하여 본 발명은, ATM 셀 생성 수단으로부터의 ATM 셀을 셀 클럭에 따라 저장하는 ALL측 송신버퍼와, 상기 ATM 셀 생성 수단에서 출력되는 셀 클럭과 프레임 신호를 입력받으며, ATM 계층으로부터 송신 받으면 전송 클럭을 상기 ALL측 송신 버퍼로 전송하여 ATM 셀을 전송하도록 하는 동시에 프레임 신호, 클럭, 동기 신호를 ATM측으로 출력하는 ALL측 송신 제어 수단과, 상기 ALL측 송신 버퍼로부터 ATM 셀을 전송받고, ALL측 송신 제어 블럭으로부터 프레임 신호와 클럭을 입력받는 ATM 계층측 수신 버퍼와, 상기 ATM 계층측 수신 버퍼로부터 저장 상태 신호를 입력받아 상기 ALL측 송신 제어 수단으로 송신 요청 신호를 제공하며, 상기 ALL측 송신 제어 수단으로부터 프레임 신호와 전송 클럭을 입력받는 ALL측 수신 제어 수단과, ALL측으로 전송할 ATM 셀을 저장하고 있는 ALL측 송신 버퍼와, ALL로부터 송신 요청 신호를 입력받으면 전송 클릭을 상기 ALL측 송신 버퍼로 전송하여 ATM 셀을 전송하도록 하는 동시에 프레임 신호와 클럭 신호와 동기 신호를 상기 ALL측으로 전송하는 ATM측 송신 제어 수단과, 수신 가능 여부를 알리는 전송 요청 신호를 상기 ATM측 수신 제어 수단으로 제공하고 프레임 신호, 클럭, 동기 신호를 입력받고 수신된 ATM 셀을 출력할 것을 명령하는 제어 신호를 출력하는 ALL측 수신 제어 수단과, 상기 ATM 계층측으로부터의 ATM 셀을 입력받으며, 상기 ALL측 수신 제어 수단으로부터 출력 제어 신호를 입력받으면 저장하였던 ATM 셀을 출력하는 ALL측 수신 버퍼를 구비한다.In order to achieve the object of the present invention, the present invention, the ALL-side transmission buffer for storing the ATM cell from the ATM cell generating means according to the cell clock, and receives the cell clock and the frame signal output from the ATM cell generating means And all transmission control means for transmitting a transmission clock to the ALL transmission buffer to transmit an ATM cell when receiving the transmission from the ATM layer, and outputting a frame signal, a clock, and a synchronization signal to the ATM, and an ATM from the ALL transmission buffer. An ATM layer receiving buffer receiving a cell, receiving a frame signal and a clock from an ALL transmission control block, and receiving a storage status signal from the ATM layer receiving buffer, and providing a transmission request signal to the ALL transmission control means. An ALL side reception control means for receiving a frame signal and a transmission clock from the ALL side transmission control means and an ALL side; The ALL-side transmit buffer that stores the ATM cell to be transmitted, and when a transmit request signal is received from ALL, the transmission click is transmitted to the ALL-side transmit buffer to transmit the ATM cell, and the frame signal, the clock signal, and the synchronization signal are transmitted. An ATM side transmission control means for transmitting to the ATM side, and a control signal for providing a transmission request signal indicating whether or not reception is possible to the ATM side reception control means, receiving a frame signal, a clock, and a synchronization signal, and outputting a received ATM cell. And an ALL side reception buffer for receiving an ATM cell from the ATM hierarchical side and an output control signal from the ALL side reception control means.
이하, 첨부된 도면을 참조하여 본 발명이 일실시예를 상세힐 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제1도는 본 발명의 개략적인 블럭 구성도로서, 11은 ATM 생성 블럭, 12는 Tx 송신 버퍼, 13은 Tx 송신 제어 블럭, 14는 Tx 수신 버퍼, 15는 Tx 수신 제어 블럭, 16은 Rx 수신 버퍼, 17은 Rx 수신 제어 블럭, 18은 Rx 송신 제어 블럭, 19는 Rx 송신 버퍼, 20은 ATM 셀 처리 블럭을 각각 나타낸다.1 is a schematic block diagram of the present invention, in which 11 is an ATM generation block, 12 is a Tx transmit buffer, 13 is a Tx transmit control block, 14 is a Tx receive buffer, 15 is a Tx receive control block, and 16 is an Rx receive buffer. 17 denotes an Rx receive control block, 18 denotes an Rx transmit control block, 19 denotes an Rx transmit buffer, and 20 denotes an ATM cell processing block.
도면에서와 같이 ALL과 ATM 계층간의 정합 제어 장치의 구성은, 본 출원인이 기 출원한 발명(출원번호; 92-24194)에 명시된 ATM 셀 생성 블럭(11)으로부터 공급되는 ATM 셀이 셀 클럭(Cell-Clk)에 따라 Tx 송신 버퍼(12)에 저장되는 동시에 상기 셀 클럭(Cell_Clk)은 Tx 송신 제어 블럭(13)에 공급되어, 53 옷텟의 ATM 셀이 저장되었는지를 판단한다.As shown in the figure, the configuration of the matching control device between the ALL and the ATM layer is such that the ATM cell supplied from the ATM cell generation block 11 specified in the present invention (Application No. 92-24194) filed by the present applicant is a cell clock (Cell). The cell clock Cell_Clk is supplied to the Tx transmission control block 13 at the same time as stored in the Tx transmission buffer 12 according to -Clk, and it is determined whether 53 ATMet of ATM cells are stored.
한편, Tx 수신 버퍼(14)는 버퍼 저장 상태를 Tx 수신 제어 블럭(15)에 제공되고, Tx 수신 제어 블럭(15)은 수신 가능 여부를 알리는 요청 신호(TCell-Req)를 Tx 송신 제어 블럭(13)에 공급하여, Tx 송신 제어 블럭(13)이 이를 판단하여 송신한다. 송신시는 Tx 송신 버퍼(12)로부터 송신 데이타(TCell-Dat)와 Tx 송신 제어 블럭(13)으로부터 동기 신호(TCell-Sync), 프레임 신호(TCell-Frm), 전송 클럭(TCell-Clk)의 각 신호에 다라 Tx 송신 버퍼(14)와 Tx 수신 제어 블럭(15)으로 전송된다.Meanwhile, the Tx reception buffer 14 provides the buffer storage state to the Tx reception control block 15, and the Tx reception control block 15 transmits a request signal TCell-Req indicating whether or not reception is possible. 13), the Tx transmission control block 13 determines this and transmits it. At the time of transmission, transmission data (TCell-Dat) from the Tx transmission buffer 12 and synchronization signal (TCell-Sync), frame signal (TCell-Frm) and transmission clock (TCell-Clk) from the Tx transmission control block 13 The signals are transmitted to the Tx transmit buffer 14 and the Tx receive control block 15 according to each signal.
ATM 계층에서 ALL로의 전송시는 Rx 수신 버퍼(16)는 버퍼 상태를 Rx 수신 제어 블럭(17)에 통보하고 Rx 수신 제어 블럭(17)는 수신 가능 여부를 알리는 전송요청(RCell-Req) 신호를 Rx 송신 제어 블럭에 제공하는데, Rx 송신 제어 블럭(18)은 이에 따라 동기 신호(RCell-Sync), 프레임 신호(RCell-Frm), 클럭신호(RCell-Clk)의 각 신호를 송신하는 동시에 Rx 송신 버퍼(19)로부터 데이타 셀(RCell-Dat)인 ATM 셀을 Rx 수신 버퍼(16)와 Rx 수신 제어 블럭(17)에 공급한다.When transmitting from the ATM layer to ALL, the Rx reception buffer 16 notifies the Rx reception control block 17 of the buffer status and the Rx reception control block 17 sends a RCell-Req signal indicating whether or not the reception is possible. The Rx transmission control block 18 transmits the signals of the synchronization signal (RCell-Sync), the frame signal (RCell-Frm), and the clock signal (RCell-Clk) at the same time. The ATM cell, which is a data cell (RCell-Dat), is supplied from the buffer 19 to the Rx reception buffer 16 and the Rx reception control block 17.
ATM 셀 처리 블럭(20)은 Rx 수신 제어 블럭(17)으로부터 Rx 수신 버퍼(16)에 ATM 셀이 저장됐음을 통보받아 이를 수신하여 ATM 헤더에 대한 가상 채널의 적합성 유무를 점검하는 동시에 ALL 헤더를 점검하여 서비스 데이타를 복원하는 기능을 한다.The ATM cell processing block 20 receives the notification from the Rx reception control block 17 that the ATM cell has been stored in the Rx reception buffer 16, checks whether the virtual channel is compatible with the ATM header, and checks the ALL header. It checks and restores service data.
ATM 셀 처리 블럭(20)의 세부적인 구성과 기능은 본 출원인이기 출원한 바 있는 선출원 발명(출원번호; 92-24193)에 명시되 있다.The detailed configuration and function of the ATM cell processing block 20 is specified in the earlier application (Application No. 92-24193) filed by the applicant.
제2도는 ALL에서의 송신 동작에 따른 처리 흐름도로서, ALL에서의 송신 과정은 Tx송신 제어 블럭(13)에 의해 시작된다.2 is a process flow diagram according to the transmission operation in ALL, and the transmission process in ALL is started by the Tx transmission control block 13.
송신 과정이 시작되고 (31) 카운터를 초기화하여 카운터값을 1로 설정한 후 (CNT='1')(32), 셀 구동프레임이 1인지(Cell_Frm='1')의 여부를 조사한다(33). 조사 결과 셀 구동 프레임이 1이 아니면 리턴하고, 셀 프레임이 1일 경우 (Cell_Frm='1')입력되는 데이타와 셀 클럭(Cell_Clk)에 따라 카운터를 1 증가시킨다 (CNT=CNT＋1)(34).The transmission process starts (31) and initializes the counter to set the counter value to 1 (CNT = '1') 32, and checks whether the cell drive frame is 1 (Cell_Frm = '1') ( 33). If the cell drive frame is not 1, the result is returned. If the cell frame is 1 (Cell_Frm = '1'), the counter is incremented by 1 according to the input data and the cell clock (Cell_Clk) (CNT = CNT + 1) (34).
이에 따라 카운터 값이 증가되지만 셀 프레임이 0일 경우는 카운터 값의 증가없이 카운터 값은 1을 유지한다.As a result, the counter value is increased, but when the cell frame is 0, the counter value remains 1 without increasing the counter value.
그리고 카운터 값을 판정하여 그 값이 53(옥텟)이 되었는지(CNT='53')를 조사하여(35), '53'일 경우 하나의 ATM셀이 생성되었음을 알고 Tx송신 버퍼에 저장한 후(36), ATM계층을 송신 가능 여부를 TCell-Req신호에 따라 송신 판정하여(36), 셀단위로 송신을 하거나(38)송신 대기가 요구되는 경우 송신 버퍼에 저장하는 단계로 귀환하며, 송신 동작을 마치는(39)동시에 처음으로 리턴한다.After determining the counter value and checking whether the value is 53 (octet) (CNT = '53 ') (35), if it is' 53', one ATM cell is generated and stored in the Tx transmission buffer ( 36), it is determined whether the ATM layer can be transmitted according to the TCell-Req signal (36), and the transmission is performed on a cell-by-cell basis (38). (39) returns to the beginning at the same time.
제3도를 ALL에서의 수신 동작에 따라 처리 흐름도로서, ALL에서의 수신 과정은 Rx 송신 제어 블럭(13)에 의해 시작된다.3 is a process flow diagram according to the reception operation in ALL, where the reception process in ALL is started by the Rx transmission control block 13.
수신 과정이 시작되며(41), 초기화 단계(42)의에서 카운터값을 1로 설정한 후(CNT='1'),AAL 계층으로의 송신가능 여부를 RCell-Req 신호에 따라 수신할 것인지를 조사하고(43), 수신이 불가능할 경우 초기화 단계(42)로 귀환하여 송신 가능할 때까지 대기한다.The reception process starts (41), and after setting the counter value to 1 in the initialization step 42 (CNT = '1'), it is determined whether to transmit to the AAL layer according to the RCell-Req signal. If the reception is impossible (43), it returns to the initialization step 42 and waits until transmission is possible.
수신이 가능하면 셀 구동프레임이 1인지(RCell-Frm='1')의 여부를 조사하여(44), '1'일 경우 입력되는 데이타와 셀 클럭(RCell-Clk)에 따라 카운터 값을 증가시키고(45), 카운터 값이 53이 되었는지(CNT='53')의 여부를 조사하여(46), '53'이 되었을 경우 하나의 ATM셀이 수신되었음을 알고 Rx 수신 버퍼에 저장한 후(47), 초기화 단계(42)으로 귀환하는 동시에 셀을 수신하여(48)ATM헤더에 대한 가상 채널, 페이로드타입, 셀우선순위 등에 대한 점검과 AAL-PDU에 대한 처리를 하여 서비스 데이타를 복원하고 종료한다.(49)If reception is possible, it is checked whether the cell drive frame is 1 (RCell-Frm = '1') (44), and if it is '1', the counter value is increased according to the input data and the cell clock (RCell-Clk). (45), check whether the counter value is 53 (CNT = '53 ') (46), if it becomes' 53', know that one ATM cell has been received and store it in the Rx reception buffer (47). At the same time, the cell is received (48), the virtual channel for the ATM header, the payload type, the cell priority, and the AAL-PDU are processed to restore and terminate the service data. (49)
제4도는 송수신시 전송되는 각 신호의 타이밍도이다.4 is a timing diagram of each signal transmitted during transmission and reception.
도면에 도시된 각 신호의 내역은 다음과 같다.Details of each signal shown in the figure are as follows.
Byte-Clk : 155.52 MHz의 속도에 대한 바이트클럭으로서 19.44MHz의 속도를 갖는다.Byte-Clk: A byte clock for a speed of 155.52 MHz with a speed of 19.44 MHz.
TCell-Req : 수신측(ATM 계층)에서 수신여부를 송신측(AAL 계층)에 통보하는 신호TCell-Req: Signal that notifies the sending side (AAL layer) whether the receiving side (ATM layer) receives
TCell-Sync : 송신셀의 시작을 알리는 신호TCell-Sync: Signal to start transmission cell
TCell-Frm: 송신셀의 전송에 대한 유효구간임을 알리는 신호TCell-Frm: Signal indicating valid section for transmission of transmitting cell
TCell-Clk : Byte-Clk, TCell-Frm의 조합과, TCell-Sync에 동기되어 TCell-Frm구간에서만 구동클럭을 제공하는 신호TCell-Clk: Combination of Byte-Clk and TCell-Frm, and signal that provides driving clock only in TCell-Frm section in synchronization with TCell-Sync.
TCell-Dat : Tcell-Sync, TCell-Frm, TCell-Clk에 동기되어 전달되는 8비트 데이타 신호TCell-Dat: 8-bit data signal transmitted in synchronization with Tcell-Sync, TCell-Frm, and TCell-Clk
RCell-Req : 수신측(AAL 계층)에서 수신여부를 송신측(ATM 계층)에 통보하는 신호RCell-Req: Signal that notifies the sending side (ATM layer) of the receiving side (AAL layer).
RCell-Frm : 수신셀의 전송에 대한 유효구간임을 알리는 신호RCell-Frm: Signal indicating valid section for transmission of receiving cell
RCell-Clk : Byte-Clk, RCell-Frm의 조합과 RCell-Sync에 동기되어 RCell-Frm구간에서만 구동클럭을 제공하는 신호RCell-Clk: Signal that provides driving clock only in RCell-Frm section in synchronization with Byte-Clk, RCell-Frm and RCell-Sync.
RCell-Dat : RCell-Sync, RCell-Frm, RCell-Clk에 동기되어 전달되는 8비트 데이타 신호RCell-Dat: 8-bit data signal transmitted in synchronization with RCell-Sync, RCell-Frm, and RCell-Clk
따라서, 상기한 바와 같이 본 발명은 비동기적 서비스 데이타의 발생에 의해 기존의 동기방식에 의해 인터페이스하는 방식과는 달리 가변적으로 발생하는 서비스 셀을 ATM계층에 전송하는 것과 상대 계층에서의 수신여부를 판정받아 송수신하므로 버퍼의 오버플로우로 인한 셀 손실을 방지하며, 셀의 유효구간만을 알리는 T/RCell-Frm과 프레임 구간동안에만 클럭을 제공하는 T/RCell-Clk신호에 의해 클럭과 입력 인에이블 신호에 의해 구동되는 버퍼와 클럭에 의해서만 구동되는 버퍼들에 동시에 사용되어 비동기로 전송되는 ATM셀들을 AAL 계층과 ATM계층에서 접속하는 수용할 수 있는 장점이 있다.Therefore, as described above, the present invention, unlike the method of interfacing by the conventional synchronous method by the generation of asynchronous service data, transmits a service cell that occurs variably to the ATM layer and determines whether reception is performed at the other layer. It receives and transmits and prevents cell loss due to overflow of the buffer.T / RCell-Frm, which informs only the effective period of the cell, and T / RCell-Clk signal, which provides a clock only during the frame period, is applied to the clock and input enable signals. There is an advantage that can be used to connect ATM cells that are used asynchronously to the buffer driven by the clock and the buffer driven only by the clock at the AAL layer and the ATM layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930027885A KR960004716B1 (en) | 1993-12-15 | 1993-12-15 | Matching control device between the Asynchronous Transfer Mode (ATM) adaptation layer and the Asynchronous Transfer mode (ATM) layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930027885A KR960004716B1 (en) | 1993-12-15 | 1993-12-15 | Matching control device between the Asynchronous Transfer Mode (ATM) adaptation layer and the Asynchronous Transfer mode (ATM) layer |
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| Publication Number | Publication Date |
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| KR950022432A KR950022432A (en) | 1995-07-28 |
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